1313129 (1) 九、發明說明 【發明所屬之技術領域】 本發明關係於影像資料處理，更明確地說，本 係一種有效且低成本處理來自影像感應器的資料的 裝置。 【先前技術】 Φ 因爲影像感應器可以被整合入各種電子產品中 ，影像感應器可以應用至各種應用，例如數位相機 攝影機、個人電腦（PC )攝影機、USB攝影機等之 要影像感應器的攝影機中。取決於該特定應用而定 感應器有各種的陣列大小。超出百萬像素的高解析 應器係被用於數位相機中，而其他低解析度CIF、 或SVGA格式則被用於保全攝影機或PC攝影機的 〇 φ 通用串列匯流排（USB )爲一種電腦匯流排架 係用作爲資訊處理裝置’例如週邊電腦裝置至個人 PC)間之連接。爲了以下的理由，想要於週邊裝置 使用U S B。桌一 ’各種範圍的資訊處理裝置可以經 加以互連至其他資訊處理裝置，例如PC的鍵盤、 印表機、掃描器、數據機、聲音裝置及視訊裝置均 由USB加以連接。第一，USB謹使用單一連接器 即可完成與其他週邊裝置的連接。第三，USB可自 裝置的連結’及軟體可自動重組該裝置，並可立即 發明關 方法與 ，所以 、數位 所有需 ，影像 影像感 VGA、 應用中 構，其 電腦（ 互連中 由USB 滑鼠、 可以經 類型， 動檢測 使用， (2) 1313129 而不必使用者介入。 然而，在USB 2.0協定下，通常1毫秒間距 以傳輸最多60000位元組之資料。此一傳輸限制 足以應付持續成長的資料量。業界都想要更快速 置傳輸資料到所連接的PC上。但，在很多情形 以在犧牲影像資料解析度的代價下，來取得較高 度。即’可以藉由丟棄部份資料，來重新製作被 的大小’以換取更縮短資料取得之時間。例如， 應器取得影像資料時，如何使影像感應器工廠或 中’以USB進行快速之驗證、評估、展示及檢 應器變得更加重要。 【發明內容】 本發明提供一種方法與裝置，用以更有效並 效益的方法，來獲取影像。本發明的影像獲取的 適用於一般目的影像感應器。 依據本發明之一種影像獲取裝置，包含：一 器；一資料處理塊，連接以接收來自影像感應器 料，該資料處理塊被架構以一選定因數，來下P 一資料儲存方塊，連接至該資料處理塊；及一控 接至該資料處理塊與該影像感應器。 依據本發明之影像獲取技術的解析度雖然低 術，但其顯著地降低硬體複雜性並完成了更有效 施法。因此，本發明的影像資料獲取技術對於不 的圖框可 明顯並不 由週邊裝 下，也可 之傳輸速 傳送資料 由影像感 開發中心 查影像感 符合成本 技術特別 影像感應 的影像資 我彩色値； 制器，連 於傳統技 的裝置實 需要最大 -5- (3) 1313129 壓縮比的應用，提供了另一種選擇。 【實施方式] 的 示 或 陣 5 料 進 影 至 排 匯 係 像 PC 他 上 在 參考第1圖，顯示本發明之影像資料獲取裝置10 例示裝置方塊圖。影像感應器12從透鏡及支撐件（未 出）接收影像。該影像感應器12可以爲CMOS型’ CCD型。依據本發明之影像資料獲取乃以現場可程式閘 列（FPGA) 16或特殊應用積體電路（ASIC)加以實施 該現場可程式閘陣列接收來自影像感應器1 2的影像資 。然後’例如，動態隨機存取記憶體（DRAM )的（先 先出）FIFO緩衝器18被連接至FPGA16並用以儲存該 像資料，以供後續的資料處理。一控制器20被連接 FPGA16及影像感應器12，以完成至通用串列匯流 USB22的介面。該控制器20係例如，USB (通用串列 流排）控制器。 影像獲取裝置10也包含有電源電壓調整器14，其 爲USB控制器20所控制，並用以供電給FPGA16與影 感應器12。USB22也可以將影像獲取裝置1〇連接至主 ，該主PC包含有USB裝置驅動器、解壓縮軟體等等其 資源。於第1圖所示之裝置中，由於影像獲取裝置大小 之顯著減小’使得本發明有可能將獲取硬體與控制器作 同一晶片上。因此，可以顯著降低製造成本。 FPGA16包含影像處理軟體（未示出）儲存在永久記 憶體中。FPGA16包含一緩衝器（未示出）或其他類型的 (4) 1313129 提供記憶儲存的記憶體及/或工作RAM記憶體 (未示出）爲影像感應器12戶斤讀取時’有關 像資料爲影像感應器12所即時輸出。當感應器 像資料讀取的同時，或不久之後，FPGA16 ^ FPGA16處理自影像感應器12所輸出之影像資 可以例如被儲存在FlF〇緩衝器18中’成爲 ，或者，在FPGA16內的板上緩衝器（未示出 檔1 9爲具有較原始影像爲小尺寸的影像資料 像檔1 9係爲影像處理軟體所使用’以找出影 區域，而不必一像素一像素地或一位元一位元 資料。影像檔1 9在資料被影像感應器1 2所讀 生。 以第1圖所示之影像獲取裝置10，一操作 PC，經由USB22發出一指令’利用USB控制| 規劃FPGA16。規劃後的FPGA16可用來控制 設定。例如，如果操作員想要設定硬體模g Reset )接腳爲高（HI)，則他可以自pC送出 ’然後’硬體模組的重置接腳被設定爲HI。 FPGA有六種操作模式，即： (1 )全影像輸出模式； (2)貝爾（Bayer)格式影像切割模式； L3 ) YCbCr影像切割模式； (4 )下除模式； (5 )測試圖案模式，及 。當一目檩 於目標的影 :12完成影 俞出資料。 料。此資料 -影像檔1 9 )中。影像 壓縮檔。影 像中之想要 地分析影像 出的同時產 員可以控制 蓉20來重新 硬體模組的 且的重置（ 一控制命令 (5) 1313129 (6 ) SAV/EAV 模式。 於全影像輸出模式中’ 一Jf定彩色値係由一特定像素 抽出’而於該像素的其他彩色値則由鄰近該像素的其他像 素抽出。 於貝爾格式影像切割模式中’例如輸入模組爲2M ( 2048x1536)的影像，而想要自（500，5〇〇)開始取得影 像。則操作貝從PC端輸入命令’’change clipping mode， . X = 500，Y = 500”，則FPGA將取得此命令，並開始計數圖 框有效信號、線有效信號及像素時脈信號。然後，截取（ 500，500) -( 1140，980)的資料給 FIFO RAM，然後， 將FIFO RAM內的資料送至USB。等待發送完成，則再次 開始。因此，操作員可以取得即時VGA影像。 於YCbCr影像切割模式中，其作業方式於前一貝爾格 式影像切割模式相同，因此，不再重覆。 於下除模式中，FPGA建立一壓縮影像，其係爲原來 > 陣列大小的一半（1 /2 )大小。這具有將整個影像資料壓 縮爲資料的一半圖框大小的作用。這損及顏色正確性及對 比，以及，影像品質，但簡化了實施彩色抽取功能所需的 硬體。取決於應用所需之影像彩色品質’本發明也可以甚 至提供如第3圖所示之1/4或1/8圖框彩色抽取的資料壓 縮。 用以依據本發明之測試影像感應器的流程係如第2圖 所示。流程的第一步驟s 1爲藉由設定重置接腳、輸出致 能接腳、及備用接腳爲高，而加以啓始硬體模組。然後， -8 - (6) 1313129 在步驟S 2，執行一檢測操作’以檢測是否有影像感應器 。如果結果爲否，則流程將停止。如果步驟S 2中之結果 爲是’則在步驟S3，操作員自PC送出包含位址資料（X ，Y )的命令給FPGA，以決定所採用的操作模式。在步驟 S 4 ’圖框有效、線有效、像素時脈信號被]p p 〇 a所計數， 然後被儲存在FIFO中’然後，FPGA自FIFO取得圖框資 料並經由USB送至PC，以檢查是否圖框資料爲可接受。 如果不可接受’則圖框資料被放棄，流程回到步驟S 3。 然後’步驟再次重覆’直到找到一可接受影像並在步驟 S 5被顯示爲止。另外，也可以再回到步驟3 4，以取得另 一資料並加以檢測，如虛線所示。一種用以定義主動影像 區域的圖框有效信號操作的時間圖係如第4圖所示。當 FPGA檢測出圖框有效的下降緣時，一特殊旗標經由usb 被傳送至PC。PC然後接收此特殊旗標並檢查是否資料大 小可接受否。如果’可接受則圖框被顯示，否則放棄該圖 框。 於SAV/EAV模式中，來自TV' VCR、VCD或DVD 的合成視訊丨g號被轉換爲BT601/605，Y/U/V格式的像素 資料。一 SAV (作用視訊的開始）碼被提供以定義一影像 的開始作用像素，及一 E A V (作用視訊的結束）碼被提供 以定義一影像的結束作用像素。 第3圖顯示爲本發明所用之例示通訊協定。該通訊協 疋包a模式功能指令部4 0及一控制命令部5 〇。該模式 功能指令部40包含有六個可選功能模式，其下方爲其命 -9 _ (7) 1313129 令碼。控制命令部5〇控制FPGA模組的操作的整個流程 。藉由該通訊協定，操作員可以自PC下命令給FPGA，以 決定自何處切割影像；或者，控制電源、I/O、SPI、PWM 的狀態。 ^ 雖然本發明已經參考較佳實施例加以說明，但可以了 解的是本案並不限定於所述之細節。各種的替代或修改可 以在爲熟習於本技藝者所了解。因此，本案之範圍係爲隨 t 附之申請專利範圍所界定。 【圖式簡單說明】 第1圖爲使用本發明之影像獲取技術的.影像感應器測 試裝置的方塊圖； 第2圖爲依據本發明的軟體操作流程圖； 第3圖爲本發明所用之通訊協定的不意圖；及 第4圖爲顯示在第2圖之方法與裝置的邏輯時序圖。 【主要元件之符號說明】 10 :影像獲取裝置 12 :影像感應器 1 4 :電壓調整器 1 6 :現場可程式閘陣列 1 8 :先進先出緩衝器 1 9 :影像檔 20 :控制器 -10- 1313129 (8) 22 :通用串列匯流排 40 :模式功能指令部 5 0 :控制命令部1313129 (1) Description of the Invention [Technical Field] The present invention relates to image data processing, and more particularly to an apparatus for efficiently and inexpensively processing data from an image sensor. [Prior Art] Φ Since the image sensor can be integrated into various electronic products, the image sensor can be applied to various applications such as a digital camera, a personal computer (PC) camera, a USB camera, etc., which are to be image sensors. . Depending on the particular application, the sensor has a variety of array sizes. High resolution devices exceeding megapixels are used in digital cameras, while other low resolution CIF, or SVGA formats are used to preserve the 〇φ universal serial bus (USB) of a camera or PC camera as a computer. The busbar frame is used as a connection between information processing devices such as peripheral computer devices to personal PCs. For the following reasons, it is desirable to use U S B for peripheral devices. Table 1 'A wide range of information processing devices can be interconnected to other information processing devices, such as PC keyboards, printers, scanners, modems, audio devices, and video devices that are connected by USB. First, USB uses a single connector to connect to other peripherals. Third, the USB can be connected to the device' and the software can automatically reorganize the device, and can immediately invent the method and, therefore, digital all needs, video image sense VGA, application medium structure, its computer (interconnected by USB slide The mouse can be typed and used for detection, (2) 1313129 without user intervention. However, under the USB 2.0 protocol, usually 1 millisecond spacing is used to transmit data of up to 60,000 bytes. This transmission limit is sufficient for sustained growth. The amount of data. The industry wants to transfer data to the connected PC more quickly. However, in many cases, it is higher at the expense of the resolution of the image data. That is, by discarding some data. , to re-create the size of the quilt in exchange for more time to obtain data. For example, how to make the image sensor factory or the 'fast verification, evaluation, display and detector change with USB when the image data is obtained? More important. SUMMARY OF THE INVENTION The present invention provides a method and apparatus for obtaining images by a more efficient and effective method. The image acquisition device is suitable for a general purpose image sensor. An image acquisition device according to the present invention comprises: a device; a data processing block connected to receive from an image sensor, the data processing block being structured with a selected factor, P is a data storage block connected to the data processing block; and a control is connected to the data processing block and the image sensor. The resolution of the image acquisition technology according to the present invention is low, but it significantly reduces the hard The complexity of the body is completed and the more effective casting method is completed. Therefore, the image data acquisition technology of the present invention can obviously not be installed by the periphery, and the transmission data can be transmitted by the image sensing development center. The special image-sensing image is color-coded; the device, which is connected to the traditional technology, requires a maximum of -5 - (3) 1313129 compression ratio, providing another option. Into the image-receiving system like PC, with reference to FIG. 1 showing an exemplary device of the image data acquiring device 10 of the present invention The image sensor 12 receives images from the lens and the support member (not shown). The image sensor 12 can be of the CMOS type 'CCD type. The image data acquisition according to the present invention is a field programmable gate array (FPGA) 16 Or a special application integrated circuit (ASIC) to implement the field programmable gate array to receive image data from the image sensor 12. Then, for example, a first random access memory (DRAM) (first in first out) FIFO buffer 18 is connected to the FPGA 16 and used to store the image data for subsequent data processing. A controller 20 is coupled to the FPGA 16 and the image sensor 12 to complete the interface to the universal serial bus USB 22. The controller 20 is, for example, a USB (Universal Serial Bank) controller. The image acquisition device 10 also includes a power supply voltage regulator 14 that is controlled by the USB controller 20 and that supplies power to the FPGA 16 and the shadow sensor 12. The USB 22 can also connect the image capture device 1 to the host, which contains the resources of the USB device driver, the decompression software, and the like. In the apparatus shown in Fig. 1, since the size of the image capturing device is significantly reduced, it is possible for the present invention to acquire the hard body on the same wafer as the controller. Therefore, the manufacturing cost can be significantly reduced. The FPGA 16 includes image processing software (not shown) stored in the permanent memory. The FPGA 16 includes a buffer (not shown) or other type of (4) 1313129 memory and/or working RAM memory (not shown) that provides memory storage for the image sensor 12 when reading the image data. Instant output for the image sensor 12. At the same time as the sensor reads the data, or soon after, the image data processed by the FPGA 16^FPGA 16 from the image sensor 12 can be stored, for example, in the FlF buffer 18, or on the board within the FPGA 16. The buffer (not shown in the file 19 is a video data file having a smaller size than the original image is used by the image processing software to find the shadow area, without one pixel by one pixel or one bit one The bit file data is read by the image sensor 12 in the image file. The image acquiring device 10 shown in Fig. 1 operates the PC and issues an instruction via the USB 22 to use the USB control to plan the FPGA 16. Planning The latter FPGA16 can be used to control the settings. For example, if the operator wants to set the hardware mode g Reset) the pin is high (HI), he can send the 'and then' the reset module of the hardware module is set from pC. It is HI. The FPGA has six modes of operation, namely: (1) full image output mode; (2) Bayer format image cutting mode; L3) YCbCr image cutting mode; (4) lower mode; (5) test pattern mode, and. When you see the shadow of the target: 12 Complete the shadow. material. This information - image file 1 9). Image compression file. In the image, the producer can control the image to re-harden the module (a control command (5) 1313129 (6) SAV/EAV mode. In the full image output mode. 'A Jf fixed color system is extracted by a specific pixel' and other color pixels of the pixel are extracted by other pixels adjacent to the pixel. In the Bell format image cutting mode, for example, the input module is 2M (2048x1536) image. , and want to get the image from (500,5〇〇). Then enter the command from the PC and enter the command ''change clipping mode, . X = 500, Y = 500”, then the FPGA will get this command and start counting. Frame effective signal, line valid signal and pixel clock signal. Then, intercept (500,500) - (1140,980) data to the FIFO RAM, and then send the data in the FIFO RAM to the USB. Wait for the transmission to complete, Then start again. Therefore, the operator can get the instant VGA image. In the YCbCr image cutting mode, the operation mode is the same as the previous Bell format image cutting mode, so it is not repeated. In the lower division mode, FP The GA creates a compressed image that is half the size of the original > size (1 /2). This has the effect of compressing the entire image data into half the size of the data. This compromises color correctness and contrast, and , image quality, but simplifies the hardware required to implement the color extraction function. Depending on the image color quality required for the application, the present invention can even provide 1/4 or 1/8 frame color as shown in Fig. 3. The extracted data is compressed. The flow of the test image sensor according to the present invention is as shown in Fig. 2. The first step s 1 of the flow is by setting a reset pin, an output enable pin, and an alternate connection. The foot is high and the hardware module is started. Then, -8 - (6) 1313129 In step S2, a detection operation ' is performed to detect whether there is an image sensor. If the result is no, the flow will stop. If the result in step S2 is YES, then in step S3, the operator sends a command containing the address data (X, Y) from the PC to the FPGA to determine the mode of operation employed. In step S4 'the frame is valid. , line valid, pixel clock signal is]p p 〇a is counted and then stored in the FIFO'. Then, the FPGA takes the frame data from the FIFO and sends it to the PC via USB to check if the frame data is acceptable. If it is not acceptable, the frame data is discarded. The flow returns to step S3. Then the 'step is repeated again' until an acceptable image is found and displayed in step S5. Alternatively, it is also possible to return to step 34 to obtain another data and detect it, such as As shown by the dotted line, a time chart for defining the effective signal operation of the frame of the active image area is shown in Fig. 4. When the FPGA detects a valid falling edge of the frame, a special flag is transmitted to the PC via usb. The PC then receives this special flag and checks if the data size is acceptable or not. If ' acceptable, the frame is displayed, otherwise the frame is discarded. In SAV/EAV mode, the composite video from the TV' VCR, VCD or DVD is converted to pixel data in BT601/605, Y/U/V format. A SAV (Start of Video) code is provided to define the start-action pixel of an image, and an E A V (End of Action Video) code is provided to define the end-effect pixel of an image. Figure 3 shows an exemplary communication protocol used in the present invention. The communication protocol packs a mode function command unit 40 and a control command unit 5 〇. The mode function instructing section 40 includes six optional function modes, the lower side of which is its -9 _ (7) 1313129 code. The control command unit 5 controls the entire flow of the operation of the FPGA module. With this protocol, the operator can command the FPGA from the PC to determine where to cut the image; or, to control the state of the power supply, I/O, SPI, and PWM. Although the present invention has been described with reference to the preferred embodiments, it is understood that the present invention is not limited to the details. Various alternatives or modifications may be apparent to those skilled in the art. Therefore, the scope of this case is defined by the scope of the patent application attached to t. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an image sensor testing apparatus using the image capturing technology of the present invention; FIG. 2 is a software operation flowchart according to the present invention; and FIG. 3 is a communication used in the present invention. The intent of the agreement; and Figure 4 is a logical timing diagram of the method and apparatus shown in Figure 2. [Description of Symbols of Main Components] 10: Image Acquisition Device 12: Image Sensor 1 4: Voltage Regulator 1 6: Field Programmable Gate Array 1 8: First In First Out Buffer 1 9 : Image File 20: Controller-10 - 1313129 (8) 22 : Universal serial bus 40 : Mode function command unit 5 0 : Control command unit