1313103 六、發明說明： 【發明所屬之技術領域】 尤指一種混合鎖存正反哭。 本發明係關於一種正反哭 【先前技術】 ％ 刖、'、電晶體液晶顯示器（TFT-LCD)已逐漸成為 種數位產品之標準輸出設備，然， 驅 電路以保證其穩定I作。 田叫動 通常’液晶顯示器驅動電路可以被分為二部份 極驅動電路與間極驅動電路。源極驅動電路用於二原; TFT-LCD每一圖元單元灰 於控制 每一圖元單k⑽ 咖_路_於控制 母圖το早兀之知描。二種驅動電路均包括應用移位 器作為核心電路單元，㈣存器與正反H係用作移位^ 器之通常選擇。正反器有許多種類型，例如SR正反器Tt 二::二:：反^及丁正反^其中^正反器最常用於 移4寄存裔中。因此’ D正反器亦常作為核心電路單 於TFT-LCD驅動電路中。 然，先前技術D正反器具有許多缺點，其具有長穿透 週期及時脈訊號偏移，為此，業内發明一種混合鎖存正反 器（Hybrid Latch Flip-Flop ’ HLFF)以解決此類問題。 《ISSCC技術論文摘要》1996年刊第138-139頁揭示 一種混合鎖存正反器’如第一圖所示，該先前技術混合鎖 存正反器100包括：一時鍾輸入節點1〇；[，一反轉單元11〇、 一正反器單元130、一缓衝單元150、一數據輸入節點1〇3 及一數據輸出節點105。該正反器單元U0包括：一數據 採樣單元140及一保持單元149。 1313103 該反轉單元110包括：一第一反相器ill、一第二反相 器112和一第三反相器113。其中，該第一反相器111之輸 入端與時脈輸入節點101相連接，該第一反相器ill之輸 出端連接至該第二反相器112之輸入端，該第二反相器H2 之輸出端連接至該第三反相器113之輸入端，該第三反相 器113之輸出端連接至該正反器單元130。 該數據採樣單元140包括4個PMOS型電晶體（即，一 第一 PMOS型電晶體131、一第二PMOS型電晶體132、 一第三PMOS型電晶體I33和一第四PMOS型電晶體13句 與6個NMOS型電晶體（即，一第一 NMOS型電晶體141、 一第二NMOS型電晶體142、一第三NMOS型電晶體143、 一第四NMOS型電晶體144、一第五NMOS型電晶體145 和一第六NMOS型電晶體146)。其中，該第一、二、三、 四PM0S型電晶體131、132、133、134之源極均連接至一 電源節點1〇4(即源極電壓VDD節點）。該第一 pM〇s型電 晶體131之閘極，第一 NM0S型電晶體141之閘極及第四 NMOS型電晶體144之閘極均連接至時脈輸入節點1〇1， 第一 PM0S型電晶體132之閘極及第二NM〇s型電晶體 142之閘極均連接至數據輸入節點1〇3。第三反相器113之 輸出端連接至第三NMOS型電晶體143之閘極°、第六 NM〇S型電晶體146之閘極及第三；pM〇s型電晶體133之 閘極。第一 PM0S型電晶體131之汲極分別連接至第一 NMOS，電晶體141之汲極、第二pM〇s型電晶體之 及極、第三PM〇s型電晶體133之汲極、第四型電 晶體134之閘極、第五NM0S型電晶體145之閘極。第一 1313103 腿OS型電晶體141之源極連接至第二腿塑電晶體 142至之汲極。第二NM〇s型電晶體之源極連接至第三 丽⑽型電晶體之沒極。第四PM0S型電晶體134之汲極 連接至第四NM0S型電晶體144之汲極。第四NM〇s型電 晶體144之源極連極至第五NM〇s型電晶體ι45之汲極。 第五NM0S型電晶體145之源極連接至第六nM〇s型電晶 體146之汲極。第三NM〇s型電晶體及第六ΝΜ〇§型， 電日日體146之源極均接地（零伏特）。 - 。該保持單元149包括一第四反相器147和一第五反相 _ 器148。其中，第四反相器147之輸入端及第五反相器148 之輸出端連接至第四PM0S型電晶體134之汲極，同時第 四反相器147之輸出端及第五反相器148之輸入端連接至 、 缓衝單元150。 該緩衝單元15〇包括一第六反相器151。其中，第六 反相器151輪入端連接至第四反相器147之輸出端，第六 反相器151輸出端連接至數據輸出節點105。 施加一時脈訊號於時脈輸入節點1〇1，時脈訊號為低籲 電壓時，第一 NM0S型電晶體141及第四NM〇S型電晶體 144關閉，第一PM0S型電晶體131開啟。反轉單元n〇 中三個反相器轉變時脈訊號之低電壓為高電壓，該高電壓 使第三NM0S型電晶體143及第六NM〇s型電晶體146 開啟，且第三：PM0S型電晶體133關閉。則如第一圖所示 之節點vi之電壓被充電至高電壓VDD，該高電壓關閉第 四PM0S型電晶體134，保持數據輸出節點1〇5之電壓值 不變。 6 1313103 時脈訊號正緣到來時’第一 NMOS型電晶體141及第 四NM0S型電晶體144開啟’第三NM0S型電晶體143 及第六NMOS型電晶體146延遲開啟狀態一段時間，該延 遲時間段由反轉單元11〇之延遲時間決定。假設數據輸入 節點103此時為低電壓，則第二PMOS型電晶體132開啟， 節點VI被充電至高電壓VDD，第五NMOS型電晶體145 開啟’且第四PMOS型電晶體134關閉，第四PMOS型電 晶體134源極通過第四、第五及第六NMOS型電晶體144、 145及146接地放電為零伏特。另一種情況，假設數據輸 入節點103此時為高電壓，第二NMOS型電晶體142開啟， 第二PMOS型電晶體132關閉，VI節點通過第四、第五及 第六NMOS型電晶體144、145及146接地放電為零伏特， 因V1為低電壓則第四PMOS型電晶體134開啟，第五 NM〇S型電晶體145關閉，第四PMOS型電晶體134之汲 極輸出高電壓至保持單元149，前述之時間段内，該正反 為單το 130視為開啟，數據輸入節點1〇3之數據可以被採 樣且鎖存。一旦第一圖中所示節點CKDB轉為低電壓後， VI與數據輸入節點103之連接減弱，該正反器單元13〇視 為關閉態。時脈負緣後第一 PMOS型電晶體131始終開啟 且保持節點VI之電壓為高電壓VDD，數據輸入節點1〇3 之數據不能被採樣。 第二圖所示係第一圖之先前技術混合鎖存正反器之工 作時序圖，其中V(D)、V(CLOCK)及V(Q)分別代表第一圖 中數據輸入節點1〇3、時脈輸入節點1〇1及數據輸: 〇5處之電壓波型圖。如第一圖及第二圖所示，數據輪出 3 l3l3l〇 前為低電壓’時脈正緣心處’數據輸入節 出數據輪入節點103之高電壓被採樣“ =據輸出㈣105從低電壓轉變為高電壓。η 2輸入郎點⑽為低電壓，數據輸出節點ι〇5為高電壓， 節點：點之低電壓被採樣且輪出，數據輪出 “ 105攸南電壓轉變為低電 彻為低電壓，數攄^電£ Tn+2刖，數據輸入節點 數據浐入〜= 5同為低電壓，Τη+2時， 持=; = ==採樣，數據輸出節… 輪出節點10S兔柄好數據輪入節點103為高電壓’數據 電壓被採樣，數脖i:Tn+3時，數據輸入節點103之高 Tn+4〜垂，輸出節點105從低電壓轉變為高電壓， 同為言引電题，據輸入即點103為高電壓，數據輸出節點105 數據^出* ’Τη+4時，數據輸入節點103之高電壓被採樣， 105保持為高電壓，Τη+5前，數據輸入節點 據於壓’數據輸出節點105為高電壓，Τη+5時，數 電』轉低電壓被採樣’數據輸出節點105從高 雷搞;〜吃口鎖存正反器用於液晶驅動電路時，每一行 混合鎖存^極都需分別使用—混合鎖存正反器1G()，但該 控二電路含電晶體數量較多，導致液晶驅動 制電路之h電歹過二’為 了適應TFT-LCD低功耗驅動控 耗。即，^，用於抓❹之混合鎖存正反器需較小功 但功耗較小要—電路同混合鎖存正反器100具有同樣功能 鎖存正反器 識於此，提供一種具有較小功耗之混合 1313103 實為必要。 【發明内容】 本發明之目的在於提供一種具有較小功耗之混合鎖存 正反器。 本發明解決技術問題之技術方案為：提供一種混合鎖 存正反器，其包括一時脈輸入節點、一正脈衝產生單元、 一正反器單元、一緩衝單元、一數據輸入節點、一數據輸 出節點，該正反器單元包括一採樣單元及一保持單元。該 時脈輸入節點連接至該正脈衝產生單元，該正脈衝產生單 元連接至該採樣單元，該採樣單元連接至該保持單元，該 保持單元連接至該緩衝單元，該數據輸入節點連接至該採 樣單元，該數據輸出節點連接至缓衝單元，該採樣單元包 括三個PMOS型電晶體及四個NMOS型電晶體，該三個 PMOS型電晶體為第一PMOS型電晶體、第二PMOS型電晶 體及第三PMOS型電晶體，該四個NMOS型電晶體為第一 NMOS型電晶體、第二NMOS型電晶體、第三NMOS型電晶 體及第四NMOS型電晶體，該第一PMOS型電晶體之源極、 第二PMOS型電晶體之源極及第三PMOS型電晶體之源極 均連接至電源節點VDD，第一PMOS型電晶體之閘極、第 二NMOS型電晶體之閘極及第四NMOS型電晶體之閘極均 連接至該正脈衝產生單元，第一 NMOS型電晶體之閘極及 第二PMOS型電晶體之閘極均連接至該數據輸入節點，第一 PMOS型電晶體之汲極、第二PMOS型電晶體之汲極、第三 PMOS型電晶體之閘極、第三NMOS型電晶體之閘極及第一 NMOS型電晶體之汲極均連接至一節點，第一NMOS型電晶 1313103 連接HNM()s型電晶體之練，第三N娜 接至第四N廳型電晶體线極，第二 地，第—體源極及第四NM0S型電晶體之源極均接 ^NM0S^1 脈衝產鎖存正反器’其包括一時脈輸入節點、-正 節點、、~正反器單元、一緩衝單元、一數據輸入 一保拄II _ 4輪出節點，該正反器單元包括一採樣單元及 兮元該時脈輸入節點連接至該正脈衝產生單元， 該保^產生早錢接雜純單元，該採樣單錢接至 節點連=該it單元連接至該緩衝單元’該數據輸入 元， ° 單70，§亥數據輸出節點連接至緩衝單 以採樣單元包括三個pM〇s型電晶體及四個NM〇s型電 ρμ〇:』ΡΜ〇_電晶體為第一PMO_電晶體、第二 曰許先贫電曰曰體及第：⑽⑽型電晶體，該四個NMOS型電 日曰體為第一 NMOS型雷b舻墙x _〇s型電θ曰體及ί 第二魏型電晶體、第三 日日興、日日 第四1^1^08型電晶體，該第一PMOS型電 之调4原極第一PM〇S型電晶體之源極及PMOS型電晶體 極及裳均連接至電源節點VDD，第—PMC>S型電晶體之閘 第-m^NMQS3Sll：晶體之閘極均連接至數據輸入節點， 電晶體之閘極、第二PM〇S型電晶體之閑極及 型電晶體之閘極均連接至該正 ， 第三m〇s型電曰髀？ PM0S型電晶體之汲極、 第—Nnu。j日日—之間極、第四舰⑽型電晶體之閘極及 第_S型電晶體之汲極均連接至一節點，第一醒⑽ 1313103 型電晶體之源極連接至第二NMOS型電晶體之汲極，第三 NMOS型電晶體之源極連接至第四NMOS型電晶體之汲 極，第二NMOS型電晶體之源極及第四NMOS型電晶體之源 極均接地，第三PMOS型電晶體之汲極及第三NMOS型電晶 體之汲極均連接至該保持單元。 一種混合鎖存正反器，其包括一時脈輸入節點、一正 脈衝產生單元、一正反器單元、一缓衝單元、一數據輸入 節點、一數據輸出節點，該正反器單元包括一採樣單元及 一保持單元。該時脈輸入節點連接至該正脈衝產生單元， 該正脈衝產生單元連接至該採樣單元，該採樣單元連接至 該保持單元，該保持單元連接至該緩衝單元，該數據輸入 節點連接至該採樣單元，該數據輸出節點連接至緩衝單 元，該採樣單元包括二PMOS型電晶體及四個NMOS型電晶 體，該二PMOS型電晶體為第一 PMOS型電晶體及第二 PMOS型電晶體，該四個NMOS型電晶體為第一NMOS型電 晶體、第二NMOS型電晶體、第三NMOS型電晶體及第四 NMOS型電晶體，第一PMOS型電晶體及第二PMOS型電晶 體之源極連接至電源節點VDD，第一PMOS型電晶體之閘 極、第一NMOS型電晶體之閘極及第三NMOS型電晶體之閘 極均連接至該正脈衝產生單元，第二NMOS型電晶體之閘 極連接至數據輸入節點，第一PMOS型電晶體之汲極、第二 PMOS型電晶體之閘極、第四NMOS型電晶體之閘極及第一 NMOS型電晶體之汲極均連接至一節點，第一NMOS型電晶 體之源極連接至第二NMOS型電晶體之汲極，第三NMOS 型電晶體之源極連接至第四NMOS型電晶體之汲極，第二 11 1313103 NMOS型電晶體之源極及第四NMOS型電晶體之源極均接 地，第二PMOS型電晶體之汲極及第三NMOS型電晶體之汲 極均連接至保持單元。 一種混合鎖存正反器，其包括一時脈輸入節點、一正 脈衝產生單元、一正反器單元、一緩衝單元、一數據輸入 節點、一數據輸出節點，該正反器單元包括一採樣單元及 一保持單元。該時脈輸入節點連接至該正脈衝產生單元， 該正脈衝產生單元連接至該採樣單元，該採樣單元連接至 該保持單元，該保持單元連接至該缓衝單元，該數據輸入 節點連接至該採樣單元，該數據輸出節點連接至緩衝單 元，該採樣單元包括二PMOS型電晶體及四個NMOS型電晶 體，該二PMOS型電晶體為第一 PMOS型電晶體及第二 PMOS型電晶體，該四個NMOS型電晶體為第一NMOS型電 晶體、第二NMOS型電晶體、第三NMOS型電晶體及第四 NMOS型電晶體，該第一PMOS型電晶體及第二PMOS型電 晶體之源極連接至電源節點VDD，第一PMOS型電晶體之 閘極及第二Ν Μ Ο S型電晶體之閘極均連接至數據輸入節 點，第一NMOS型電晶體之閘極及第四NMOS型電晶體之閘 極連接至該正脈衝產生單元，第一PMOS型電晶體之汲極、 第二PMOS型電晶體之閘極、第三NMOS型電晶體之閘極及 第一 NMOS型電晶體之汲極均連接至一節點，第一 NMOS 型電晶體之源極連接至第二NMOS型電晶體之汲極，第三 NMOS型電晶體之源極連接至第四NMOS型電晶體之汲 極，第二NMOS型電晶體之源極及第四NMOS型電晶體之源 極均接地，第二PMOS型電晶體之汲極及第三NMOS型電晶 12 1313103 體之及極均連接至保拉- 雙衝產生罩元；正緣觸發型、負緣觸發型或 於採^前技術相比’本發明之混合鎖存正反器之優點在 較先前技之單T電晶體數量 = 雖然該正脈衝產生單元具比先前技術混合 ^^ 轉單元更多之電晶體，但採用了脈衝產生 1=離脈衝產生單元和正反器單元，使該正脈衝 於液晶驅動電路中成為公共電路，所以該正脈衝 包括更多電晶體卻不會增加功耗。因此本發明之 此口、子正反器實現了比先前技術功耗低之目的。 本於=外t果採用雙緣觸發，不改變時脈頻率就可提高 -月之混δ鎖存正反器之資料輸容 單元資料傳輸容量之雙倍。 巧无别技術正反器 【實施方式】 框圖請為本發明之混合鎖存正反_之結構 _，该混合鎖存正反器包括··—時脈H點斯、 正脈衝產生皁7G310、—正反器單元33〇、 单疋33〇包括-採樣單元34〇及—保持單元349 汉盗 該時脈輸入節點3〇1連接至該正脈 通過節點302連接至該採樣U 知樣早兀340通過郎點3〇4連接 "亥 元349通過節點3〇6連接該緩衝單；^早元州，該保持單 平70350，該數擄輸入節點 13 1313103 ===至輯樣單元，紐據輪出節點撕連接至緩衝 該㈣衝產生單元可從時脈輸人節點謝接收時脈 ^後將接收狀時脈喊轉變為正脈衝訊號。該正 「讯喊由節點302施加於正反器單元33〇。該正反哭單元 3脚，採樣單《40由數據輸人節點3G3接 心脈衝產生單元則接收正脈衝訊號，採樣單據元^於^ 、正脈衝峰值時娜樣數據輸人節·3之數據訊號，即， 於每一正脈衝峰值時刻，如數據訊號為高電壓，該採樣單 = 340輸出一高電壓，相反，如果數據訊號為低電壓，則該 採樣單元34G輸出-低電壓。㈣後之數據通過節點綱ς 入至保持單元349。下一次數據採樣前，該保持單元349保 持從採樣單元340輸入之採樣結果，且從節點3〇6輸出該採 樣結果至緩衝單元350。緩衝單元35〇延遲及放大該採樣結 果，提供一更高驅動能力至後續電路。很明顯，該混合鎖 存正反器300可以實現正反器之基本功能。即，根據時脈訊 號採樣數據訊號且輸出數據訊號。本發明中混合鎖存正反 器300之正脈衝產生單元31〇可包括三種實施方式，該正反 器單元330可包括四種實施方式。 請參照第四圖’係第三圖混合鎖存正反器之正脈衝產 生單元第一貫施方式之電路圖。第四圖所示之正脈衝產生 單元410包括：一第一反相器411，一第二反相器412，一第 二反相器413 ’ 一第四反相器414及反及閘415。第一反相器 411之輸入端連接至時脈輸入節點401，其輸出端連接至第 二反相器412之輸入端。第二反相器之輸出端連接至第三反 14 .1313103 相器413之輸入端’弟二反相器之輸出端連接至反及閘々Μ 之一輸入端，反及閘之另一輪入端連接至時脈輸入節點 401，反及閘415之輸出端連接至第四反相器414之輸入端， 第四反相器414之輸出端連接至節點4〇2。第一反相器 及弟一反相斋412延遲來自時脈輸入節點之時脈訊號，第三 反相器413延遲且反轉來自時脈輸入節點4〇1之時脈訊號。 即，節點401之時脈訊號被第一反相器411、第二反相器412 及第二反相為413延遲且反轉後輸入至反及閘415之一輸入 端，節點401之時脈訊號同時輸入至反及閘415之另一輸入 端。即，時脈訊號之正緣或負緣被直接輸入反及閘415之一 輸入端，該正緣或負緣被延遲且反轉為負緣或正緣後輸入 至反及閘415之另一輸入端，每次接收到時脈正緣後，延遲 之負緣前，該反及閘415輸出一負電壓，連續起來則形成負 脈衝。該負脈衝經過第四反相器414後被反轉成正脈衝，且 輸出至節點402。然，每次接收到時脈負緣後，延遲之正緣 前，並無脈衝產生。 請參照第五圖’該圖係第三圖混合鎖存正反器之正脈 衝產生單元第二實施方式之電路圖。第五圖所示之正脈衝 產生單元5U)包括一第一反相器511，-第二反相器犯， -第二反相器513’ -第四反相器514及或閘516。第一反相 裔511之輸入端連接至時脈輸入節點5〇1，其輸出端連接至 第二反相器512之輸入端。第二反相器512之輸出端連接至 第三反相器513之輸入端’第三反相器513之輸出端連接至 或閘516之-輸人端’或閘516之另—輸人端連接至時脈輸 入節點501 ’或閘516之輪出端連接至第四反相器514之輸入 15 1313103 端，第四反相器514之輸出端連接至節點5〇2。第一反相器 511及第二反相器512延遲來自時脈輪入節點之時脈訊號， 第三反相器513延遲且反轉來自時脈輸入節點5〇1之時脈訊 號。即’節點501之時脈訊號被第—反相器511、第二反相 益512及第二反相器513延遲且反轉後輸入至或閘516之一 輸入端，節點501之時脈訊號同時輸入至或閘516之另一輸 入端。即，時脈訊號之正緣或負緣被直接輸入或閘516之二 輸入端’該正緣或負緣被延遲且反轉為負緣或正緣後輸入 至或閘516之另一輸入端，每次接收到時脈負緣後，延遲之 正緣前，或閘516輸出一負電壓，連續起來則形成負脈衝。 該負脈衝經過第四反相器514後被反轉成正脈衝，且輸出至 節點502。然，每次接收到時脈正緣後，延遲之負緣前，並 無脈衝產生。 請參照第六圖，係第三圖混合鎖存正反器之正脈衝產 生單元第三實施方式之電路圖。值得注意之處為：該實施 方式採用雙緣觸發型正脈衝產生單元後，不需改變時脈之 頻率即可倍增數據傳輸之容量。第六圖所示之正脈衝產生 單元610包括：一第一反相器611，一第二反相器612，一第 三反相器613, 一第四反相器614及互斥或閘617。第一反相 器611之輸入端連接至時脈輸入節點，其輸出端連接至 第一反相窃612之輸入端。第二反相器612之輸出端連接至 第三反相器613之輸入端，第三反相器613之輸出端連接至 互斥或閘617之一輸入端，互斥或閘617之另一輸入端連接 至時脈輸入節點601，互斥或閘617之輸出端連接至第四反 相器614之輸入端，第四反相器614之輸出端連接至節點 16 1313103 6〇2。第一反相器611及第二反相器612延遲央ό π 蛛水自時脈輪入節 點之時脈訊號’第三反相器613延遲且反轉來自時脈 ^1313103 VI. Description of the invention: [Technical field to which the invention pertains] In particular, a hybrid latch is crying. The present invention relates to a kind of positive and negative crying. [Prior Art] A liquid crystal display (TFT-LCD) has gradually become a standard output device for digital products. However, the circuit is driven to ensure its stability. Tian called the usual 'liquid crystal display driver circuit can be divided into two parts of the pole drive circuit and the interpole drive circuit. The source driver circuit is used for the two originals; each pixel unit of the TFT-LCD is grayed out to control each primitive single k(10) coffee_road_in the control mother image το early. Both drive circuits include an application shifter as the core circuit unit, and (4) registers and forward and reverse H systems are commonly used as shift controllers. There are many types of flip-flops, such as SR flip-flop Tt 2:: 2:: anti-^ and Ding Zheng anti-^ where the positive and negative counters are most commonly used in shifting 4 storage. Therefore, the 'D flip-flops are often used as the core circuit in the TFT-LCD driver circuit. However, the prior art D flip-flop has many disadvantages, which have a long penetration period and a timely pulse signal offset. To this end, the industry has invented a hybrid latch flip-flop (Hybrid Latch Flip-Flop 'HLFF) to solve this type of problem. problem. ISSCC Technical Paper Abstract, 1996, pp. 138-139, discloses a hybrid latch flip-flop as shown in the first figure. The prior art hybrid latch flip-flop 100 includes: a clock input node 1; An inversion unit 11A, a flip-flop unit 130, a buffer unit 150, a data input node 1〇3, and a data output node 105. The flip-flop unit U0 includes a data sampling unit 140 and a holding unit 149. The inverting unit 110 includes a first inverter ill, a second inverter 112, and a third inverter 113. The input end of the first inverter 111 is connected to the clock input node 101, and the output end of the first inverter ill is connected to the input end of the second inverter 112. The second inverter An output of H2 is coupled to an input of the third inverter 113, and an output of the third inverter 113 is coupled to the flip-flop unit 130. The data sampling unit 140 includes four PMOS type transistors (ie, a first PMOS type transistor 131, a second PMOS type transistor 132, a third PMOS type transistor I33, and a fourth PMOS type transistor 13). And six NMOS type transistors (ie, a first NMOS type transistor 141, a second NMOS type transistor 142, a third NMOS type transistor 143, a fourth NMOS type transistor 144, a fifth An NMOS type transistor 145 and a sixth NMOS type transistor 146), wherein the sources of the first, second, third, and fourth PMOS transistors 131, 132, 133, and 134 are all connected to a power supply node 1 〇 4 (ie, the source voltage VDD node). The gate of the first pM〇s-type transistor 131, the gate of the first NM0S transistor 141 and the gate of the fourth NMOS transistor 144 are all connected to the clock input. The node 1〇1, the gate of the first PMOS transistor 132 and the gate of the second NM 〇s transistor 142 are both connected to the data input node 1〇3. The output of the third inverter 113 is connected to the The gate of the three NMOS type transistor 143, the gate of the sixth NM〇S type transistor 146, and the third; the gate of the pM〇s type transistor 133. The first PM0S The drains of the transistors 131 are respectively connected to the first NMOS, the drain of the transistor 141, the sum of the second pM〇s type transistors, the drain of the third PM〇s type transistor 133, and the fourth type of transistor. The gate of 134, the gate of the fifth NM0S type transistor 145. The source of the first 1313103 leg OS type transistor 141 is connected to the second leg plastic transistor 142 to the drain. The second NM〇s type transistor The source is connected to the third pole of the third type (10) type transistor. The drain of the fourth PMOS type transistor 134 is connected to the drain of the fourth NMOS transistor 144. The source of the fourth NM 〇s type transistor 144 The pole is connected to the drain of the fifth NM〇s type transistor ι45. The source of the fifth NM0S type transistor 145 is connected to the drain of the sixth nM〇s type transistor 146. The third NM〇s type transistor And the sixth type, the source of the electric solar body 146 is grounded (zero volts). The holding unit 149 includes a fourth inverter 147 and a fifth inverter 148. The input of the fourth inverter 147 and the output of the fifth inverter 148 are connected to the drain of the fourth PMOS transistor 134, while the output of the fourth inverter 147 and the fifth inverter The input end of 148 is connected to the buffer unit 150. The buffer unit 15A includes a sixth inverter 151. The sixth inverter 151 is connected to the output end of the fourth inverter 147. The output of the six inverter 151 is connected to the data output node 105. A clock signal is applied to the clock input node 1〇1, and when the clock signal is a low voltage, the first NM0S transistor 141 and the fourth NM〇S type The transistor 144 is turned off, and the first PMOS type transistor 131 is turned on. The low voltage of the three inverters in the inverting unit n〇 is a high voltage, and the high voltage turns on the third NMOS transistor 143 and the sixth NM 〇s transistor 146, and the third: PM0S The type transistor 133 is turned off. Then, the voltage of the node vi as shown in the first figure is charged to the high voltage VDD, which turns off the fourth PMOS transistor 134, keeping the voltage value of the data output node 1〇5 unchanged. 6 1313103 When the positive edge of the clock signal arrives, 'the first NMOS type transistor 141 and the fourth NMOS type transistor 144 are turned on'. The third NM0S type transistor 143 and the sixth NMOS type transistor 146 are delayed in the on state for a period of time. The time period is determined by the delay time of the inversion unit 11〇. Assuming that the data input node 103 is low voltage at this time, the second PMOS type transistor 132 is turned on, the node VI is charged to the high voltage VDD, the fifth NMOS type transistor 145 is turned on, and the fourth PMOS type transistor 134 is turned off, and the fourth The source of the PMOS type transistor 134 is grounded to zero volts by the fourth, fifth, and sixth NMOS type transistors 144, 145, and 146. In another case, it is assumed that the data input node 103 is at a high voltage at this time, the second NMOS type transistor 142 is turned on, the second PMOS type transistor 132 is turned off, and the VI node is passed through the fourth, fifth, and sixth NMOS type transistors 144, 145 and 146 ground discharge is zero volt, the fourth PMOS type transistor 134 is turned on because V1 is low voltage, the fifth NM〇S type transistor 145 is turned off, and the drain of the fourth PMOS type transistor 134 is output high voltage to maintain The unit 149, in the foregoing time period, the positive and negative ones are regarded as being turned on, and the data of the data input node 1〇3 can be sampled and latched. Once the node CKDB is turned to a low voltage as shown in the first figure, the connection of the VI to the data input node 103 is weakened, and the flip-flop unit 13 is regarded as being in the off state. After the clock negative edge, the first PMOS transistor 131 is always on and the voltage of the node VI is kept at a high voltage VDD, and the data of the data input node 1〇3 cannot be sampled. The second figure shows the working timing diagram of the prior art hybrid latch flip-flop of the first figure, wherein V(D), V(CLOCK) and V(Q) respectively represent the data input node 1〇3 in the first figure. , clock input node 1〇1 and data input: 电压5 voltage waveform diagram. As shown in the first and second figures, the data is rotated 3 l3l3l 〇 before the low voltage 'clock positive edge' data input section data wheeling node 103 high voltage is sampled "= according to output (four) 105 from low The voltage is converted to a high voltage. The η 2 input angstrom point (10) is a low voltage, the data output node ι〇5 is a high voltage, the node: the low voltage of the point is sampled and turned out, and the data turns out "105 攸 South voltage is converted to low voltage Clearly low voltage, number 摅 ^ electric £ Tn + 2 刖, data input node data input ~ = 5 is low voltage, Τ η + 2, hold =; = = = sampling, data output section... Round out node 10S The rabbit handles the good data rounding node 103 for the high voltage 'data voltage is sampled, when the number neck i:Tn+3, the data input node 103 is high Tn+4~ sag, and the output node 105 changes from low voltage to high voltage, For the quotation, according to the input point 103 is the high voltage, when the data output node 105 data is output * 'Τη+4, the high voltage of the data input node 103 is sampled, 105 is maintained at a high voltage, before Τη+5, The data input node is based on the voltage 'data output node 105 is high voltage, when Τη+5, the number of electricity is turned low. The voltage is sampled 'data output node 105 from Gao Lei; ~ eat port latch flip-flop for the liquid crystal driver circuit, each row of mixed latch ^ pole must be used separately - hybrid latch flip-flop 1G (), but The second circuit of the control circuit has a large number of transistors, which causes the liquid crystal driving circuit to pass through the second circuit in order to adapt to the low-power driving control of the TFT-LCD. That is, ^, the hybrid latch flip-flop for grabbing requires less work but less power consumption - the circuit has the same function as the hybrid latch flip-flop 100. The latch is known here, providing one with A mix of smaller power consumption, 1313103, is necessary. SUMMARY OF THE INVENTION It is an object of the present invention to provide a hybrid latch flip-flop with low power consumption. The technical solution of the present invention is to provide a hybrid latching flip-flop including a clock input node, a positive pulse generating unit, a flip-flop unit, a buffer unit, a data input node, and a data output. A node, the flip-flop unit includes a sampling unit and a holding unit. The clock input node is coupled to the positive pulse generating unit, the positive pulse generating unit is coupled to the sampling unit, the sampling unit is coupled to the holding unit, the holding unit is coupled to the buffer unit, and the data input node is coupled to the sampling a data output node is connected to the buffer unit, the sampling unit includes three PMOS type transistors and four NMOS type transistors, and the three PMOS type transistors are a first PMOS type transistor and a second PMOS type type a crystal and a third PMOS type transistor, wherein the four NMOS type transistors are a first NMOS type transistor, a second NMOS type transistor, a third NMOS type transistor, and a fourth NMOS type transistor, the first PMOS type The source of the transistor, the source of the second PMOS type transistor, and the source of the third PMOS type transistor are all connected to the power supply node VDD, the gate of the first PMOS type transistor, and the gate of the second NMOS type transistor The gates of the pole and the fourth NMOS transistor are connected to the positive pulse generating unit, and the gate of the first NMOS transistor and the gate of the second PMOS transistor are connected to the data input node, the first PMOS Type transistor a pole of the second PMOS type transistor, a gate of the third PMOS type transistor, a gate of the third NMOS type transistor, and a drain of the first NMOS type transistor are connected to a node, the first NMOS The type of crystal crystal 1313103 is connected to the HNM() s type transistor, the third N is connected to the fourth N hall type crystal line pole, the second ground, the first body source and the source of the fourth NM0S type transistor Each of the NM0S^1 pulse production latch flip-flops includes a clock input node, a positive node, a ~-reactor unit, a buffer unit, a data input, a protection II _ 4 round-out node, The flip-flop unit includes a sampling unit and a unit, and the clock input node is connected to the positive pulse generating unit, and the generating unit generates a pre-existing pure unit, and the sampling unit is connected to the node connection=the unit is connected to the unit Buffer unit 'The data input element, ° single 70, § Hai data output node is connected to the buffer single to the sampling unit including three pM〇s type transistors and four NM〇s type electric ρμ〇:』ΡΜ〇_O crystal The first PMOS type is the first PMO_ transistor, the second 曰 first lean 曰曰 body, and the (10) (10) type transistor. The electric celestial body is the first NMOS type Lei b舻 wall x _ 〇 s type electric θ 曰 body and ί second Wei type transistor, the third day Nikko, the Japanese fourth 4^1^08 type transistor, The first PMOS type electric adjustment 4 original pole first PM 〇 S type transistor source and PMOS type transistor pole and skirt are connected to the power supply node VDD, the first - PMC> S type transistor gate -m^ NMQS3S11: The gate of the crystal is connected to the data input node, the gate of the transistor, the idle electrode of the second PM〇S transistor and the gate of the transistor are connected to the positive, the third m〇s type Hey? The drain of the PM0S type transistor, the first - Nnu. j日—The gate of the pole, the fourth ship (10) type transistor and the drain of the _S type transistor are connected to one node, and the source of the first awake (10) 1313103 type transistor is connected to the second NMOS The drain of the type transistor, the source of the third NMOS type transistor is connected to the drain of the fourth NMOS type transistor, the source of the second NMOS type transistor and the source of the fourth NMOS type transistor are grounded, The drain of the third PMOS type transistor and the drain of the third NMOS type transistor are both connected to the holding unit. A hybrid latch flip-flop includes a clock input node, a positive pulse generating unit, a flip-flop unit, a buffer unit, a data input node, and a data output node, the flip-flop unit including a sample Unit and a holding unit. The clock input node is connected to the positive pulse generating unit, the positive pulse generating unit is connected to the sampling unit, the sampling unit is connected to the holding unit, the holding unit is connected to the buffer unit, and the data input node is connected to the sampling unit a data output node is connected to the buffer unit, the sampling unit includes two PMOS type transistors and four NMOS type transistors, and the two PMOS type transistors are a first PMOS type transistor and a second PMOS type transistor, The four NMOS type transistors are a first NMOS type transistor, a second NMOS type transistor, a third NMOS type transistor, and a fourth NMOS type transistor, and the sources of the first PMOS type transistor and the second PMOS type transistor The pole is connected to the power supply node VDD, the gate of the first PMOS type transistor, the gate of the first NMOS type transistor, and the gate of the third NMOS type transistor are all connected to the positive pulse generating unit, and the second NMOS type The gate of the crystal is connected to the data input node, the drain of the first PMOS type transistor, the gate of the second PMOS type transistor, the gate of the fourth NMOS type transistor, and the drain of the first NMOS type transistor Connect to a node, a source of the first NMOS type transistor is connected to a drain of the second NMOS type transistor, a source of the third NMOS type transistor is connected to a drain of the fourth NMOS type transistor, and the second 11 1313103 NMOS type The source of the transistor and the source of the fourth NMOS type transistor are grounded, and the drain of the second PMOS type transistor and the drain of the third NMOS type transistor are both connected to the holding unit. A hybrid latching flip-flop includes a clock input node, a positive pulse generating unit, a flip-flop unit, a buffer unit, a data input node, and a data output node, the flip-flop unit including a sampling unit And a holding unit. The clock input node is connected to the positive pulse generating unit, the positive pulse generating unit is connected to the sampling unit, the sampling unit is connected to the holding unit, the holding unit is connected to the buffer unit, and the data input node is connected to the a sampling unit, the data output node is connected to the buffer unit, the sampling unit includes two PMOS type transistors and four NMOS type transistors, and the two PMOS type transistors are a first PMOS type transistor and a second PMOS type transistor, The four NMOS type transistors are a first NMOS type transistor, a second NMOS type transistor, a third NMOS type transistor, and a fourth NMOS type transistor, and the first PMOS type transistor and the second PMOS type transistor The source is connected to the power supply node VDD, the gate of the first PMOS type transistor and the gate of the second Μ Ο S type transistor are connected to the data input node, the gate of the first NMOS type transistor and the fourth The gate of the NMOS type transistor is connected to the positive pulse generating unit, the drain of the first PMOS type transistor, the gate of the second PMOS type transistor, the gate of the third NMOS type transistor, and the first NMOS type The extremes of the crystal Connected to a node, the source of the first NMOS type transistor is connected to the drain of the second NMOS type transistor, the source of the third NMOS type transistor is connected to the drain of the fourth NMOS type transistor, and the second NMOS The source of the type transistor and the source of the fourth NMOS type transistor are grounded, and the drain of the second PMOS type transistor and the third NMOS type transistor 12 1313103 are connected to the Paula-double-punch generation. Casing element; positive edge trigger type, negative edge trigger type or prior art compared to 'the hybrid latching flip-flop of the present invention has the advantage of the prior art single T transistor number = although the positive pulse generating unit has Mixing more transistors than the prior art, but using pulse generation 1 = off-pulse generating unit and flip-flop unit, so that the positive pulse becomes a common circuit in the liquid crystal driving circuit, so the positive pulse includes more Multi-transistors do not increase power consumption. Therefore, the port and sub-reactor of the present invention achieve the purpose of lower power consumption than the prior art. In this case, the double-edge trigger is used, and the clock frequency can be increased without changing the clock frequency. The data transmission capacity of the mixed-delta flip-flop device of the month is doubled. [Technical method] The block diagram is the structure of the hybrid latching positive and negative _ of the present invention. The hybrid latching flip-flop includes:··clock H dot, positive pulse generating soap 7G310 - a flip-flop unit 33 〇, a single 疋 33 〇 includes - sampling unit 34 〇 and - holding unit 349 thief, the clock input node 3 〇 1 is connected to the sinusoidal connection node 302 to the sampling U兀 340 is connected by lang point 3〇4"Haiyuan 349 is connected to the buffer list through node 3〇6; ^Early state, the remaining single flat 70350, the number 掳 input node 13 1313103 === to the sample unit, The button is disconnected from the node to the buffer. The (four) impulse generating unit can receive the clock from the clock input node and then convert the receiving clock into a positive pulse signal. The positive "call" is applied to the flip-flop unit 33 by the node 302. The forward and reverse crying unit 3 feet, the sampling list "40 is received by the data input node 3G3, the heart pulse generating unit receives the positive pulse signal, and the sampling document element ^ At the peak of the positive pulse, the data signal of the input data is 3, that is, at the peak time of each positive pulse, if the data signal is high voltage, the sample list = 340 outputs a high voltage, and if so, if the data When the signal is low voltage, the sampling unit 34G outputs - low voltage. The data after (4) is passed through the node to the holding unit 349. The holding unit 349 holds the sampling result input from the sampling unit 340 before the next data sampling, and The sampling result is output from the node 3〇6 to the buffer unit 350. The buffer unit 35〇 delays and amplifies the sampling result to provide a higher driving capability to the subsequent circuit. Obviously, the hybrid latching flip-flop 300 can realize the positive and negative The basic function of the device is to sample the data signal according to the clock signal and output the data signal. The positive pulse generating unit 31 of the hybrid latch flip-flop 300 of the present invention may include three embodiments. The flip-flop unit 330 can include four embodiments. Please refer to the fourth figure, which is a circuit diagram of the first embodiment of the positive pulse generating unit of the third-character hybrid latching flip-flop. The positive pulse shown in the fourth figure. The generating unit 410 includes a first inverter 411, a second inverter 412, a second inverter 413', a fourth inverter 414 and an inverse gate 415. The input of the first inverter 411 The terminal is connected to the clock input node 401, and the output end thereof is connected to the input end of the second inverter 412. The output end of the second inverter is connected to the input end of the third reverse 14.1313103 phaser 413 The output of the phase comparator is connected to one of the input terminals of the opposite gate, and the other wheel of the gate is connected to the clock input node 401, and the output of the gate 415 is connected to the input of the fourth inverter 414. The output of the fourth inverter 414 is connected to the node 4〇2. The first inverter and the second inverter 412 delay the clock signal from the clock input node, and the third inverter 413 is delayed and reversed. The clock signal from the clock input node 4〇1 is turned. That is, the clock signal of the node 401 is used by the first inverter 41. 1. The second inverter 412 and the second inverting phase are 413 delayed and inverted and input to one of the input terminals of the inverse gate 415. The clock signal of the node 401 is simultaneously input to the other input terminal of the inverse gate 415. That is, the positive or negative edge of the clock signal is directly input to one of the input terminals of the anti-gate 415, and the positive or negative edge is delayed and inverted to the negative or positive edge and then input to the other of the anti-gate 415 At the input end, each time after receiving the positive edge of the clock, before the negative edge of the delay, the back gate 415 outputs a negative voltage, and continuously forms a negative pulse. The negative pulse is inverted after passing through the fourth inverter 414. A positive pulse is generated and output to node 402. However, each time a negative edge of the clock is received, no pulse is generated before the positive edge of the delay. Referring to the fifth drawing, the figure is a circuit diagram of a second embodiment of the positive pulse generating unit of the hybrid latching flip-flop of the third figure. The positive pulse generating unit 5U) shown in the fifth figure includes a first inverter 511, a second inverter, a second inverter 513' - a fourth inverter 514 and an OR gate 516. The input of the first inverting 511 is connected to the clock input node 5〇1, and the output thereof is connected to the input of the second inverter 512. The output of the second inverter 512 is connected to the input end of the third inverter 513. The output of the third inverter 513 is connected to the input terminal of the OR gate 516 or the other end of the gate 516. The output connected to the clock input node 501' or the gate 516 is connected to the input 15 1313103 terminal of the fourth inverter 514, and the output of the fourth inverter 514 is connected to the node 5〇2. The first inverter 511 and the second inverter 512 delay the clock signal from the clock-in node, and the third inverter 513 delays and inverts the clock signal from the clock input node 5〇1. That is, the clock signal of the node 501 is delayed by the first inverter 511, the second reverse power benefit 512, and the second inverter 513, and is inverted and input to one of the inputs of the OR gate 516, and the clock signal of the node 501. At the same time, it is input to the other input of the OR gate 516. That is, the positive or negative edge of the clock signal is directly input or the input of the gate 516 is 'the positive or negative edge is delayed and inverted to the negative or positive edge and then input to the other input of the gate 516 Each time after receiving the negative edge of the clock, before the positive edge of the delay, or the gate 516 outputs a negative voltage, the continuous pulse forms a negative pulse. The negative pulse is inverted to a positive pulse after passing through the fourth inverter 514 and output to node 502. However, each time the positive edge of the clock is received, no pulse is generated before the negative edge of the delay. Please refer to the sixth figure, which is a circuit diagram of the third embodiment of the positive pulse generating unit of the hybrid latching flip-flop of the third figure. It is worth noting that after the implementation adopts the dual-edge triggered positive pulse generating unit, the capacity of the data transmission can be multiplied without changing the frequency of the clock. The positive pulse generating unit 610 shown in FIG. 6 includes a first inverter 611, a second inverter 612, a third inverter 613, a fourth inverter 614, and a mutually exclusive or gate 617. . The input of the first inverter 611 is coupled to the clock input node, and the output thereof is coupled to the input of the first reverse burglary 612. The output of the second inverter 612 is connected to the input of the third inverter 613, and the output of the third inverter 613 is connected to one of the mutex or gate 617 inputs, and the other of the mutex or gate 617 The input is coupled to clock input node 601, the output of mutex or gate 617 is coupled to the input of fourth inverter 614, and the output of fourth inverter 614 is coupled to node 16 1313103 6〇2. The first inverter 611 and the second inverter 612 delay the clock signal of the node π spider from the clock-in node. The third inverter 613 delays and inverts from the clock ^
點601之時脈訊號。即，節點601之時脈訊號被第二二 611、第二反相器612及第三反相器613延遲且反轉後輸二= 互斥或閘617之一輸入端，節點601之時脈訊號同時輸入至 互斥或閘617之另一輸入端。時脈訊號之正緣或負緣^直接 輪入互斥或閘617之一輸入端，該正緣或負緣被延遲且反轉 為負緣或正緣後輸入至互斥或閘617之另一輪入端，每次接 收到時脈負緣後，延遲之正緣前，及每次接收到時脈正緣 後，延遲之負緣前，互斥或閘617均輸出一負電壓，連續起 來則形成負脈衝。該負脈衝經過第四反相器614播祜；5絲# 正脈衝，且輸出至節點602。 請參照第七圖’係第三圖混合鎖存正反器之正反器單 元之第一實施方式及緩衝單元之電路圖示。如第七圖所 不，該正反器早元730包括· 採樣單元740，一保持單元 749。該採樣單元740包括：三個PMOS型電晶體（即，第一 PMOS型電晶體731、第二PMOS型電晶體732及第三PM〇s 型電晶體733)及四個NMOS型電晶體（即，第一nm〇S型電 晶體741、第二NMOS型電晶體742、第三NM0S型電晶體743 及弟四NM0S型電晶體744)。該保持單元749包括：第五反 相器747及第六反相器748。 該第一PM0S型電晶體731之源極、第二PMOS型電晶 體732之源極及第三PM0S型電晶體733之源極均連接至電 源節點VDD。第一PMOS型電晶體731之閘極、第二NMOS 型電晶體742之閘極及第四NM0S型電晶體744之閘極均連 17 1313103 接至脈衝訊號輸入節點702。第一 NMOS型電晶體741之間 極及第二PM0S型電晶體732之閘極均連接至數據輸入節點 703。第一PMOS型電晶體731之汲極、第二PMOS型電晶體 732之汲極、第三PM0S型電晶體733之閘極、第三NM0S型 電晶體743之閘極及第一 NM0S型電晶體741之汲極均連接 至節點V7。第一 NM0S型電晶體741之源極連接至第二 NM0S型電晶體742之沒極。第三NM0S型電晶體743之源極 連接至第四NM0S型電晶體744之汲極。第二NM0S型電晶 體742之源極及第四NMOS型電晶體744之源極均接地（零伏 特）。第二PMOS型電晶體733之没極及第三NMOS型電晶體 743之汲極均通過節點7〇4連接至保持單元749。本技術領域 之普通技術人員可看出第一 PMOS型電晶體731、第二Point 601 clock signal. That is, the clock signal of the node 601 is delayed by the second two 611, the second inverter 612, and the third inverter 613, and the input is inverted, and the input of the node 601 is the input of the mutex or the gate 617. The signal is simultaneously input to the other input of the mutex or gate 617. The positive or negative edge of the clock signal directly enters one of the inputs of the mutex or gate 617. The positive or negative edge is delayed and inverted to the negative or positive edge and then input to the mutex or gate 617. After one round of ingress, each time after receiving the negative edge of the clock, before the positive edge of the delay, and after receiving the positive edge of the clock, before the negative edge of the delay, the mutual exclusion or gate 617 outputs a negative voltage, which is continuous. Then a negative pulse is formed. The negative pulse is propagated through the fourth inverter 614; the 5 filament # positive pulse is output to the node 602. Referring to the seventh embodiment, the first embodiment of the flip-flop unit of the hybrid latch flip-flop and the circuit diagram of the buffer unit are shown. As shown in the seventh figure, the flip-flop early element 730 includes a sampling unit 740 and a holding unit 749. The sampling unit 740 includes three PMOS type transistors (ie, a first PMOS type transistor 731, a second PMOS type transistor 732, and a third PM?s type transistor 733) and four NMOS type transistors (ie, The first nm 〇S type transistor 741, the second NMOS type transistor 742, the third NMOS transistor 743, and the fourth NMOS transistor 744). The holding unit 749 includes a fifth inverter 747 and a sixth inverter 748. The source of the first PMOS transistor 731, the source of the second PMOS type transistor 732, and the source of the third PMOS transistor 733 are all connected to the power supply node VDD. The gate of the first PMOS transistor 731, the gate of the second NMOS transistor 742, and the gate of the fourth NMOS transistor 744 are connected to the pulse signal input node 702. The gates of the first NMOS type transistor 741 and the gate of the second PMOS type transistor 732 are both connected to the data input node 703. a drain of the first PMOS type transistor 731, a drain of the second PMOS type transistor 732, a gate of the third PMOS transistor 733, a gate of the third NMOS transistor 743, and a first NM0S transistor The 741's 汲 is connected to node V7. The source of the first NMOS transistor 741 is connected to the terminal of the second NMOS transistor 742. The source of the third NM0S type transistor 743 is connected to the drain of the fourth NM0S type transistor 744. The source of the second NM0S type electric crystal 742 and the source of the fourth NMOS type transistor 744 are both grounded (zero volts). The drain of the second PMOS type transistor 733 and the drain of the third NMOS type transistor 743 are both connected to the holding unit 749 through the node 7〇4. One of ordinary skill in the art can see the first PMOS type transistor 731, the second
PMOS型電晶體732、第一 NMOS型電晶體741及第二NMOS 型電晶體742構成一反及閘。脈衝訊號輸入節點7〇2及數據 輸入節點703為該反及閘之二輸入端，節點V7為該反及閘 之輸出端。假設脈衝訊號輸入節點702為低電壓，數據輸入 節點703無論為低電壓或高電壓，節點V7均為高電壓，第 二PMOS型電晶體乃3關閉’且第三NMOS型電晶體743 P# 啟。因假設脈衝訊號輸入節點7〇2為低電壓，第四NM〇Ss 電晶體744關閉，結果保持單元749之數據不變。另，假設 脈衝sfL號輸入郎點702為面電壓，數據輸入節點703為低電 壓時，V7節點為高電壓。脈衝訊號輸入節點7〇2為高電壓， 而數據輸入節點703為高電壓時V7節點為低電壓。如果V7 節點為高電壓，第三PMOS型電晶體733關閉，第三NM〇s 型電晶體743開啟，既然已假設脈衝訊號輸入節點7〇2為高 18 1313103 電壓，第四NMOS型電晶體744開啟，保持單元749通過節 點704、第三NMOS型電晶體743及第四NMOS型電晶體744 對地放電，這就等同於輪出一低電壓至保持單元749。另一 方面，如果V7節點為低電壓，第三pM〇s型電晶體733開 啟，第三NMOS型電晶體743關閉，這樣就輸出一高電壓至 保持單元749。結果由時脈正緣觸發，數據輸入節點之數據 被採樣。被採樣之數據從採樣單元740經節點704輸入至保 持單元749。下一數據被採樣前，保持單元749反轉並保持 該採樣數據’然後該採樣數據經節點706輸入至緩衝單元 φ 750 ° 該緩衝單元750包括一第七反相器751，該反相器751 反轉經正反器单元730及節點706輸入之反轉採樣數據。於 是’該採樣數據就恢復為最原始採樣時之數據，然後將原 始之採樣數據輸至數據輸出節點7〇5。即，該缓衝單元750 係為輸出訊號提供一緩存’且為後續電路提供更高之驅動 能力。 請參照第八圖，該圖係第三圖混合鎖存正反器之正反 φ 器單元之第二實施方式及緩衝單元之電路圖示。如第八圖 所示’該正反器單元830包括：一採樣單元840，一保持單 元849。該採樣單元840包括：三個PMOS型電晶體（即，第 一 PMOS型電晶體831、第二PMOS型電晶體832及第三 PM0S型電晶體833)及四個NMOS型電晶體（即，第一NM〇s 型電晶體841、第二NMOS型電晶體842、第三NMOS型電晶 體843及第四NMOS型電晶體844)。該保持單元849包括：第 五反相器847及第六反相器848。 19 1313103 該第一PMOS型電晶體831之源極、第二PMOS型電晶 體832之源極及PMOS型電晶體833之源極均連接至電源節 點VDD。第一PMOS型電晶體之閘極及第二1^厘〇3型電晶體 842之閘極均連接至數據輸入節點8〇3。第一nm〇s型電晶 體841之閘極、第二PM0S型電晶體832之閘極及第三NM0S 型電晶體843之閘極均連接至節點8〇2。第一PM〇Ss電晶體 831之汲極、第二PM0S型電晶體832之汲極、第三PM0S型 電晶體833之閘極、第四NM0S型電晶體844之閘極及第一 NM0S型電晶體841之沒極均連接至節點vs。第一nm〇S型 電晶體841之源極連接至第二NM0S型電晶體842之汲極。 第二NM0S型電晶體843之源極連接至第四NM0S型電晶體 844之汲極。第二NMOS型電晶體之源極及第四NMOS型電 晶體844之源極均接地（零伏特）。第三PM〇s型電晶體833之 汲極及第三NMOS型電晶體843之汲極均通過節點8〇4連接 至保持單元849。本技術領域之普通技術人員可看出：第一 PMOS型電晶體831、第二PM0S型電晶體832、第一 NMOS 型電晶體841及第二NMOS型電晶體842構成一反及閘。節 點802及數據輸入節點803為該反及閘之二輸入端，節點v8 為該反及閘之輸出端。假設節點802為低電壓，數據輸入節 點803無論為低電壓或高電壓，節點V8均為高電壓，第三 PMOS型電晶體833關閉，且第四NMOS型電晶體844開啟。 因假設節點802為低電壓，第三NMOS型電晶體843關閉， 結果保持單元849之數據保持不變。另，假設節點8〇2為高 電壓，數據輸入節點803為低電壓時，V8節點為高電壓， 郎點802為尚電壓，而數據輸入節點803為高電壓時vg節點 20 1313103 為低電壓。如果V8節點為高電壓，第三PMOS型電晶體833 關閉，第四NMOS型電晶體844開啟，既然已假設節點802 為高電壓’第三NMOS型電晶體843開啟，保持單元849通 過節點804、第三NMOS型電晶體843及第四NMOS型電晶體 844對地放電為零伏特’這就等同於輸出一低電壓至保持單 元849。另一方面’如果V8節點為低電壓，第三PMOS型電 晶體833開啟’第四NMOS型電晶體844關閉，這樣就輸出 一高電壓至保持單元849。即，由時脈正緣觸發，數據輸入 節點803之數據被採樣，被採樣之數據由採樣單元84〇經節 籲 點804輸入至保持單元849。下一數據被採樣前，保持單元 849反轉並保持該採樣數據，然後該採樣數據經節點8〇6輸 入至緩衝單元850。 該緩衝單元850包括一第七反相器851，該反相器851 反轉從正反器單元830經節點806輸入之反轉採樣數據。於 是’該採樣數據就恢復為最原始採樣時之數據，然後將原 始之採樣數據輸入至數據輸出節點805。即，該緩衝單元85〇 係為輸出訊號提供一緩存，且為後續電路提供更高之驅動鲁 能力。 以上描述中採樣單元740及840包括七個型電晶體 為明顯。既然本發明脈衝觸發型正反器單元 脈 區動採樣過程，節點搬之電壓多數時間為低，則獨 點之電壓多數為高。因此對於大多數之使用，僅採用第一 電晶體831就足夠了，且優於同時採用第一 pM〇s 型，，體831及第二PMOS型電晶體832,還可減少本發明正 反盗單元之所需電晶體數量。 21 1313103 請參考第九圖，該圖係第三圖混合鎖存正反器之正反 器單元之第三實施方式及緩衝單元之電路圖示。第九圖中 所示，該正反器單元930包括：一採樣單元940，一保持單 元949。該採樣單元94〇包括：二p]V[〇s型電晶體（即，第一 PM0S型電晶體931及第二PMOS型電晶體932)及四個The PMOS type transistor 732, the first NMOS type transistor 741, and the second NMOS type transistor 742 constitute a reverse gate. The pulse signal input node 7〇2 and the data input node 703 are the input terminals of the reverse gate, and the node V7 is the output terminal of the inverse gate. Assuming that the pulse signal input node 702 is low voltage, the data input node 703 is low voltage or high voltage, the node V7 is high voltage, the second PMOS type transistor is 3 off' and the third NMOS type transistor 743 P# is activated. . Since the pulse signal input node 7〇2 is assumed to be a low voltage, the fourth NM〇Ss transistor 744 is turned off, and as a result, the data of the holding unit 749 is unchanged. In addition, it is assumed that the pulse sfL number is 158 as the surface voltage, and when the data input node 703 is at the low voltage, the V7 node is at the high voltage. The pulse signal input node 7〇2 is a high voltage, and the V7 node is a low voltage when the data input node 703 is at a high voltage. If the V7 node is high voltage, the third PMOS type transistor 733 is turned off, and the third NM 〇s type transistor 743 is turned on, since it has been assumed that the pulse signal input node 7〇2 is high 18 1313103 voltage, the fourth NMOS type transistor 744 Turning on, the holding unit 749 discharges to ground through the node 704, the third NMOS type transistor 743, and the fourth NMOS type transistor 744, which is equivalent to rotating a low voltage to the holding unit 749. On the other hand, if the V7 node is at a low voltage, the third pM s-type transistor 733 is turned on, and the third NMOS-type transistor 743 is turned off, thus outputting a high voltage to the holding unit 749. The result is triggered by the positive edge of the clock and the data at the data input node is sampled. The sampled data is input from the sampling unit 740 to the holding unit 749 via the node 704. Before the next data is sampled, the holding unit 749 inverts and holds the sampled data 'The sampled data is then input to the buffer unit φ 750 ° via the node 706. The buffer unit 750 includes a seventh inverter 751, the inverter 751 The inverted sample data input by the flip-flop unit 730 and the node 706 is inverted. Then the sampled data is restored to the data at the time of the original sampling, and then the original sampled data is output to the data output node 7〇5. That is, the buffer unit 750 provides a buffer for the output signal and provides a higher driving capability for subsequent circuits. Please refer to the eighth figure, which is a circuit diagram of the second embodiment of the positive and negative φ unit of the hybrid latch flip-flop and the circuit diagram of the buffer unit. As shown in the eighth figure, the flip-flop unit 830 includes a sampling unit 840 and a holding unit 849. The sampling unit 840 includes three PMOS type transistors (ie, a first PMOS type transistor 831, a second PMOS type transistor 832, and a third PMOS type transistor 833) and four NMOS type transistors (ie, An NM〇s type transistor 841, a second NMOS type transistor 842, a third NMOS type transistor 843, and a fourth NMOS type transistor 844). The holding unit 849 includes a fifth inverter 847 and a sixth inverter 848. 19 1313103 The source of the first PMOS type transistor 831, the source of the second PMOS type transistor 832, and the source of the PMOS type transistor 833 are all connected to the power supply node VDD. The gate of the first PMOS type transistor and the gate of the second 1 〇 〇 type 3 transistor 842 are both connected to the data input node 8〇3. The gate of the first nm 〇s type electric crystal 841, the gate of the second PMOS transistor 832, and the gate of the third NMOS transistor 843 are all connected to the node 8〇2. The drain of the first PM〇Ss transistor 831, the drain of the second PMOS transistor 832, the gate of the third PMOS transistor 833, the gate of the fourth NMOS transistor 844, and the first NM0S type The poles of the crystal 841 are all connected to the node vs. The source of the first nm 〇S type transistor 841 is connected to the drain of the second NMOS transistor 842. The source of the second NMOS transistor 843 is connected to the drain of the fourth NMOS transistor 844. The source of the second NMOS type transistor and the source of the fourth NMOS type transistor 844 are both grounded (zero volts). The drain of the third PM?s type transistor 833 and the drain of the third NMOS type transistor 843 are both connected to the holding unit 849 through the node 8?. A person skilled in the art can see that the first PMOS type transistor 831, the second PMOS type transistor 832, the first NMOS type transistor 841 and the second NMOS type transistor 842 constitute a reverse gate. Node 802 and data input node 803 are the input terminals of the inverse and gate, and node v8 is the output of the inverse gate. Assuming node 802 is low voltage, data input node 803 is low voltage or high voltage, node V8 is high voltage, third PMOS type transistor 833 is off, and fourth NMOS type transistor 844 is on. Since the node 802 is assumed to be at a low voltage, the third NMOS type transistor 843 is turned off, and the data of the result holding unit 849 remains unchanged. In addition, assuming that node 8〇2 is high voltage, data input node 803 is low voltage, V8 node is high voltage, 朗点802 is still voltage, and vg node 20 1313103 is low voltage when data input node 803 is high voltage. If the V8 node is high voltage, the third PMOS type transistor 833 is turned off, and the fourth NMOS type transistor 844 is turned on. Since the node 802 is assumed to be a high voltage 'the third NMOS type transistor 843 is turned on, the holding unit 849 passes through the node 804, The third NMOS type transistor 843 and the fourth NMOS type transistor 844 discharge zero volts to ground 'this is equivalent to outputting a low voltage to the holding unit 849. On the other hand, if the V8 node is at a low voltage, the third PMOS type transistor 833 is turned "the fourth NMOS type transistor 844 is turned off, so that a high voltage is outputted to the holding unit 849. That is, triggered by the positive edge of the clock, the data of the data input node 803 is sampled, and the sampled data is input to the holding unit 849 by the sampling unit 84 via the node 804. Before the next data is sampled, the holding unit 849 inverts and holds the sampled data, and then the sampled data is input to the buffer unit 850 via the node 8〇6. The buffer unit 850 includes a seventh inverter 851 that inverts inverted sample data input from the flip-flop unit 830 via the node 806. Then, the sampled data is restored to the data at the time of the original sampling, and then the original sampled data is input to the data output node 805. That is, the buffer unit 85 provides a buffer for the output signal and provides a higher drive capability for subsequent circuits. The sampling units 740 and 840 in the above description include seven types of transistors as apparent. Since the pulse-triggered flip-flop unit of the present invention is subjected to the pulse sampling process, the voltage of the node is mostly low, and the voltage of the single point is mostly high. Therefore, for most uses, it is sufficient to use only the first transistor 831, and it is better than using the first pM〇s type, the body 831 and the second PMOS type transistor 832, and can also reduce the positive and negative theft of the present invention. The number of transistors required for the unit. 21 1313103 Please refer to the ninth figure, which is a circuit diagram of a third embodiment of the flip-flop unit of the hybrid latch flip-flop and a buffer unit of the third figure. As shown in the ninth figure, the flip-flop unit 930 includes a sampling unit 940 and a holding unit 949. The sampling unit 94A includes: two p]V [〇s type transistors (ie, the first PM0S type transistor 931 and the second PMOS type transistor 932) and four
NMOS型電晶體（即，第一nm〇S型電晶體941、第二NMOS 型電晶體942、第三NMOS型電晶體943及第四NMOS型電晶 體944)。該保持單元949包括：第五反相器947及第六反相 器 948。 該第一 PMOS型電晶體931及第二PMOS型電晶體932 之源極連接至電源節點VDD。第一 PMOS型電晶體931之閘 極、第一NMOS型電晶體941之閘極及第三NMOS型電晶體 943之閘極均連接至節點9〇2。第二nm〇s型電晶體942之閘 極連接至數據輸入節點903。第一PMOS型電晶體931之汲 極、第二PMOS型電晶體932之閘極、第四NMOS型電晶體 944之閘極及第一nm〇S型電晶體941之汲極均連接至節點 V9。第一NMOS型電晶體941之源極連接至第：NM〇s型電 晶體942之汲極。第三NM0S型電晶體943之源極連接至第 四NMOS型電晶體944之沒極。第二NMOS型電晶體之源極 及第四NMOS型電晶體944之源極均接地（零伏特）。第二 PMOS型電晶體932之沒極及第三NMOS型電晶體943之汲 極均通過節點904連接至保持單元949。當節點902為低電壓 時，苐一 PMOS型電晶體931開啟，第一 NMOS型電晶體941 關閉，第三NMOS型電晶體943關閉，V9被持續充電為高電 壓。因V9為高電壓，第二PM〇S型電晶體932關閉，第四 22 1313103 NOMS型電晶體944開啟。結果保持單元949之數據保持不 變。當節點902變為高電M時，第_ pM〇s型電晶體％工關 閉，第一NMOS型電晶體941開啟，第三顧仍型電晶體州 開啟，假設此時數據輸入節點為低電壓，第：NM〇s型電 晶體關閉，考慮到節點V9還保持高電壓，第四N〇MS電晶_ 體保持開啟一#又時間，結果保持單元949之數據通過節點_ 904、第>NMOS型電晶體943及第四n〇MS型電晶體944對. 地放電為零伏。此等效為輸出一低電壓至電壓保持單元 949。假設數據輸入節點903為高電壓，第二NOMS型電晶 φ 體942開啟，節點V9通過第一 NOMS型電晶體941及第二 NOMS塑電晶體942對地放電為零伏，因此第四NOMS型電 晶體944關閉’第二PMOS型電晶體932開啟，節點904通過 - 第二型電晶體932充電為高電壓並輸出至保持單元 949。即’由時脈正緣觸發’數據輸入節點903之數據被採 樣，被採樣之數據由採樣單元940經節點904輸入至保持單 元949。下一數據被採樣前，保持單元949反轉並保持該採 樣數據，然後該採樣數據經節點906輸入至緩衝單元950。 鲁 該缓衝單元950包括一第七反相器951，該反相器951 反轉經正反器單元930及節點906輸入之反轉採樣數據。於 是，該採樣數據就恢復為最原始採樣時之數據，然後將原 始之採樣數據輪至數據輸出節點905。即，該緩衝單元950 係為輸出訊號提供一緩存，且為後續電路提供更高之驅動 能力。 請參考第十圖，該圖係第三圖混合鎖存正反器之正反 器單元之第四實施方式及緩衝單元之電路圖示。如第十圖 23 1313103 中所示，該正反器單元1030包括：一採樣單元1040，一保 持單元1049。該採樣單元1040包括：二PMOS型電晶體（即， 第一 PMOS型電晶體1031及第二PMOS型電晶體1〇32)及四 個NMOS型電晶體（即，第一 NMOS型電晶體1041、第二 NMOS型電晶體1042、第三NMOS型電晶體1043及第四 NMOS型電晶體1044)。該保持單元1049包括：第五反相器 1047及第六反相器1048。An NMOS type transistor (i.e., a first nm 〇S type transistor 941, a second NMOS type transistor 942, a third NMOS type transistor 943, and a fourth NMOS type electric crystal 944). The holding unit 949 includes a fifth inverter 947 and a sixth inverter 948. The sources of the first PMOS type transistor 931 and the second PMOS type transistor 932 are connected to the power supply node VDD. The gate of the first PMOS type transistor 931, the gate of the first NMOS type transistor 941, and the gate of the third NMOS type transistor 943 are all connected to the node 9〇2. The gate of the second nm 〇s type transistor 942 is coupled to the data input node 903. The drain of the first PMOS type transistor 931, the gate of the second PMOS type transistor 932, the gate of the fourth NMOS type transistor 944, and the drain of the first nm 〇S type transistor 941 are all connected to the node V9. . The source of the first NMOS type transistor 941 is connected to the drain of the :NM 〇s type transistor 942. The source of the third NM0S type transistor 943 is connected to the terminal of the fourth NMOS type transistor 944. The source of the second NMOS type transistor and the source of the fourth NMOS type transistor 944 are both grounded (zero volts). The gate of the second PMOS type transistor 932 and the third NMOS type transistor 943 are connected to the holding unit 949 through the node 904. When the node 902 is at a low voltage, the first PMOS type transistor 931 is turned on, the first NMOS type transistor 941 is turned off, the third NMOS type transistor 943 is turned off, and V9 is continuously charged to a high voltage. Since V9 is a high voltage, the second PM〇S type transistor 932 is turned off, and the fourth 22 1313103 NOMS type transistor 944 is turned on. The data of the result holding unit 949 remains unchanged. When the node 902 becomes high power M, the first _ pM 〇 s type transistor is turned off, the first NMOS type transistor 941 is turned on, and the third NAND type transistor is turned on, assuming that the data input node is low voltage at this time. , the NM〇s type transistor is turned off, considering that the node V9 still maintains a high voltage, the fourth N〇MS transistor remains open for a time, and the data of the holding unit 949 is passed through the node _904, the > The NMOS type transistor 943 and the fourth n〇MS type transistor 944 are discharged to zero volts. This equivalent is to output a low voltage to voltage holding unit 949. Assuming that the data input node 903 is at a high voltage, the second NOMS type electromorphic φ body 942 is turned on, and the node V9 is discharged to the ground by the first NOMS type transistor 941 and the second NOMS plastic transistor 942 to zero volts, so the fourth NOMS type The transistor 944 is turned off 'the second PMOS type transistor 932 is turned on, and the node 904 is charged to a high voltage by the second type transistor 932 and output to the holding unit 949. That is, the data of the data input node 903 is triggered by the clock positive edge, and the sampled data is input by the sampling unit 940 to the holding unit 949 via the node 904. The holding unit 949 inverts and holds the sample data before the next data is sampled, and then the sample data is input to the buffer unit 950 via the node 906. The buffer unit 950 includes a seventh inverter 951 that inverts the inverted sample data input via the flip-flop unit 930 and the node 906. Thus, the sampled data is restored to the data at the time of the original sampling, and then the original sampled data is transferred to the data output node 905. That is, the buffer unit 950 provides a buffer for the output signal and provides a higher driving capability for subsequent circuits. Please refer to the tenth figure, which is a circuit diagram of a fourth embodiment of the flip-flop unit of the hybrid latch flip-flop and a buffer unit of the third figure. As shown in the tenth figure 23 1313103, the flip-flop unit 1030 includes a sampling unit 1040 and a holding unit 1049. The sampling unit 1040 includes: two PMOS type transistors (ie, a first PMOS type transistor 1031 and a second PMOS type transistor 1〇32) and four NMOS type transistors (ie, a first NMOS type transistor 1041) The second NMOS type transistor 1042, the third NMOS type transistor 1043, and the fourth NMOS type transistor 1044). The holding unit 1049 includes a fifth inverter 1047 and a sixth inverter 1048.
該第一 PMOS型電晶體1031及第二PMOS型電晶體 1032之源極連接至電源節點VDD。第一PMOS型電晶體 1031之閘極及第二NMOS型電晶體1042之閘極均連接至數 據輸入節點1003。第一NMOS型電晶體1041之閘極及第四 NMOS型電晶體1044之閘極連接至節點1〇〇2。第一；PMOS型 電晶體1031之汲極、第二PMOS型電晶體1032之閘極、第三 NMOS型電晶體1043之閘極及第一 NMOS型電晶體1041之 汲極均連接至節點V10。第一 NMOS型電晶體1041之源極連 接至第二NMOS型電晶體1〇42之汲極。第三NMOS型電晶體 1043之源極連接至第四NMOS型電晶體1044之汲極。第二 NMOS型電晶體之源極及第四NMOS型電晶體1044之源極 均接地（零伏特）。第二PMOS型電晶體1032之汲極及第三 NMOS型電晶體1〇43之汲極均通過節點1〇〇4連接至保持單 元1049。假設節點1〇〇2為低電壓，第一NMOS型電晶體1041 關閉’第四NMOS型電晶體1044關閉，如果數據輸入節點 1003為低電壓，第一PMOS型電晶體1031開啟，第二NMOS 型電晶體1042關閉，節點V10被持續充電至高電壓。既然 V10為高電壓，第二PMOS型電晶體1032關閉，第三NOMS 24 1313103The sources of the first PMOS type transistor 1031 and the second PMOS type transistor 1032 are connected to the power supply node VDD. The gate of the first PMOS type transistor 1031 and the gate of the second NMOS type transistor 1042 are both connected to the data input node 1003. The gate of the first NMOS transistor 1041 and the gate of the fourth NMOS transistor 1044 are connected to the node 1〇〇2. First, the drain of the PMOS type transistor 1031, the gate of the second PMOS type transistor 1032, the gate of the third NMOS type transistor 1043, and the drain of the first NMOS type transistor 1041 are all connected to the node V10. The source of the first NMOS type transistor 1041 is connected to the drain of the second NMOS type transistor 1?42. The source of the third NMOS type transistor 1043 is connected to the drain of the fourth NMOS type transistor 1044. The source of the second NMOS type transistor and the source of the fourth NMOS type transistor 1044 are both grounded (zero volts). The drain of the second PMOS type transistor 1032 and the drain of the third NMOS type transistor 1〇43 are both connected to the holding unit 1049 through the node 1〇〇4. Assuming that the node 1〇〇2 is low voltage, the first NMOS type transistor 1041 is turned off, and the fourth NMOS type transistor 1044 is turned off. If the data input node 1003 is low voltage, the first PMOS type transistor 1031 is turned on, and the second NMOS type is turned on. The transistor 1042 is turned off and the node V10 is continuously charged to a high voltage. Since V10 is high voltage, the second PMOS type transistor 1032 is turned off, and the third NOMS 24 1313103
型電晶體觸開啟。結果簡單元腿之_不變。如果 數據輸入節點1003為高電壓，第—pM〇s型電晶體關閉，第 二NMOS型電晶體魏開啟。由於第—Ν_型電晶體腿 關閉’節點νιο仍保持高電壓。vl〇為高電壓則第二 型電晶體1G32關閉’結果保持單元刪之數據不變。即， 不論數據輸入節點之電壓為高或低電壓，保持單元1〇49之 數據不變。假設當節點1〇〇2由低電壓變為高電壓時，第一 NMOS型電晶體1041開啟，第四NM〇s型電晶體川料開啟。 如果數據輸入節點1003為低電壓，第一PM〇s型電晶體1〇31 開啟，第二NMOS型電晶體1042關閉節，點V10被持續充電 至尚電壓。既然V10為高電壓，第二PMOS型電晶體1032關 閉’第二NOMS型電晶體1〇43開啟。因此時第四NMOS型電 晶體1044也為開啟’結果保持單元1〇49之數據通過節點 1004、第三NMOS型電晶體1〇43及第四NOMS型電晶體1044The type of transistor touches open. The result is that the unit's leg is unchanged. If the data input node 1003 is at a high voltage, the -pM〇s type transistor is turned off, and the second NMOS type transistor is turned on. Since the first-Ν-type transistor leg is turned off, the node νιο still maintains a high voltage. When vl〇 is high voltage, the second type transistor 1G32 is turned off. That is, the data of the holding unit 1〇49 does not change regardless of whether the voltage of the data input node is high or low. It is assumed that when the node 1〇〇2 changes from a low voltage to a high voltage, the first NMOS type transistor 1041 is turned on, and the fourth NM〇s type transistor is turned on. If the data input node 1003 is at a low voltage, the first PM s-type transistor 1 〇 31 is turned on, the second NMOS type transistor 1042 is turned off, and the point V10 is continuously charged to a still voltage. Since V10 is a high voltage, the second PMOS type transistor 1032 is turned off, and the second NOMS type transistor 1〇43 is turned on. Therefore, the fourth NMOS type transistor 1044 is also turned on. The data of the result holding unit 1〇49 passes through the node 1004, the third NMOS type transistor 1〇43, and the fourth NOMS type transistor 1044.
對地放電為零伏。這等效為輸出一低電壓至電壓保持單元 1049。如果數據輸入節點1〇03為高電壓，第一PM〇s型電晶 體關閉，第二NMOS型電晶體1〇42開啟。由於第一NMOS 型電晶體1041為開啟，節點V10通過第一 NOMS型電晶體 1041及第二NOMS型電晶體1042對地放電為零伏，因此第 四NOMS型電晶體1044關閉，第二PMOS型電晶體1032開 啟，輸出高電壓至保持單元1049。即，由時脈正緣觸發， 數據輸入節點1003之數據被採樣，被採樣之數據由採樣單 元1040經節點1〇〇4輸入至保持單元1049。下一數據被採樣 前，保持單元1049反轉並保持該採樣數據，然後該採樣數 據經節點1006輸入至緩衝單元1050。 25 1313103 該緩衝單元1〇5〇包括一第七反相器1〇51 ，該反相器 1051反轉從正反器單元1030經節點1〇〇6輸入之反轉採樣數 據。於是，該採樣數據就恢復為最原始採樣時之數據，然 後將原始之採樣數據施加於數據輪出節點1〇〇5。即，該緩 衝單元1050係為輸出訊號提供一緩存，且為後續電路提供 更南之驅動能力。 以上描述本發明實施方式中採樣單元74〇及84〇僅包括 七個MOS型電晶體’ 94〇及1〇4〇僅包括六個M〇s型電晶體為 明顯，較第一圖所示之採樣單元14〇包括十個14〇5型電晶 體/本發明之採樣單元具有較小耗電量，雖然本發明之正 脈衝產生單元310所需電晶體數量多於第—圖所示之先前 技術此σ鎖存正反器中反轉單元11〇所需之電晶體數量然 本發明Ϊ用了正脈衝正反11單元後可时離脈衝產生單元 與正反器單70，使該正脈衝產生單元於液晶驅動電路中成 為公共電路’參考第十二圖可知該正脈衝產生單元於液晶 驅動電路巾係為公共電路，其所增加之電晶體數量不會導 致總體驅動電路魏增加，因此本發明之混合鎖存正反器 實現了比先前技術更低功耗之目的。且採用雙緣觸發狂 ，衝產生I"0後’不改變時脈頻率即可倍增數據傳輸之容 篁。 之工考第十—圖，係本發明之混合鎖存正反器300 :序圖。如第十一圖所示"V (D )’，係數據輪入節點迎 ,文康訊號波型圖；，，V(CL〇CK)"係時脈輸 脈訊號波型圖；”Vrr>T . 之日子 口 V(CLK)”係節點3〇2之脈衝訊號浊〗 ”V(Q)，’係數據輸出節…心认…皮型圖， 點305之輸出δίΐ號波型圖。該第十_一 g 26 ΓϋΗ7Χ~3ΐΓ 4 ·> J / /,-- 1313103 中所不之"V(CLK)"波型圖為第四圖所示脈衝產生單元410 所產生。於時脈Τη之前，v(CLOCK)及V(CLK)均為低電壓， 假《又V(q)為低電壓，Tn時，lk)出現一正緣，因此產生 __^楚 、一一正脈衝V(CLK)’數據訊號v(D)被採樣。因Tn時V(D) 為间電壓’ V(Q)也轉變為高電>1。Tn+1時，V(CLK)出現另 二二f，因此產生一第二正脈衝V(CLK)，數據訊號V(D) H羡。因Tn+1時V(D)為低電壓，V(Q)也轉變為低電壓。 5 γ因Tn+2時V(D)為低電壓，v⑼仍保持為低電壓，因 V: I:厂為高電壓，V(Q)也轉變為高電壓，因Tn+4時 ()〜電壓’ V⑼仍保持為高電壓，因μ 電壓，V(Q)也轉變為低雷 （）為低 始六x 付笑勹低窀壓。雖然以上本發明揭示之、、9人 鎖存正反器300係設計用於 „ 之此合 用非僅限於此。 仏夜曰曰顯不益之驅動電路，但其應 利申述’本發明符合發明專利要件，爰依法提出專 2二=以上_一本發明之較佳實施例，G ㈣之人士’在援依本案發 = 飾或變化m含心 <荨政修 【圖式簡單說明】之申明專利軌圍内。 p圖係先前麟混” Γ=!技術混合鎖存正反器單上時二： i:;!技術混合鎖存正反器電路示意圖。 第二圖域前技術混合料正反器 第二圖係本發明之混合鎖#、 第四圖係第三圖混合鎖分塊示意圖。 施方式之電路圖。心之正脈衝產生單元第—實 27 1313103 第五圖係第三圖混合鎖存正反器之正脈衝產生單元第二實 施方式之電路圖。 第六圖係第三圖混合鎖存正反器之正脈衝產生單元第三實 施方式之電路圖。 第七圖係第三圖混合鎖存正反器之正反器單元之第一實施 方式之電路圖。 第八圖係第三圖混合鎖存正反器之正反器單元之第二實施 方式之電路圖。 第九圖係第三圖混合鎖存正反器之正反器單元之第三實施 方式之電路圖。 第十圖係第三圖混合鎖存正反器之正反器單元之第四實施 方式之電路圖。 第十一圖係本發明混合鎖存正反器之工作時序圖。 第十二圖係本發明混合鎖存正反器用於液晶驅動之電路 圖。 【主要元件符號說明】 混合鎖存正反器 300 時脈輸入節點 301、401、501、601、701、801、901、1001、 脈衝訊號輸入節點 302、402、502、602、702、802、902、1002 數據輸入節點 採樣數據輸出節點 數據輸出節點 303、703、803、903、1003、1203 304、704、804、904、1004 305、705、805、905、1005、1205 緩衝單元輸入節點 306、706、806、906、1006 28 1313103 正脈衝產生單元 反及閘 正反器單元 採樣單元 緩衝單元 保持單元 第一反相器 第二反相器 第三反相器 第四反相器 或閘 互斥或閘 第一 PMOS型電晶體 第二PMOS型電晶體 第三PMOS型電晶體 第一 NMOS型電晶體 第二NMOS型電晶體 第三NMOS型電晶體 第四NMOS型電晶體 第五反相器 第六反相器 第七反相器 電源節點 310、410、510、610、1210 415 330、730、830、930、1030、1230 340、740、840、940、1040、1240 350、750、850、950、1050、1250 349、749、849、949、1049、1249 411、 511、611 412、 512、612 413、 513、613 414、 514、614 516 617 731、831、931、1031 732、 732、832、932、1032 733、 733、833、933、1033 741、 841、941、1041 742、 842、942、1042 743、 843、943、1043 744、 844、944、1044 747、 847、947、1047 748、 848、948、1048 751、851、951、1051The ground discharge is zero volts. This is equivalent to outputting a low voltage to voltage holding unit 1049. If the data input node 1 〇 03 is at a high voltage, the first PM 〇 s type transistor is turned off, and the second NMOS type transistor 1 〇 42 is turned on. Since the first NMOS type transistor 1041 is turned on, the node V10 is discharged to the ground by the first NOMS type transistor 1041 and the second NOMS type transistor 1042 to zero volts, so the fourth NOMS type transistor 1044 is turned off, and the second PMOS type is turned off. The transistor 1032 is turned on and outputs a high voltage to the holding unit 1049. That is, triggered by the positive edge of the clock, the data of the data input node 1003 is sampled, and the sampled data is input by the sampling unit 1040 to the holding unit 1049 via the node 1〇〇4. The holding unit 1049 inverts and holds the sample data before the next data is sampled, and then the sample data is input to the buffer unit 1050 via the node 1006. 25 1313103 The buffer unit 1〇5〇 includes a seventh inverter 1〇51 that inverts the inverted sample data input from the flip-flop unit 1030 via the node 1〇〇6. Thus, the sampled data is restored to the data at the time of the original sampling, and then the original sampled data is applied to the data rounding node 1〇〇5. That is, the buffer unit 1050 provides a buffer for the output signal and provides a more southing drive capability for subsequent circuits. In the above description, the sampling units 74A and 84A in the embodiment of the present invention only include seven MOS type transistors '94〇 and 1〇4〇, including only six M〇s type transistors, which are obvious, compared with the first figure. The sampling unit 14A includes ten 14〇5 type transistors/the sampling unit of the present invention has a small power consumption, although the positive pulse generating unit 310 of the present invention requires more transistors than the prior art shown in the first figure. The number of transistors required for the inverting unit 11 in the sigma latching flip-flop is the same as that of the positive-pulse-inverting 11 unit, and can be separated from the pulse generating unit and the flip-flop unit 70, so that the positive pulse is generated. The unit becomes a common circuit in the liquid crystal driving circuit. Referring to the twelfth figure, the positive pulse generating unit is a common circuit in the liquid crystal driving circuit, and the number of transistors added does not cause an increase in the overall driving circuit. Therefore, the present invention The hybrid latch flip-flop achieves lower power consumption than the prior art. And the use of double-edge trigger mad, rush to generate I " 0 after 'do not change the clock frequency can multiply the capacity of data transmission 篁. The tenth drawing of the work is a hybrid latching flip-flop 300 of the present invention: a sequence diagram. As shown in the eleventh figure, "V (D)', is the data wheel entry node, Wenkang signal waveform map;,, V (CL〇CK)" is the clock signal waveform; "Vrr> ;T. The day of the mouth V (CLK)" node 3 〇 2 pulse signal turbidity 〗 〖V (Q), 'system data output section... heart recognition... skin map, point 305 output δίΐ wave pattern. The tenth_one g 26 ΓϋΗ7Χ~3ΐΓ 4 ·> J / /, - 1313103 does not have a "V(CLK)" waveform pattern generated by the pulse generation unit 410 shown in the fourth figure. Before the clock Τη, v(CLOCK) and V(CLK) are both low voltages, and false "V(q) is low voltage, Tn, lk) appears a positive edge, thus producing __^楚, one by one The pulse V(CLK)' data signal v(D) is sampled. Since Tn, V(D) is the inter-voltage 'V(Q) also transitions to high power>1. When Tn+1, V(CLK) appears another 22f, thus generating a second positive pulse V(CLK), data signal V(D) H羡. Since Tn+1, V(D) is a low voltage, and V(Q) also changes to a low voltage. Because V(D) is low voltage when Tn+2, v(9) remains at low voltage, because V: I: factory is high voltage, V(Q) also changes to high voltage, because Tn+4 ()~ The voltage 'V(9) is still kept at a high voltage, and the voltage (V) is also converted to a low thunder () due to the μ voltage, which is a low initial six x 勹 勹 low 窀 pressure. Although the above disclosed, 9 people latch positive and negative The unit 300 is designed to be used for „this is not limited to this. The driving circuit of the day and night is not good, but it should be stated that 'the invention meets the requirements of the invention patent, 提出 提出 提出 2 = = = = = = = = = = = 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳 较佳In the case of the case = decoration or change m with heart < 荨政修 [schematic description of the description] in the declared patent track. The p-picture is previously collocated. Γ=!Technical hybrid latching flip-flops are on the second two: i:;!Technical hybrid latching flip-flop circuit schematic. The second picture front technology mix positive and negative device second diagram The hybrid lock # of the present invention, the fourth diagram is the third diagram of the hybrid lock block diagram. The circuit diagram of the implementation mode. The positive pulse generation unit of the heart - the real 27 1313103 The fifth figure is the third figure hybrid latch flip-flop The circuit diagram of the second embodiment of the positive pulse generating unit. The sixth figure is the circuit diagram of the third embodiment of the positive pulse generating unit of the hybrid latching flip-flop of the third figure. The seventh figure is the third figure of the hybrid latching flip-flop A circuit diagram of a first embodiment of a flip-flop unit. The eighth diagram is a circuit diagram of a second embodiment of a flip-flop unit of a hybrid latch flip-flop in the third diagram. The circuit diagram of the third embodiment of the flip-flop unit of the inverter. The tenth diagram is the circuit diagram of the fourth embodiment of the flip-flop unit of the hybrid latch flip-flop of the third figure. The eleventh figure is the hybrid lock of the present invention. The working timing diagram of the positive and negative counters. The circuit diagram of the hybrid latching flip-flop is used for liquid crystal driving. [Main component symbol description] Hybrid latch flip-flop 300 clock input node 301, 401, 501, 601, 701, 801, 901, 1001, pulse signal input node 302, 402, 502, 602, 702, 802, 902, 1002 data input node sampling data output node data output node 303, 703, 803, 903, 1003, 1203 304, 704, 804, 904, 1004 305, 705, 805 905, 1005, 1205 buffer unit input node 306, 706, 806, 906, 1006 28 1313103 positive pulse generating unit inverse gate flip-flop unit sampling unit buffer unit holding unit first inverter second inverter third Inverter fourth inverter or gate mutual exclusion or gate first PMOS type transistor second PMOS type transistor third PMOS type transistor first NMOS type transistor second NMOS type transistor third NMOS type transistor Fourth NMOS type transistor fifth inverter sixth inverter seventh inverter power supply node 310, 410, 510, 610, 1210 415 330, 730, 830, 930, 1030, 1230 340, 740, 840, 940, 1040, 1240 350, 750, 8 50, 950, 1050, 1250 349, 749, 849, 949, 1049, 1249 411, 511, 611 412, 512, 612 413, 513, 613 414, 514, 614 516 617 731, 831, 931, 1031 732, 732 , 832, 932, 1032 733, 733, 833, 933, 1033 741, 841, 941, 1041 742, 842, 942, 1042 743, 843, 943, 1043 744, 844, 944, 1044 747, 847, 947, 1047 748, 848, 948, 1048 751, 851, 951, 1051
VDD 29VDD 29