TWI311721B - - Google Patents

Description

1311721 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an instruction of a micro-control (four) system and an execution method thereof, and _ is an instruction related to a multi-micro control system and an execution method thereof. [Prior Art] With the advancement of _ technology, the services that computers can provide and Wei are more and more comprehensive.

, 'Think of σ computer. Dirty, the computer program is the computer's logic of thinking. By starting all the hardware and reading the program at the same time, the computer can provide (4) the method to solve the problem, or the task to be fulfilled when finished. The program that directs the computer to execute the series of processing procedures and steps is composed of a series of instructions or a combination of statements. The machine language is the most basic instruction, which is synthesized by the operation code "7G". The relationship between the opcode and the operand is the operation of the operand with the data of the operand. At the same time, in order to simplify the editing of the program, a method of expressing the command and the concatenation in a shortcode manner has been developed. For example, in the county element (4), it may be address information, or simple thermal information, and provide various motion tweets in the operation code, data transfer, arithmetic operation, operation, and bit operation. Please refer to the following formula (1), which is a conventional _ instruction and its included opcodes and operands: MOV A, REGA ', 'MOV is the opcode' which means "data transfer" and a And 嶋 为 为 两个 两个 两个 两个 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自 各自Data is stored in the accumulator . Fine 'before the computer executes the instruction, it must pass the series of decoding and analysis work' to execute the operation unit and the operation unit - the second: = new interpretation - and the - (6) diagram Points _ know: = when referring to the first method 'in the execution of the instruction (1) instruction, first, in the step of the test, the second party's executive bus 12 reads the memory i: the benefit 16 from the data one __ instruction In the solution 16, 'put the data store 161+ in the register A162' to control '4λ: Α.| 3S 1 λ ., . Τ"', in step S03, according to ^(10)卿', the curry 162 is 敝The accumulator 161 is read in to complete the execution of the instruction of equation (1). According to the above-mentioned control, the age of the design is based on the premise that there is only one control (or only one main controller) in the system, and it must be controlled by ^1. When the implementation of the micro-control core logic of one or more executable programs in the township system (and possibly each of the corresponding scratchpads or other related circuit units), the above-mentioned conventional instructions will be difficult to achieve. Parallel multiplex processing; even if it is reluctant, software writing is bound to be very complicated. For multiple micro-control systems, when the program is programmed, the unclear units can share internal resources, read program execution and help (4), and (4) important, such as private but can improve the parallel processing of multiple micro-controls. Responding to uglyness in a timely manner can also reduce system costs. In view of the above, the present invention is directed to a multi-micro control system that can solve the above problems, and proposes an instruction suitable for a multiple micro-control system and an execution method thereof, and executes the instruction through multiple micro-control systems to achieve parallel multiple The efficiency of processing, and effectively improve the ability of the control system operation processing 1311721. SUMMARY OF THE INVENTION The main object of the present invention is to provide a multi-difficult (four) system age, including - opemtion code and at least - multiple micro control core logic selection operation elements (operand for selection a_g mUltiple MQJ c 〇re to (6)), and when there are y ' or (10) below the micro control clutter logic, at least N number of bits are needed to select the micro control core logic, wherein the N number of bits can be It is a continuous number of bits, or a number of discontinuous bits, and the arithmetic code can be used to provide an operation when the instruction executes the program. The multiple micro-control core logic selection operation element can be specified when the instruction is executed. In the multi-micro-control woven system, when the command is executed, the lion's micro-control relay logic and its sub-operational elements (shirts. ah (4) information; using this ^7, without writing complicated code, can be simple and The micro-control core logic and its sub-operating elements to be selected in the multiple micro-control system are explicitly indicated. The other object of the present invention is to provide a multiple micro-control system which can be mixed according to the above instructions. The purpose--the purpose is to provide a multi-recording control (10) system instruction execution method, and extract the instruction through the main operation micro-control unit and complete the decoding, and use the multiple micro-control kernel in the instruction to the logic selection operation 1 to specify The selected micro-control core and logic cooperate to perform the operation of the operation code, and the data of the selected micro-control core and the logic are directly written to the designated position of the other selected micro-control core logic. With this instruction and method, different micro-control core logics in multiple micro-control secrets can share resources and control each other, realize the ability to process several programs in parallel, and improve the performance of the operation. 1311721 The arithmetic element contains "M3" The two parts of "A" mean the core logic M3 of the microcontroller, and one of the internal positions A and the sub-position A corresponds to the third accumulator. Therefore, the multi-micro control core logic selects the operation leg. Corresponding to "the third accumulator in the third microcontroller core logic"; and in the multi-micro control core logic selection operand _G2A, it also contains the micro-control Controller = heart logic address M2, and the child of the detail (10) _, the position of the scorpion is that it can not be temporarily stored n 2A 'so' this multi-face control stealing heart logic 雠 operation Yuanqing hidden system corresponds to Lu 4 "in The second microcontroller core logic register 2A". Therefore, the overall animal provided by this instruction is interpreted as "storing the data of the second microcontroller core logic register 2-8 into the third microcontroller core. The logic is the third accumulator. The above is only the implementation of the invention, except for the data transfer operation in equation (2), which is commonly used in other computational operations, such as arithmetic operations. Logic, nose, _ tree _ 峨, 歧 ( (4) M in the implementation of the ^ calculations are all in the side of her slack. At the same time, the core of the core system of the selection of Na Wei - 峨元中, this is in addition to The source address, the destination p, the gift of 'K_____, to mention the instruction action corresponding to the operation element, such as the instruction provided by the formula (3) cap: MOV M1REGIB, #55f{ ( 3) Among them, MOV is still the opcode, the pottery 矣 _ v ^ shell material moved, and M1REG1B and #55H: multi-record Control _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ is an immediate constant data, 1311721 which is the information of "". Therefore, the overall action provided by this instruction can be interpreted as "moving the 55H to the temporary storage $ib of the -microcontroller core logic." The above formula (2) is a combination of the operation code lap 3 & two multi-face control operation thin surface operation unit; the equation (3) is a combination of the operation code collocation-multiple micro control core logic selection operation element and one other operation element; In addition to the 'only-computing-matching-multiple micro-control core logic selection operand combination, of course, is also possible, such as the instructions provided in equation (4):

POP M3PC (4) In this command, POP is the opcode 'meaning "send the contents of the stack to the specified location", and c is the only one in the "transportation" and is - multi-micro control The logic selects the operand, which means "the third micro-controls the process of the difficult logic." The overall action provided by the formula (4) Lai Ling can be interpreted as "sending the stack memory_content to the third micro-control private logic. In the program counter." The references to the "multiple micro-control core logic selection operands" in the equations (2)-(4) include the parts representing the micro-control core logic (M1, M2, M3, etc.) and the sub-operation elements (A, PC, etc.) indicating the sub-positions. . However, it is also possible that the instruction 4 needs to define the micro-control core logic without defining its sub-location. The scale "Dou New Butterfly _ Collection Na (four) Yuan" contains only the part that indicates difficulty to steal, and (4) must contain the sub-operating element that represents the sub-position. For example, 'hypothetical tearing (four) careful "Lai __ stacked memory", then in the age of the town, there is no need to include sub-operating elements that represent sub-positions. PUSHPC M4 _ (5) This instruction means "«read (four) core Take care of the counter _ material to the stack memory 1311721 J ο In addition, 'finely on the material, fine higher _ grammar to (four) age 4 in fact, if translated into low-order binary code, test the various equations (2) - (4), It will be represented by a series of binary digits, iux shot------------------------------------------------------------------------------ For example, if you use the 16-bit binary code to represent the above instructions, you can use the most The five-digit number of the meaning bit Signifi is the beginning of the operation code, and the other digits are used to represent the position of the operand. The heart is below the n-digit, and the number of _bits is available. To select two micro-control core logics, therefore, when there are 2N or 2 micro-control core logics, 'f must have at least n bits to select the desired micro-control, logic (conceptually, this N-bit The two-touch code can be regarded as the "identification code" of the micro-control core logic (identi Flcati〇n, ID)). In the present invention, the arrangement of the number of bits is a bit of a continuation of the bit, and is also a dissimilarity of the forest; the (four) record, in the general case can be placed in the position of the operand, but can also be placed in the operation position Or both. For example, assuming that the instruction is as exemplified above, the 6-bit binary stone is represented, and the instruction set has a total of 24 arithmetic codes to be defined. Since there are 24 kinds of opcodes, 2<=^n owes the need for five-element wire. 'Because the test uses the five-digit number starting from the most significant bit as the indication of the operation code check', the other digits are used as the representation operand. Inspection. At this point, it is assumed that the multiple micro-control system makes a micro-control center-sewed seam (so three-digit knowledge (four) is needed to lack the micro-control core logic). According to the present invention, the sixth to the first reading, or the A continuous bit such as a 16-bit number is used to indicate the default control, and a non-contiguous bit such as the first and the eleventh may be used to represent the specified micro-control core logic. And because. 1311721 There are 24 kinds of arithmetic code 'so you can make the face to 1G1U to represent the i-th to μ-th operation, and let ιΐχχχ denote the 24th kind, and let U_ to η out the silky township_to the tree core logic to execute the 24th kind Operation ^ At this time, in the instructions from the 23rd to the 23rd operations, the micro-control kernel is specified: the three bits of the logic are located in the position of the operand; and in the instruction of the 24th operation, the micro-control core is specified, The three bits of logic are located in the location of the opcode. In the age of the 24th operation mentioned above, the miscellaneous _ heart logic is located in the position of the opcode, but conceptually, we can also regard the opcode as a two-digit number starting from the coffee, and The control core logic selects the operand as the number after the start of the third digit. The above is an introduction to the instructions of the multiple micro-control system, and the method of execution of the instructions will be further proposed. For example, the instruction in the above formula (2) is taken as an example, and please refer to the second (4) diagram and the - (b) diagram at the same time, which are divided into two parts: the multi-micro control system and the execution method of its age. In the execution of the instruction of the equation (2), first, in the step su, in the multiple micro-control system composed of the N micro-control core logics 30 32, each micro-control core logic has a register 262, 263, 282 therein. , 302, 322, 323, 324, using the first micro-control core logic 26 as the main operation micro-control unit, and taking the data in the '2' through the medullary flow row 22 and temporarily storing it to the instruction temporary storage In step S12+, the first-micro-control core logic 26 decodes the instruction of the equation (2) and determines that the content of the read-only (2) instruction is "storing the data in the register 2A282 of the second micro-control core logic 28 into the first The third micro-controller core logic 30 of the third accumulator 3〇1, in step S13, according to the result of the first micro-control core logic 26 read out, the first micro-controller core logic 26 commands the second micro-control core Logic 28, to read the data in which the scratchpad 2A commits 2' and write this data to the third accumulator of the third micro control core logic 30. 3〇1 13 1311721 [Simplified description] First ( a) The figure is a block diagram of a conventional control system. The first (b) diagram shows the instruction execution method of the conventional control system. The second (a) diagram is a block diagram of a system according to an embodiment of the present invention. The second (b) diagram is an instruction execution method according to an embodiment of the present invention. [Main component symbol description] 10 memory 12 data bus 14 instruction register 16 controller 162 register 161 accumulator 20 memory 22 data bus 24 instruction register 26 first microcontroller core logic

262 register 1A 263 register 1B 261 first accumulator 28 second microcontroller core logic

282 register 2A 1311721 281 second accumulator 30 third microcontroller core logic 302 register 3A 301 third accumulator - 32 Nth microcontroller core logic

. 322 Register NA

323 register NB > 324 register NC 321 Nth accumulator

Claims (1)

1311721 ^ . ^· ;: X. Applying for a patent garden: 1. The instruction execution method of the singular micro-control system can be applied to a multi-micro control system. The main operation micro control unit extracts an instruction, and the instruction is composed of an operation code and at least one multi-micro control core logic selection operation unit; performing a decoding task of the instruction in the main operation micro control unit; According to the silk of the decoding task, the enchantment operation micro-relay unit title Wei right-operation operation performs the operation operation in the micro-control unit corresponding to at least one address specified by the multiple micro-control core logic selection operation element. 2. The instruction execution method of the multiple micro control system according to claim 1, wherein the digital micro control system is composed of a plurality of microcontroller core logics, and any of the microcontroller core logic shots As a touch computing micro control unit. 3. If applying for the multi-micro-control woven age implementation of the second item described in item 2, the multi-micro control key __ operation element is to select at least N consecutive or continuous reading elements to select Corresponding to 2% 2N or less of micro-control core logic, where N is a natural number. 4. The method for executing an instruction of a multiple micro-control system according to claim 3, wherein the at least N number of bits are located in a shed, or an operation, or - part is located in the operation unit and the other part is located in the operation code . 5. The method for executing multiple micro-controls (10) and the command execution method as described in the first paragraph of the patent application, wherein the multi-touch successor _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ One of the subunits inside the control unit. 6. The method for executing an instruction of a multiple micro-control system as described in claim 2, wherein: 17 1311721, a I? arbitrary micro-control unit can pass the instruction with any microcontroller core logic or It is to communicate with the surrounding units.疋', a multi-micro-control system, comprising a plurality of micro-control core logics, each micro-control core logic has a micro-control _ heart logic identification code encoded in a binary manner, wherein the system performs and specific micro-controls her At the time of the relevant instruction, the micro-control core logic identification code of the specific micro-control core logic is included in the age towel. 8. A multi-micro-control system consists of a plurality of micro-control gamma (four) series, each micro-control core logic has a micro-control core logic identification code encoded in binary mode, where 'the system is executed and specific micro-control When the core logic is associated with an instruction, the instruction obtains the micro control core logic identification code from a location where the micro control core logic identification code is stored. 9. The multiple micro-control system of claim 8, wherein the instruction comprises an opcode position and an operand position, and the micro-control core logic identifier is located within the operand position, within the opcode position, or One part is in the operand position and the other part is in the opcode position.