13.1140013.11400
• I 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種功率放大器，特別是關於一種西格 瑪-德爾塔(sigma-delta)型功率放大器。 【先前技術】 傳統音訊功率放大器的效率低，造成產生的熱量高， _ 必須使用大型散熱器（heat sink)幫助散熱，因此實體裝置的 體積龐大。近年來為了縮小放大器的體積，便有高效率的 設計方案提出，其中最普遍的方式是使用D類(class D)放大 器’又稱為切換式放大器（switching amplifier)。此類放大 • 器的工作原理，乃是利用高頻調變方法將類比或數位的輸 . 入訊號轉換為二階(two-level)的輸出訊號，再將此二階的 訊號送給功率級(power stage)，以切換功率級當中的功率 開關（power switch)。這些功率開關產生的熱量極低，因此 φ 放大器的效率大幅提高。 在習知的D類放大器中，大多數的系統係採用脈寬調 變（Pulse Width modulation; PWM)架構。典型的音訊PWM 放大器可以在介於100 KHz到500 KHz之間的切換頻率工 作’更高的切換頻率可以降低失真（distortion)，卻會導致 較低的效率，這是因為輸出波形中超量的轉態（transition) 所造成的，每一次轉態都要耗費少許能量。以典型的350 kHz時脈頻率而言，習知的PWM型D類放大器的失真/雜訊 性能表現並不是很好。 1311400 另一種較不普遍的調變技術係使用西格瑪_德爾塔調 變器將類比或數位的輸入訊號轉換為一串較高取樣頻率 的1和〇的數位訊號，典型的取樣頻率約為最高音訊頻率的 64倍。西格瑪-德爾塔調變器經常在類比數位轉換器 (Anal〇g-to_Digitai Converter; ADC)中使用，用來將類比的 3讯訊號轉換為數位的1位元串流。由於西格瑪_德爾塔調 憂的精確度較高，使用西格瑪-德爾塔調變的架構比使用 φ PWM調變的架構具有較佳的失真特性，但是切換頻率明顯 高出很多，因此效率較低。 為進一步說明，圖1顯示習知的西格瑪_德爾塔型功率 放大器10，其包括西格瑪_德爾塔調變器12將輸入訊號vin • 轉換後給輸出級14，輸出級14包括量化器16驅動功率級18 、 ’因而產生輸出訊號Vout以供推動制队，量化器π的輸出 訊號亦經過反相器13產生負回授給西格瑪_德爾塔調變器 12。西格瑪_德爾塔調變器12和量化器16可以使用類比電路 φ 、數位電路或混合類比及數位電路來實現。在以類比電路 • 實現的系統中，輸入訊號Vin是類比信號，輸出訊號v〇ut 是1位元數位訊號’西格瑪-德爾塔調變器12的積分器通常 疋類比積分器，可以使用離散時間（discrete time)切換電容 (switching capacitor)技術或標準的連續時間（continu〇us time)類比線性技術實現。在以數位電路實現的系統中，輸 入訊號Vin是多位元數位訊號，輸出訊號^价是丨位元數位 訊號，西格瑪-德爾塔調變器12的積分器是離散時間積分器 ，以諸如加法器和暫存器等標準的數位硬體來實現。在以 1311400 混合類比及數位電路實現的系統中，例如前幾級的積分是 由類比電路完成，而後幾級是採用數位電路，輪入$號 是類比信號，輸出訊號Vout是1位元數位訊號。從量化器 提供給西格瑪-德爾塔調變器12的負回授可以大力地抑制ι 位7G量化所產生的量化雜訊，使得在有限頻帶中的訊噪比 (Signal-to-Noise Ratio; SNR)很高。 — 在此類電路的設計中，穩定性和抑制量化雜訊二者之 • 間必須妥協。量化雜訊的輸入對輸出的轉移函數 function)通常被定義成某種古典的高通濾波器函數，例如 謝比謝夫(Chebychev)設計。穩定性和抑制量化雜訊之間的 關係可以簡單地說明如下：具有積極抑制雜訊的轉移函數 ' 的電路在較低輸入準位變得不穩定，而具有較不積極抑制 、 雜訊的轉移函數的電路擁有在較大的輸入範圍仍然穩定 的特性。將西格瑪-德爾塔調變技術應用在D類放大器的缺 點之一在於’為維持系統之穩定度必須要有較高之轉態率 • (transition rate)，因而導致功率級18當中的切換損失 (switching loss)較大’因而降低了效率。以圖ι所示的功 率放大器10為例，如果使用7級的西格瑪-德爾塔調變器12 ' 操作於12MHz的時脈速率，正常音訊取樣率為48 kHz，其 轉態率可達到典型的350kHz頻率的PWM系統的10倍。除 了功率消耗高，高切換速率也會產生電場干摄 (Electro-Magnetic Interference; EMI)的問題。通常這類調 變器具有頻率在100kHz以上的強大頻譜成分，可能弓丨發對 射頻（Radio Frequency; RF)或其他裝置的干擾。 7 1311400 概要地說’將西格瑪_德爾塔調變技術應用在D類放大 器時，其切換速率與輸入訊號Vin的振幅大小是相關的， 切換速率太低時容易使西格瑪-德爾塔調變器12變得不穩 定，但是切換速率太高會增加功率消耗及EMI，利用切換 速率控制電路可以降低切換頻率，且兼顧西格瑪-德爾塔調 變器12的穩定度。 — 為了降低西格瑪-德爾塔調變器的切換頻率，美國專利 _ 第6,924,757號提出利用調整磁滯(hysteresis)大小來達成。 圖2所示係該專利提出的西格瑪-德爾塔調變模組2〇，其中 西格瑪-德爾塔調變器22與一般使用的裝置相同，但是量化 器24係具有可變磁滞的1位元比較器’類比數位轉換器26 ' 將輸入訊號Vin轉換為數位訊號，藉以從檢索表28中選取 、 磁滯值，決定篁化器24的磁滯大小，達到控制切換頻率的 目的。此系統的缺點之一是，由於引入量化器磁滯，高階 西格瑪-德爾塔調變器的穩定性將會降低，因此必須依照輸 • 入訊號Vin的每一個範圍預設在檢索表28中的磁滯值的最 佳值。另外，因為量化器24的磁滯是離散的，容易引發其 他的問題。再者，量化器24必須使用可變磁滯的装置，電 路較複雜也較昂責，而增加的數位轉換器26和檢索表28讓 晶片變大而且提高成本。 的功率放大器10還有另一項問題，由於功率級18 不是線性的，從量化器16的輸出產生負回授並未精確地表 達真實的輸出訊號V_，因此引人的誤差會讓放大器1〇的 性能劣化。 ° 13.11400 因此，一種改 所冀。 良的西格瑪-德爾塔型功率放大器，乃為 【發明内容】 本么明的目的之―，在於提出一種可調整切換頻率的 西格瑪·德爾塔型功率放大器及其調變方法。 根據本發明，一種西格瑪-德爾塔型功率放大器包括一 _西格瑪·德_塔調變器、-輸出級以及-介㈣二者之間的 增益控制器，該增益控制器根據一與輸人訊號相關之訊號 將及西格瑪-德爾塔調變器提供給該輸出級的轉換訊號放 大或縮小後再提供給該輸出級，藉以降低其調變的轉態率 - 0 、 根據本發明，一種西格瑪-德爾塔型功率放大器的調變 方法包括在一西格瑪_德爾塔調變器提供一轉換訊號給一 輸出級之前，根據一與輸入訊號相關之訊號將該轉換訊號 • 放大或縮小後再提供給該輸出級，藉以降低該調變的轉態 率。 ’一 【實施方式】 圖3顯示根據本發明的西格瑪-德爾塔型功率放大器3〇 ’西格瑪-德爾塔調變器32用來將輸入訊號Vin轉換為訊號s ’被增益控制器36放大或縮小為訊號gS，g表示增益，係 根據輸入訊號Vin的大小決定，輸出級34再從訊號gS產生 輪出訊號Vout以供推動喇叭。在典型的系統中，輸出級34 1311400 包括量化器16及功率級18，作θ 級叫堇包括量化器16，沒有:在某些數位系統中，輸出 是輪出訊號V〇Ut。較佳者，負718’量化器16的輸出就 相器33提供給西格瑪-德爾塔調：=== AA j, . 艾态32,如此可以反應真實 =即使功率級18的線性度較 性能 過於劣化。此類設計在某此廉田 控制電路32、33、36及16；；=例如將功率級18與其他 ,〇在冋一晶片上時，比較合適 2 的實施财，例如1 力率㈣是外掛的，也可以 _輸出產生負回授訊號，如圖3中的元件符號 35所不在不同的只施例中，也可以將輸入訊號偷放大 或縮小後做為決定增益g的控制訊號，如圖3巾所示，具有 增益k的放大器38從輸入訊號Vin產生訊齡心給增益控制 器36，控制其增益g。因為增益g隨著輸入訊號Vin的大小 改變’所以西格瑪-德爾塔調變器32的切換頻率也跟著改變 # 圖4顯示增益控制器36的一個實施例，可變增益放大 器40的輸入端連接訊號s，輸出訊號的，輸入訊號vin控制 可變增ϋ放大器40的增盈。可變增益放大器4〇可以使用電 壓控制增益放大器或電流控制增益放大器。 圖5顯示一個全類比實現的西格瑪_德爾塔調變模組， 其使用7級的類比西格瑪-德爾塔調變器32，負回授係從輸 出訊號Vout經反相器33及電阻RFB的路徑提供。在增益控制 器中，運鼻放大益42的非反相輸入端連接一參考電壓，在 此實施例中為接地’運算放大器42的反相輸入端和輸出端 1311400 之^接電阻44’可變電阻46連接在運算放大純的反相 輸^牙西格瑪-德爾塔調變器32之間，電阻44和可變電阻 46的阻值决疋增益控制器的增益，藉由改變可變電阻46的 阻值即可改變增益控制器的增益。可變電阻46包含電阻 48及50串聯在運算放大器42的反相輸人端和西格瑪-德爾 塔，變器32之間’以及電晶體52及54分別並聯至電阻5〇， 電=體52的閘極連接輸入訊號vin，電晶體54的閘極從反 相器56連接輸入訊號Vin的反相訊號，電晶體52及54的導 通阻值隨輸入訊號Vin的大小改變。假設電阻48的阻值為 R1、電阻50的阻值為尺2、電阻44的阻值為尺3，當輸入訊 號Vin為〇日^，電晶體52及54完全關閉，可變電阻46等於電 阻48串聯電阻5〇,其等效阻值為R1+R2 ’因此增益控制器 的增益為 g=R3/(Rl+R2) [公式 υ 當輸入訊號Vin的絕對值很大時，電晶體52或54完全開啟 ，電阻50被旁通，可變電阻46的等效阻值為R1，因此增益 控制器的增益為 g=R3/Rl [公式2] 當輸入訊號Vin的絕對值由〇逐漸變大時，電晶體52或54由 完全關閉而逐漸開啟，電晶體52的阻值為Rmi、電晶體“ 11 1311400 的阻值為Rm2 ’可變電阻46的等效卩且值為 R1+(RM1//R2//RM2)，因此增益控制器的增益為 ’ g=R3/[Rl+(RM1//R2//RM2)] [公式 3] 圖6係一變化的實施例，可變電阻46的等效阻值只利用輸 入訊號Vin控制電晶體52來決定。圖7係另一個變化的實施 論例’運算放大器58的反相輸入端和西格瑪_德爾塔鋼變器32 之間連接電阻60，可變電阻62連接在運算放大器S8的反相 輸入端和輸出端之間，藉輸入訊號Vin調整可變電阻62的 阻值，以控制增益，當輸入訊號Vin的絕對值較大時，可 - 變電阻62的阻值也較大。在圖5至圖7這類實施例中，增益 _ 控制器的增益是連續的值。 圖8顯示增益控制器36的另一個實施例，共輪入端的 多個放大裔64各具有不同的增益，分別以“到糾表示，第 • ·*個放大器64的增益為幻，多工器64受輸入訊號Vin控制從 该多個放大器64中選擇一個，以產生訊號的給輸出級34。 在一變化的實施例中，如圖9所示，多工器受輸入訊號 Vin控制’將訊號s連接至多個共輸出端的放大器7〇之中的 一個’以產生訊號gS給輸出級34。在圖8及圖9這類實施例 中’增益控制器的增益是離散的值。 圖10顯示增益控制器36的又一個實施例，放大器72將 訊號s放大或縮小為訊號gS給輸出級34，類比數位轉換器 74將輸入訊號Vin轉換為數位訊號，據以在增益表76中查 12 1311400 找’因而決定放大器72的增益g。 圖Π顯示增益控制器36的再一個實施例，數位放大器 78將訊號S放大或縮小為訊號gS給輸出級34，類比數位轉 換器80將輸入訊號Vin轉換為數位訊號控制數位放大器78 的增益g。 為了與習知技術對照，圖12至圖14顯示圖3之功率放 大器30的模擬結果，圖15至圖20顯示不使用本發明之增益 控制器36(圖1)的模擬結果。如圖12所示，在-60dB的小輸 入訊號時，雜訊底層（noise floor)在-100dB以下，而且在音 訊頻帶（20Hz至20kHz)中的雜訊底層更可達-120dB以下， 顯示雜訊小，而在全尺度（full scale)的大輸入訊號時，如 圖13所示，雜訊仍然維持在低水準，顯示功率放大器3〇的 良好性能。圖14係切換頻率對輸入訊號大小的關係圖，當 輪入訊號大小Vin<0.5Vmax時(Vmax表示輸入訊號Vin的最 大振幅）’切換頻率約在3 70 kHz，而在輸入訊號大小Vin 為0.7\^^乂至0.8¥11^\時，切換頻率升高到約5501^2，選 擇適當的設計變數可以降低此範圍的切換頻率。圖15顯示 在小輸入訊號時’習知的功率放大器1〇可以正常工作，然 而在大輸入訊號時，如圖16所示，西格瑪-德爾塔調變器12 變得不穩定’所以雜訊底層上升至-50dB。圖17顯示在輸 入訊號大小Vin>0.7Vmax時’西格瑪-德爾塔調變器π已經 變得不穩定。圖18至圖20所示係提高切換頻率後的結果， 為了在全尺度的輸入訊號時得到穩定的西格瑪_德爾塔調 變器12 ’切換頻率必須高達1MHz。因為切換頻率提高， 13 1311400 - , 所以功率消耗和EMI也會跟著提高。 【圖式簡單說明】 圖1顯示習知的功率放大器； 圖2顯示習知具有磁滞控制的西格瑪-德爾塔調變模組 ， 圖3顯示根據本發明的功率放大器； _ 圖4顯示增益控制器的一個實施例； 圖5顯示一個全類比實現的西格瑪-德爾塔調變模組； 圖6顯示圖5變化的一個實施例； 圖7顯示圖5變化的另一個實施例； - 圖8顯示增益控制器的另一個實施例； * 圖9顯示圖8變化的一個實施例； 圖10顯示增益控制器的又一個實施例； 圖11顯示增益控制器的再一個實施例； _ 圖12顯示本發明的功率放大器在小輸入訊號時的模 擬結果； 圖13顯示本發明的功率放大器在全尺度輸入訊號時 的模擬結果； 圖14顯示本發明的功率放大器的切換頻率對輸入訊 號大小的關係圖； 圖15,4示驾知的功率放大器在低切換頻率、小輸入訊 號時的模擬結果； 圖16顯不$知的功率放大器在低切換頻率、全尺度輸 14 1311400 入訊號時的模擬結果； 圖1示t知的功率放大器在低切換頻率下切換頻 率對輸入訊號大小的闕係圖； 圖18顯示習知的功率於 刀半敌大器在尚切換頻率、小輸入訊 號時的模擬結果； 圖20顯示習知的功率放大 率對輸入訊號大小的關係圖。 【主要元件符號說明】 圖19顯不習知的功率放大 入訊號時的模擬結果；以及 器在高切換頻率、全尺度輸 器在高切換頻率下切換頻 1 〇 功率放大器 12西格瑪-德爾塔調變器 13 反相器 14 輸出級 16量化器 18 功率級 20西格瑪-德爾塔調變模組 22西格瑪-德爾塔調變器 23 反相器 24量化器 26 類比數位轉換器 28檢索表 30功率放大器 15 1311400• I. INSTRUCTION DESCRIPTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a power amplifier, and more particularly to a sigma-delta type power amplifier. [Prior Art] The efficiency of the conventional audio power amplifier is low, resulting in high heat generation. _ A large heat sink must be used to help dissipate heat, so the physical device is bulky. In recent years, in order to reduce the size of the amplifier, a highly efficient design has been proposed, the most common of which is the use of a class D amplifier, also known as a switching amplifier. The operation of this type of amplifier is to convert the analog or digital input signal into a two-level output signal by using the high-frequency modulation method, and then send the second-order signal to the power stage (power). Stage) to switch the power switch in the power stage. The power generated by these power switches is extremely low, so the efficiency of the φ amplifier is greatly improved. In the conventional class D amplifier, most systems use a Pulse Width Modulation (PWM) architecture. A typical audio PWM amplifier can operate at switching frequencies between 100 KHz and 500 KHz. Higher switching frequencies reduce distortion but result in lower efficiency due to excessive turn in the output waveform. Caused by the transition, each transition takes a little energy. The distortion/noise performance of the conventional PWM type D amplifier is not very good at a typical 350 kHz clock frequency. 1311400 Another less common modulation technique uses a sigma-delta modulator to convert an analog or digital input signal into a series of higher-sampling 1 and 数 digital signals. The typical sampling frequency is about the highest audio. 64 times the frequency. Sigma-delta modulators are often used in analog-to-digital converters (Anal〇g-to_Digitai Converters) to convert analog 3 signals into digital 1-bit streams. Due to the high accuracy of Sigma-Delta tuning, the architecture using Sigma-delta modulation has better distortion characteristics than the architecture using φ PWM modulation, but the switching frequency is significantly higher and therefore less efficient. For further explanation, FIG. 1 shows a conventional sigma-delta type power amplifier 10 that includes a sigma-delta modulator 12 that converts an input signal vin • to an output stage 14 that includes quantizer 16 drive power. Stage 18, ' thus produces an output signal Vout for driving the team, and the output signal of the quantizer π is also negatively fed back to the sigma delta modulator 12 via the inverter 13. The sigma delta modulator 12 and quantizer 16 can be implemented using analog circuits φ, digital circuits, or mixed analog and digital circuits. In a system implemented by analog circuits, the input signal Vin is an analog signal, and the output signal v〇ut is a 1-bit digital signal. The integrator of the sigma-delta modulator 12 is usually an analogy integrator, and discrete time can be used. (discrete time) Switching capacitor technology or standard continuous time (continu〇us time) analog linear technology. In a system implemented by a digital circuit, the input signal Vin is a multi-bit digital signal, the output signal is a digital bit signal, and the integrator of the sigma-delta modulator 12 is a discrete-time integrator such as addition. Standard digital hardware such as registers and scratchpads. In a system implemented with 1311400 mixed analog and digital circuits, for example, the integration of the first few stages is performed by an analog circuit, and the latter stages are digital circuits. The rounded $ is an analog signal, and the output signal Vout is a 1-bit digital signal. . The negative feedback provided from the quantizer to the sigma-delta modulator 12 can greatly suppress the quantization noise generated by the ι 7G quantization, so that the signal-to-noise ratio (SNR) in the finite frequency band is achieved. ) Very high. – In the design of such circuits, the stability and suppression of quantization noise must be compromised. The transfer function of the quantization noise input to the output function is usually defined as a classical high-pass filter function, such as the Chebychev design. The relationship between stability and suppression of quantization noise can be briefly explained as follows: A circuit with a transfer function that actively suppresses noise becomes unstable at a lower input level, and has a less active suppression, a transfer of noise. The function's circuitry has features that are stable over a large input range. One of the disadvantages of applying sigma-delta modulation technology to a class D amplifier is that 'the transition rate must be high in order to maintain system stability, resulting in switching losses in power stage 18 ( The switching loss) is larger' thus reducing the efficiency. Taking the power amplifier 10 shown in FIG. 1 as an example, if a 7-stage sigma-delta modulator 12' is used to operate at a clock rate of 12 MHz, the normal audio sampling rate is 48 kHz, and the transition rate can reach a typical rate. 10 times the PWM system with 350kHz frequency. In addition to high power consumption, high switching rates also create problems with Electro-Magnetic Interference (EMI). Usually such modulators have strong spectral components with frequencies above 100 kHz, which may interfere with radio frequency (RF) or other devices. 7 1311400 In summary, when the sigma-delta modulation technology is applied to a class D amplifier, the switching rate is related to the amplitude of the input signal Vin. When the switching rate is too low, the sigma-delta modulator 12 is easy to be used. It becomes unstable, but the switching rate is too high, which increases power consumption and EMI. The switching rate control circuit can reduce the switching frequency and take into account the stability of the sigma-delta modulator 12. - In order to reduce the switching frequency of the sigma-delta modulator, U.S. Patent No. 6,924,757 proposes to use the hysteresis size. Figure 2 shows the sigma-delta modulation module 2〇 proposed by the patent, wherein the sigma-delta modulator 22 is the same as the commonly used device, but the quantizer 24 is a 1-bit variable magnetic hysteresis. The comparator 'analog ratio converter 26' converts the input signal Vin into a digital signal, thereby selecting the hysteresis value from the retrieval table 28, and determining the hysteresis size of the chemist 24 to achieve the purpose of controlling the switching frequency. One of the disadvantages of this system is that the stability of the high-order sigma-delta modulator will be reduced due to the introduction of the quantizer hysteresis, so it must be preset in the search table 28 in accordance with each range of the input signal Vin. The optimal value of the hysteresis value. In addition, since the hysteresis of the quantizer 24 is discrete, it is easy to cause other problems. Furthermore, the quantizer 24 must use a device with variable hysteresis, which is more complicated and more cumbersome, and the increased digitizer 26 and look-up table 28 make the wafer larger and costly. Another problem with the power amplifier 10 is that since the power stage 18 is not linear, generating a negative feedback from the output of the quantizer 16 does not accurately represent the true output signal V_, so an inductive error would cause the amplifier to 〇 The performance is degraded. ° 13.11400 Therefore, a change. A good sigma-delta type power amplifier is the object of the present invention. It is to propose a sigma delta type power amplifier with adjustable switching frequency and a modulation method thereof. According to the present invention, a sigma-delta type power amplifier includes a gain controller between a sigma-de-tower modulator, an output stage, and a (four), the gain controller is based on an input signal The associated signal and the conversion signal provided by the sigma-delta modulator to the output stage are amplified or reduced and then supplied to the output stage, thereby reducing the transition rate of the modulation - 0 , according to the invention, a sigma - The modulation method of the delta type power amplifier includes: before a sigma-delta modulator provides a conversion signal to an output stage, the conversion signal is enlarged or reduced according to a signal related to the input signal, and then supplied to the The output stage, in order to reduce the transition rate of the modulation. FIG. 3 shows a sigma-delta type power amplifier 3 〇 sigma-delta modulator 32 for converting the input signal Vin into a signal s 'by being amplified or reduced by the gain controller 36 according to the present invention. For the signal gS, g represents the gain, which is determined according to the size of the input signal Vin, and the output stage 34 generates the turn-out signal Vout from the signal gS for driving the speaker. In a typical system, the output stage 34 1311400 includes a quantizer 16 and a power stage 18, the θ stage 堇 includes a quantizer 16, and no: in some digital systems, the output is a turn-off signal V 〇 Ut. Preferably, the output of the negative 718' quantizer 16 is supplied to the sigma-delta tune by the phaser 33: === AA j, . Ai state 32, so that it can be true = even if the linearity of the power stage 18 is more than the performance Deterioration. Such a design is in some of the field control circuits 32, 33, 36 and 16;; = for example, when the power stage 18 is connected to the other, it is suitable for the implementation of 2, for example, 1 force rate (four) is plug-in The output may also generate a negative feedback signal. As shown in Figure 3, the component symbol 35 is not in a different embodiment. The input signal may be amplified or reduced as a control signal for determining the gain g, as shown in the figure. As shown in FIG. 3, the amplifier 38 having the gain k generates a signal from the input signal Vin to the gain controller 36 to control its gain g. Since the gain g changes with the magnitude of the input signal Vin, the switching frequency of the sigma-delta modulator 32 also changes. Figure 4 shows an embodiment of the gain controller 36 with the input of the variable gain amplifier 40 connected to the signal. s, the output signal, the input signal vin controls the gain of the variable booster amplifier 40. The variable gain amplifier 4〇 can use a voltage controlled gain amplifier or a current controlled gain amplifier. Figure 5 shows a full analog implementation of the sigma-delta modulation module, which uses a 7-level analog sigma-delta modulator 32, and a negative feedback from the output signal Vout via the inverter 33 and the resistor RFB. provide. In the gain controller, the non-inverting input of the nose amplifier 42 is connected to a reference voltage, which in this embodiment is a grounded 'inverting input of the operational amplifier 42 and the output of the output 131141 is variable 44' The resistor 46 is connected between the operationally amplified pure inverting sigma-delta modulator 32, and the resistance of the resistor 44 and the variable resistor 46 is determined by the gain of the gain controller by changing the variable resistor 46. The value of the resistor changes the gain of the gain controller. The variable resistor 46 includes resistors 48 and 50 connected in series between the inverting input terminal of the operational amplifier 42 and the sigma-delta, the converter 32' and the transistors 52 and 54 are respectively connected in parallel to the resistor 5〇, the electric body 52 The gate is connected to the input signal vin, the gate of the transistor 54 is connected to the inverted signal of the input signal Vin from the inverter 56, and the conduction resistance of the transistors 52 and 54 is changed according to the magnitude of the input signal Vin. Assume that the resistance of the resistor 48 is R1, the resistance of the resistor 50 is the ruler 2, and the resistance of the resistor 44 is the ruler 3. When the input signal Vin is the next day, the transistors 52 and 54 are completely closed, and the variable resistor 46 is equal to the resistor. 48 series resistor 5 〇, its equivalent resistance is R1 + R2 ' so the gain of the gain controller is g = R3 / (Rl + R2) [Formula υ When the absolute value of the input signal Vin is large, the transistor 52 or 54 is fully turned on, the resistor 50 is bypassed, and the equivalent resistance of the variable resistor 46 is R1, so the gain of the gain controller is g=R3/Rl [Equation 2] When the absolute value of the input signal Vin is gradually increased from 〇 When the transistor 52 or 54 is completely turned off and gradually turned on, the resistance of the transistor 52 is Rmi, and the resistance of the transistor "11 1311400 is the equivalent value of the Rm2 'variable resistor 46 and the value is R1+(RM1// R2//RM2), so the gain of the gain controller is 'g=R3/[Rl+(RM1//R2//RM2)] [Equation 3] Figure 6 is a variation of the embodiment, the equivalent of the variable resistor 46 The resistance is determined only by the input signal Vin controlling the transistor 52. Figure 7 is another variation of the implementation of the 'inverting input of the operational amplifier 58 and the sigma delta steel transformer 32 The resistor 60 is connected. The variable resistor 62 is connected between the inverting input terminal and the output terminal of the operational amplifier S8. The resistance of the variable resistor 62 is adjusted by the input signal Vin to control the gain. When the absolute value of the input signal Vin is large. The resistance of the variable resistor 62 is also large. In the embodiment of Figures 5 through 7, the gain of the gain_controller is a continuous value. Figure 8 shows another embodiment of the gain controller 36, The plurality of amplifying 64s of the common wheel end each have different gains, and the gain of the amplifier 64 is illusory, and the multiplexer 64 is controlled by the input signal Vin from the plurality of amplifiers 64. One is selected to produce a signal to output stage 34. In a variant embodiment, as shown in Figure 9, the multiplexer is controlled by the input signal Vin to connect the signal s to one of the amplifiers 7 of the plurality of common outputs to generate a signal gS to the output stage 34. In the embodiments of Figures 8 and 9, the gain of the 'gain controller is a discrete value. 10 shows a further embodiment of the gain controller 36. The amplifier 72 amplifies or reduces the signal s to the signal stage gS to the output stage 34. The analog-to-digital converter 74 converts the input signal Vin into a digital signal, which is used in the gain table 76. Check 12 1311400 to find 'and thus determine the gain g of amplifier 72. Figure Π shows a further embodiment of the gain controller 36. The digital amplifier 78 amplifies or reduces the signal S to the output stage 34. The analog-to-digital converter 80 converts the input signal Vin into a digital signal to control the gain of the digital amplifier 78. . For comparison with the prior art, Figs. 12 through 14 show simulation results of the power amplifier 30 of Fig. 3, and Figs. 15 through 20 show simulation results without using the gain controller 36 (Fig. 1) of the present invention. As shown in Figure 12, at a small input signal of -60dB, the noise floor is below -100dB, and the underlying noise floor in the audio band (20Hz to 20kHz) is more than -120dB. The small signal, while on the full scale of the large input signal, as shown in Figure 13, the noise is still maintained at a low level, showing the good performance of the power amplifier 3 。. Figure 14 is a diagram showing the relationship between the switching frequency and the input signal size. When the rounding signal size Vin <0.5Vmax (Vmax indicates the maximum amplitude of the input signal Vin), the switching frequency is about 3 70 kHz, and the input signal size Vin is 0.7. When \^^乂 to 0.8¥11^\, the switching frequency rises to about 5501^2, and selecting the appropriate design variable can reduce the switching frequency of this range. Figure 15 shows that the conventional power amplifier 1 〇 can work normally when the input signal is small. However, when the signal is large, as shown in Figure 16, the sigma-delta modulator 12 becomes unstable. Rise to -50dB. Figure 17 shows that the sigma-delta modulator π has become unstable at the input signal size Vin > 0.7Vmax. Figures 18 through 20 show the results of increasing the switching frequency. In order to obtain a stable sigma-delta modulator 12' at the full-scale input signal, the switching frequency must be as high as 1 MHz. Because the switching frequency is increased, 13 1311400 - , power consumption and EMI will also increase. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a conventional power amplifier; FIG. 2 shows a conventional sigma-delta modulation module with hysteresis control, FIG. 3 shows a power amplifier according to the present invention; _ FIG. 4 shows gain control One embodiment of the apparatus; Figure 5 shows a sigma-delta modulation module implemented in a full analogy; Figure 6 shows an embodiment of the variation of Figure 5; Figure 7 shows another embodiment of the variation of Figure 5; - Figure 8 shows Another embodiment of the gain controller; * Figure 9 shows an embodiment of the variation of Figure 8; Figure 10 shows yet another embodiment of the gain controller; Figure 11 shows a further embodiment of the gain controller; The simulation result of the power amplifier of the invention when inputting a small signal; FIG. 13 shows the simulation result of the power amplifier of the present invention when inputting a signal at full scale; FIG. 14 is a diagram showing the relationship between the switching frequency of the power amplifier of the present invention and the input signal size; Figure 15, 4 shows the simulation results of the power amplifier with low switching frequency and small input signal; Figure 16 shows the power amplifier at low switching frequency, full scale. 14 1311400 Simulation results when entering the signal; Figure 1 shows the tracing diagram of the switching frequency of the power amplifier at the low switching frequency with respect to the input signal size; Figure 18 shows the conventional power in the tool half of the enemy at the switching frequency Simulation results when inputting a small signal; Figure 20 shows a conventional power amplification ratio versus input signal size. [Main component symbol description] Figure 19 shows the analog result when the power is amplified into the signal; and the device switches the frequency at the high switching frequency and the full-scale converter at the high switching frequency. 1 〇 Power amplifier 12 Sigma-delta Converter 13 Inverter 14 Output Stage 16 Quantizer 18 Power Stage 20 Sigma-Delta Modulation Module 22 Sigma-Delta Modulator 23 Inverter 24 Quantizer 26 Analog-to-Digital Converter 28 Retrieve Table 30 Power Amplifier 15 1311400
32 西格瑪-德爾塔調變器 33 反相器 34 輸出級 35 量化器的輸出訊號 36 增益控制器 38 放大器 40 可變增益放大器 42 運算放大器 44 電阻 46 可變電阻 48 電阻 50 電阻 52 電晶體 54 電晶體 56 反相器 58 運算放大器 60 電阻 62 可變電阻 64 放大器 66 多工器 68 多工器 70 放大器 72 放大器 74 類比數位轉換器 16 1311400 76 增益表 78 數位放大器 類比數位轉換器 8032 Sigma-delta modulator 33 inverter 34 output stage 35 quantizer output signal 36 gain controller 38 amplifier 40 variable gain amplifier 42 operational amplifier 44 resistor 46 variable resistor 48 resistor 50 resistor 52 transistor 54 Crystal 56 Inverter 58 Operational Amplifier 60 Resistor 62 Variable Resistor 64 Amplifier 66 Multiplexer 68 Multiplexer 70 Amplifier 72 Amplifier 74 Analog Digit Converter 16 1311400 76 Gain Table 78 Digital Amplifier Analog Digital Converter 80