TWI311007B - Flip-flop having improved set-up time and method used with - Google Patents

Description

1311007 %年年"Monthly Double Day Correction Replacement Page 97-11-28 IX. Description of the Invention: [Technical Field] The present invention relates to a flip-flop and a method therefor, and in particular to a A flip-flop having an improved settling time and used in it. [Prior Art] Due to the evolution of integrated circuit design and technology, the performance of the circuit is rapidly improved. A preferred example can be seen in the field of microprocessors. Only a few years ago, the personal computer microprocessor still stayed at 3 〇〇 MHz ^ clock 'now, personal electric service ϋ has been face 3_V [HZ or 1 ^ = pulse speed and pulse delay for circuit performance A block diagram of a typical delay path that would be within a digital circuit: this delay path is widely used in microprocessors and a conventional path including flip-flops (10), (10), and combinatorial logic elements: : In the flip-flop 1 103 103, D is the data input terminal, Q is the bus 枓 output ~, and ck is the receiving clock signal terminal. The positive and negative ι〇ι, (10) by (4). Figure 2 is a hybrid _ 1 operation delay clock map. 1 and Fig. 2, the flip-flop 1GI releases the data to the combinational logic unit at the first one of the clock signals, at which time the delay is at the time of the data. And L day (clock to output value) is formed by combinatorial logic unit 1 () 2 swollen into ^ / thief 101, it will pass, - _ _ * round positive and negative device 1 〇 3, and the data in the combination to avoid early The time interval of propagation in 兀102 is the propagation time interval of 2〇5, 1311007 97 years "month-to-day correction replacement page one ''97-11-28 time interval 206 has the state setting of the flip-flop 1〇3. Therefore, the delay can be regarded as the sum of the delay time interval 204, the propagation time interval 2〇5, and the set time time interval 2〇6.

Figure 3 is a block diagram of the circuit of the master-slave plastic flip-flop. The data between the data is input to the inverse gate 313 via the AND gates 311, 312, and the output nickname is controlled via the inverter 301 to control the output values of the gates 311 and 312, and the inverse 313 is coupled to the main chat. Clock (4) via inverter 3〇8, 3〇9 clock signal CK30 and pulse signal CK3 i, clock signal CK3Q and (1)i control main flip-flop MFF switch 32 322 and slave positive switch 323 , 324 to perform the signal lock and the output mutual conversion action, and the inverters 302, 303 and the inverters 304, 305 perform the flash lock of the signal, and the inverters 306, 3 〇 7 will be from the latch SFF The output signal is reversed.

Because the generation time of each signal is different, for example, non-critical data (10) pure input) money, feedback (feedbad〇_ generation time is shorter than _ sex data generation time, the conventional circuit of Figure 3 puts all the losers together - Long MFF, and then from A coffee. It will be necessary to share the same - circuit and the same - clock, and can not achieve the optimization of the clock. [Inventive content] „„The purpose of the invention It is to provide an anti-semitic with improved set-up time, using different main latches to latch key data and non-critical data, to set the timing of the pros and cons and the timing of the critical path. The re-purpose of the present invention is to provide - a method for using a flip-flop with improved settings (4), _ data and non-data can be processed separately 6 1311007 years " month kiss correction 97-11-28 to improve the set time and critical path of the flip-flop Timing. ★ The present invention proposes a flip-flop with improved settling time, package eight.

Main flash, first selector, second main question, second selector, and two; '. - the first master latch receives a critical J for _ key material; the first selector receives a plurality of non-critical heart data and selects to rotate the first selected material; the second primary flash is lightly connected to the selection Data, the second main flash is used to flash lock the ^_bee material, and one of the first input ends of the first one is coupled to the second main output of the first main selector Main flash; and from the Hi boots 1) to the second selector, wherein the second selector is connected to the ui button (four) or the first select data output 1 to select the data to the slave flash, the k-latch is used to latch and output Second choice of information. The invention also proposes that the seed is produced in a positive and negative manner with improved discrimination time. Steps: First, 'receive multiple non-key data, one, one of the non-key data is a first selection data, and a flash lock, and simultaneously receive the key data. Then, the gas selection data is the second selection data; Down and down, select the second choice data. According to the column, the key data of the flip-flops, ii:! is shorter than the time when the key data is generated. The structure and the key data of the non-key assets are selected, so the non-critical data can be processed separately without setting the time and the timing of the critical path. 7 1311007 97 The above-mentioned and other objects, features and advantages of the present invention are more apparent in the above-mentioned "month-setting correction page 97-11-28, and in conjunction with the above, the detailed description is given. 4 depicts a flip-flop=road block diagram with an improved settling time in accordance with an embodiment of the present invention. The flip-flop with improved settling time _ includes selection of main flashes 42 and 43, and 45. Control signal SEL41 controls sca^J to obtain multiple non-critical data such as non-critical data into) signal, feedback (fine (four) signal via ^ select data to ^42 will be off - one output first::: sex data Then input to the second = between. ^ every 44 - ^ generation (four) is shorter than the generation of the _f material, the selection of the master 44 is received by the main latch 42 - Feng, the signal_control selector 44 From time to time, ^^ is not related to the company's key information and rational process (4) to ^r ^ for _ data and non-data data can be; more short-lived non-critical functions to lead to the second door From the latch's and the setting of the device due to this classification, Hi. Worry processing of non-smooth data, it is beneficial to reduce the positive and negative image. Figure 5 is another embodiment of the present invention with improved settling time 8 1311 d〇c /g is a circuit block diagram. The flip-flop 5〇〇 includes a selector 5, a positive latch 52, a positive 53, a selector 54, a slave 55, and an inverter 501 to 505, 51 The data enters a first selection signal to the main latch 52 by selecting the state controlled by the signal python from the inverted state 5Π. The switch 521, the cut and the inverters 523, 524. The switch (2) controls the main 52 to receive the first selection data and then through the inverter to cut, and = two inversion mechanisms to _ this first - select the data, and then this material It is polled to the selector 54. The clock signal CK is inverted to generate the clock signal CKB, and then generated by the inverter 503, the second = m 'day _ number CKB timely pulse money cKu to control the opening When the switch 522 is turned on and off, the main flash 52 can be executed by the structure 53 and the key data is inverted by the inverter, 5〇1, and input to the main switch 531. The U has the same structure as the main question 52, and the main latch 522 The m2 and the inverters 533 and 534 are included to flash lock and output the inverted lean key to the selector 54. The selector 54 receives the first selected data of the main flash 52 and the key data of the main selection. The device 54 outputs the structure through the control of the second selection data to the slave door selection, and the ==2=5 has the same nodes as the main (four) 55 ε 51 and 552, the inverters 553 and 554, from Pick you up, "the younger brother has a long-term choice" and then received the output line through the inverter, 504 and reverse crying 505. Q and reverse rotation round out the letter B. Data screening, and then use another soil? Strict (four) a number of non-critical key information and non-key assets: choose: 唬 control another - selector will (4) select the teacher, so that non-critical data and key 1311 QiQt7f d〇c / g data The processing can be processed separately, and the processing speed can be increased. Figure 0 depicts a method for improving the set time in the embodiment of the present invention. First, in step s6〇1, a latch is received and latched. At the same time, in step 603, a plurality of non-key materials are received, and a first selection data is outputted, and then the first selection data is latched via step s6〇5, followed by step 5:: step S6〇?, Selecting the key data or the second selection data is the second selection data, which is the flash lock and the selection data in step 9. According to the present invention, the flip-flop having the improved set time and the eight-dimensional 3 ί have the structure of the two different main-sense selectors and the non-critical data, so that the key data I through different main 卩Children _ do not affect each other, so can; The set time of the positive and negative states and the timing of the critical path. Although the present invention has been implemented in a preferred manner, it is to be understood by those skilled in the art that the invention is modified and retouched after the disclosure of the scope of the invention. Figure. Figure 1 depicts the circuit block of a typical delay path in a digital circuit. Figure 2 depicts an illustration! The operation of the circuit block =3 depicts the circuit block diagram of the conventional master-slave type flip-flop... The positive and negative of the embodiment of the present embodiment of the present invention is a circuit block diagram of a flip-flop having an improved settling time according to another embodiment of the present invention. . Figure 6 depicts a method for use with a flip-flop having improved set times in accordance with an embodiment of the present invention. [Main component symbol description] 101, 103, 400, 500: flip-flop 102: combination logic unit 204 to 206: time interval • 311, 312: and gate 313: reverse gates 41, 44, 51, 54: selector MFF, 42, 43, 52, 53: main question SFF, 45, 55: from flash 321 ~ 324, 521, 522, 531, 532, 551, 552: switches 301 ~ 309, 501 ~ 505, 511, 523, 524 533, 534, 553, 554: Inverter • CK30, CK3 Bu CK, CKB, CK1: Clock signal SEU, SEL2, SEL41, SEL44: Select signal Q1: Output signal QB1: Inverted output signal D: Data input Terminal, Q: data output terminal, CK: receiving clock signal terminal 1311007 clock signal

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Claims (1)

1311 Qi0t7f d〇c/g X. Patent application scope: 1. A flip-flop with improved set-up time, comprising: ^ a master-latch, receiving a critical (criticai) material, the first master The latch is used to latch the key data; - a first selector, receiving a plurality of non-critical data, the first selector outputting one of the plurality of non-critical data as a first selected data; a primary latch coupled to the first selector, the second primary latch for latching the first selection data; a second selector coupled to the first primary latch and the brother a second flash; and a slave latch coupled to the second selector, wherein the second selector is configured to select the key data and the first selected data to output a second selected data to the slave latch The slave latch is used to latch and output the second selection material. ~ 2. The method of claim 1, wherein the first main latch comprises a first switch, a second switch, a first reverse steal, and a second reverse phase. The first switch is configured to control the input of the key data, and the first inverter is coupled to the second inverter through the second switch to latch and rotate the key data. 3. As claimed in the first paragraph of the patent application, there is a positive and negative reaction to improve the set time, and the </ br> master has the same configuration as the first main latch. 4 'As claimed in claim 1 of the invention having the improved set time, the slave latch has the same configuration as the first master latch. 1311 〇〇9wf.d〇c/g 5. For the flip-flop with improved set time in item 1 of the application scope, each of the non-critical materials is generated for a shorter period of time than the time at which the critical information is generated. 6. A method for use with a flip-flop having an improved settling time, comprising the steps of: receiving a plurality of non-critical materials, and selecting one of the non-critical materials as a first selection material, and latching Locking the first selection data while receiving and latching a critical data; selecting the key material or the first selection data as a second selection data; and latching and outputting the second selection data. 7. The method of claim 6 for use in a flip-flop having an improved set time, wherein each of the non-critical materials is generated less than the time at which the key material was generated.