TWI310233B - Trap memory with a modified drain/source voltage and the method for making the same - Google Patents

Description

Ι3Ί0233 IX. Description of the Invention: [Technical Field] The present invention relates to a trapable memory (Trap Mem〇ry) and a method of fabricating the same, and more particularly to a novel energy trapping source for a modulated source/drain voltage and Its manufacturing method. [Prior Art] The Xixia_Oxide_Nitrate_Oxide/Substrate (SONOS) memory structure derived from flash memory (FLASH) and electronic erasing read-only memory (EEPROM) technology, the earliest According to Dr. Shi Min and others, the semiconductor industry and academic circles in the United States, Europe, Taiwan, Japan, and South Korea have extensively studied and discussed, but such S0N0S still has many shortcomings, such as the multi-layer architecture built on closed extremes. Large voltage to guide the channel layer underneath; the stored charge is easily dissipated, for a storage medium without a multi-layer structure, especially without insulation, the charge (4) is dissipated; in addition, the storage mechanism is built below the level The structure of the oxide, the oxide and the oxide ((10) 〇) is used to improve the high-operational components. In the fabrication, it is easy to produce the disadvantage that the upper and lower layers cannot be properly aligned due to the use of multiple masks. Storage, 'Ό' is a limitation that can cause the component to continue to shrink (depending on the length of the channel). The length of the structure = in: the (four) N〇s component of the bit, in addition to the higher operation = Bu: if there is no effective isolation in the remaining interval of the two charges, the stored density-free region of the south of the charge will be diffused to a low The difficulty of density, Mang I』 & 成 疋 疋 疋 疋 疋 疋 疋 疋 , 疋 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 11 11 11 11 A large voltage is consumed to guide the channel layer underneath, even if a large voltage operation is required in the read mode, a small amount of impact ionization is generated, which affects component reliability and storage effective time; Finally, for the horizontal ΟΝΟ structure, the charge distribution is too scattered, and it is impossible to induce a strong electric field to make a large change to the threshold voltage, making it difficult to interpret. Paper [Wen-Jer Tsai, Chih-Chieh Yeh, Nian-Kai Zous, Chen-Chin Liu, Shih-Keng Cho, Tahui Wang, Samuel C. Pan, Chih-Yuan Lu, "Positive Oxide Charge-Enhanced Read Disturb in a Localized Trapping Storage Flash Memory Cell" in IEEE TRANSACTIONS ON ELELCTRON DEVICES, VOL. 51, NO. 3, MARCH 20 04] reveals a SONOS component that uses a horizontal ΟΝΟ structure to the bottom of the gate. When the horizontal structure is long enough, The high-voltage writing operation of the source or the drain causes the area of the electron collision free phenomenon to be different, and the electrons that have entered the storage area after passing through the gate oxide layer are localized, but the structure has the above自我 Self-alignment features that are completely compatible with the channel. However, when the component is miniaturized, the localization phenomenon will gradually disappear, the bit interpretation window is compressed, and the double-bit function is lost. In addition, because the gate structure is used in the gate, The write or erase operation voltage is too high and may not meet the electrical requirements of the mainstream integrated circuit. Papers [Rossella Ranica, Alexandre Villaret, Pascale Mazoyer, Stephane Monfray, Daniel Chanemougame, Pascal Masson, Arnaud Regnier, Cyrille N. Dray, Roberto Bez, and Thomas Skotnicki, "A New 40-nm SONOS Structure Based on Backside Trapping for Nano -scale Memories"] reveals a 111758.doc 1310233 s〇N〇s element that makes the horizontal structure below the extreme. This structure effectively improves the component structure mentioned in the previous paper in terms of operating voltage, due to the upper gate It is not the use of a multi-layer structure to write or erase the operation of the electric house will not pass, but as mentioned in the previous paper, when the horizontal structure is long enough, the high voltage writing operation at the source or the bungee will lead to electronics. The area generated by the collision free phenomenon is different, and the electrons that have penetrated into the storage area after the upper oxide layer of the lower layer are localized. However, when the components are miniaturized, the localization phenomenon may be due to the absence of effective isolation. Or interfere with _, the bit interpretation window is (four), the function of the double bit is lost n. After the structure is completed, the structure is to be constructed. The gate has self-alignment problems. If the gate cannot be placed in the center of the horizontal 〇Ν〇 structure, it will make the localization phenomenon asymmetrical when writing from the source and the drain. The bit interpretation window is compressed 'when' is not overwritten for a long time, it will spread to the other end due to the charge, so it is not easy to completely erase (under-erase) when doing single-ended erasure. Paper [Laurent Bqreuil, Luc Haspeslagh, Pieter Blomme

Dirk Wellekens, Joeri De Vos, Martino Lorenzini, and Jan Van Houdt, "A New scalable Self-Aligned Dual-Bit Split-Gate Charge-Trapping Memory Device" in IEEE

TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO 1 0, OCTOBER 2005.] Reveals a SONOS component that uses a horizontal 〇NO structure below the gate terminal. 'This structure uses isolation technology' to ensure that the charge stored in different regions is not concentrated. Diffusion or inter-bit interference due to electric field crossover, so that the length of the gate coincides with the length of the channel, that is, control 111758.doc 1310233 The end of the gate and the end of the source/drain definition area are just aligned, A ^ 4 a community to make ° stand on both sides of the gate, the storage area of each bit, it is necessary to use another layer of mask definition, which will result in different storage areas of two bits, even in the gate When the controller is further reduced, there may be a slight deviation of the mask, so that the storage area of a certain bit completely disappears. In addition, the length of the idle pole is the characteristic length, which is bound to make the structure more limited when miniaturized. However, this structure still has to use a multi-layer structure, which will make the writing or erasing operation voltage too high 'may not meet the electrical requirements of the mainstream integrated circuit. Paper [HWan Ch0, Tai-su Parki, Si Y〇ung Choi, J〇ng Duk

Lee, and Jong-Ho Lee'"Body-Tied Double-Gate SONOS Flash (Omega Flash) Memory Device Built 〇n Bulk Si Wafer", in Semiconductor R&D Center, Samsung

Electronics Co., Ltd. wants to use bilateral gates and even multilateral gates to increase the drive current and enhance the high-speed collision dissociation effect in the depletion zone at the end of the channel. This is a good idea, but it is necessary to form a bilateral gate or even a multilateral gate. Extremely 'or other more complex gate structures, self-alignment between the gates of different faces'. This problem is more serious after the components are miniature, and the relative geometrical positions of the gates of different faces are often not precisely determined by the designer. This is achieved because the reticle cannot be absolutely accurate due to the alignment of the small scale, which will cause unnecessary heating effects, and even different threshold voltages in different SONOS components in the same wafer will greatly reduce the The value of creativity 'this is the self-alignment problem that will be encountered in the SONOS attempt of bilateral gates and even multilateral gates. Paper [Rob van Schaijk, Michiel van Duuren, Pierre 111758.doc .10· 1310233

Goarin, Wan Yuet Mei, Kees van der Jeugd, "Reliability of embedded SONOS memories", in IEEE 2004.] reveals a SONOS component that forms a storage region under the gate, which is the off-shape of the SONOS component. The problem, whether it is the gate-to-channel, or the gate pair, is the storage structure of the storage area, but this component can only be used as a one-dimensional memory.

U.S. Patent Publication No. 2006/0,068,546 discloses a SONOS component that can be completely isolated per bit, by first stacking 0Ν0, and then dug a well with a mask definition to make electron energy on both sides of the well. The trap, in turn, the gate oxide layer and the gate deuteration layer fill the well horizontally, so that each bit can be completely isolated, but a well is dug out by a mask definition to separate In the case of two bit storage areas, the size of the storage area will be uneven. 'This will be more serious when the component is miniature, and even when the mask is too large, it will cause a certain bit storage area to completely disappear. In addition, If the level is emphasized during the filling process, it will increase the difficulty of the process. In addition, after the completion of the electron energy trapping area, the well will form a three-to-three (four). If there is a small amount of contact with the free electricity, move to the lower tip of the well. Discharge, the accumulation of this unexpected electricity may change the critical charge of the charge in the charge storage area on both sides.

Influential, in addition, the length of the gate of the Me A is the characteristic length, which is bound to make the structure more restricted in the =, and the structure still has to use multiple layers of junctions to cause writing or erasing operations. If the voltage is too high, it may not meet the electrical requirements of the mainstream integrated circuit. Inch. Micro-US Patent Publication No. 2〇〇4/〇, 2〇7,__ also reveals the functional FLASH component, self-pairing, and horse-soap one 7L FLASH component, 111758.doc 1310233 but with self The effect of alignment 'only this architecture can not complete the more complex structure in the same number of reticle use, to achieve multi-bit storage, and improve the efficiency and the efficiency of the bit accumulation. U.S. Patent Publication No. 2002/0,004,291 discloses a SONOS component that can be completely isolated per bit, similar to U.S. Patent Publication No. 2006/M6M46, which differs in that it first forms a gate with a photomask and then uses a gate field to make light. The cover is cut and separated so that each bit can be completely isolated.

The SONOS component 'the beginning of the mask to form the μ pole must ensure that it can be placed in the remote structure. Otherwise, if the next two bit storage areas are to be formed, the storage area will be unevenly sized. It is serious, even if the reticle offset is too large, it will cause the _ _ storage area to completely disappear. The 'other' gate length is the characteristic length', which is bound to make the structure more restricted when miniaturized. The & structure still has to use a multi-layer structure, which will make the write or erase operation voltage too high, and may not meet the electrical requirements of the mainstream integrated circuit. U.S. Patent Publication No. 2/5/1,6,793 is also a single-bit FLASH component. This structure is substantially the same as the conventional FLASH component, and the gate oxide layer, FLA_, upper blocking oxide layer, The control layer is stacked once and finished. 'With the mask definition (4), although there is a good self-aligning effect, this architecture cannot be used in a relatively complicated structure in the same number of masks to achieve multiple positions. Meta-storage, while improving performance, the effect of bit-integration. Refer to the Republic of China Patent Bulletin No. 237349 and the Republic of China Patent Bulletin No. 239073, both of which are s*N〇s components of the two-dimensional, all of which are of the three-layer structure of horizontal H1758.doc -12· 1310233 and effective Isolation 'This is a component with a horizontal storage mechanism set on the closed-pole T side. There are still two-dimensional storage area lengths that are uneven when the mask is defined, the operating voltage is too large' and the component shrinkage is limited.

❿ US Patent Publication No. 285/177, which also forms a storage area SONGS element under the gate, but when the middle channel material is used to separate the two bit storage areas, 'the storage area size will be uneven. This will increase the severity of the component when it is miniature. Even when the mask is too large, it will cause the loss of a certain bit storage area. The use of a photomask in the gate will result in alignment problems. There is a problem when the bit storage area is being miniaturized. U.S. Patent Publication No. 2_/M23,513, is to make a big question, and excavate the well at the gate, using the sidewall residue to leave two bit-storage areas' to reuse the sedimentation above the well end. Automatically aligning the gate, this concept is excellent in alignment, but the multi-layer gate still consumes a large voltage, and the gate is extremely characteristic length. During the miniaturization process, the two elements are gradually approaching, which will compress the possibility of miniaturization. . US Patent Publication No. 2005/0,255,657 discloses the use of a continuous deposition of three or more layers of structure, which is defined by a reticle, leaving a sidewall during etching, but if the reticle fails to etch away the layered structure above the bump, The effectiveness of this component is reduced by leaving the multilayer structure that the sidewall wants to leave. U.S. Patent Publication No. 2005/0,242,391, the entire disclosure of which is incorporated herein by reference in its entirety, the disclosure of the entire disclosure of the entire disclosure of the disclosure of the entire disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of The component 'this is a single-bit SONOS, which is not scalable. In addition, as mentioned earlier, 'multilayer gates still require a large operating voltage. 111758.doc •13· 1310233 From the above example, we can find that 'in different papers and patents, there are needles: the inventor’s initial development of the problem of developing 8 〇 deleting components and problems, such as built in The multi-layer architecture of the gate terminal consumes a large voltage; the stored charge is easily dissipated. 'For a storage medium without a multilayer structure or without an insulating body, the charge is easily dissipated; for a horizontal crucible structure in which the storage mechanism is built below The fabrication of components that improve high operating voltages requires the use of multiple masks. 'The upper and lower layers will not be properly aligned during miniaturization; the horizontal storage structure also limits the component shrinkage (and therefore the horizontal structure length and channel length); The other two s〇N〇s components have no effective isolation in the two charge storage intervals, which will cause the stored charge to spread and cause the bit reading window to be reduced. If it is to be isolated, it cannot be self-aligned. The steps are also complicated; finally, for the horizontal coffee structure, the charge distribution is dispersed, and the synthetic electric field may not change the threshold voltage. Or to study the concept of double bit Save. Therefore, it is necessary to provide an innovative and progressive modulation source/bungee voltage capable memory and its manufacturing method to solve the above problems. SUMMARY OF THE INVENTION The main object (4) of the present invention provides a method for manufacturing a modulated source/drain electrode, which comprises the following steps: (a) providing a substrate having a surface; (b) Forming a recess on the surface of the substrate, the recess having two sidewalls and a bottom; (c) forming an electron storage layer on the surface of the substrate and the recess; (d) partially removing the An electron storage layer to form two discontinuous electron energy 111758.doc -14-1310233 traps (or electron storage layers), and exposing the surface of the substrate and the bottom of the recess, the electron trapping regions Each of the two sidewalls of the recess is disposed on the sidewall of the recess, and the electron trapping region has a pitch; (e) forming a conductive layer on the surface of the substrate, the electron trapping region, and the bottom of the recess 'I has a _ gate region on the upper surface of the conductive layer; (f) a gate oxide layer is formed on the conductive layer; (g) a gate bismuth layer is formed on the gate oxide layer; (h) Removing the gate layer to leave a relative position in the recessed region; (1) growing the residual 矽' to form a gate, wherein the gate has a horizontal width smaller than the spacing of the electron energy trapping regions; (J) forming a gate protective layer on the gate and the gate oxide layer And (9) forming a source and a drain electrode, wherein the source and the drain are located inside the conductive layer relative to the electron trap. ▲ Another object of the present invention is to provide a modulated source/drain voltage capable recessed body comprising a substrate, two discontinuous electron energy trapping regions, conductive: two-gate oxide layer, one gate, one Source and a bungee. The substrate has a groove-shaped groove having two sidewalls and a bottom portion, and the sidewalls are used for storing electrons in the electron energy trapping region, and are respectively located on the sidewall of the groove. Can trap the interval with - spacing. The conductive layer is located on the surface of the substrate, the electron energy trapping region, and the surface of the recess. The layer is on the conductive layer. The idle pole is located on the interpole oxide layer, and the horizontal width of the gate is less than the spacing of the electron depression regions relative to the gate recessed region. The source and the drain are located on the conductive layer, and are respectively located on two sides of the gate, and the source and the drain are located inside the isoelectric b-zone. In the present invention, the channels of the electron energy trapping region and the upper layer and the gate electrode can produce a complete self-alignment effect. In addition, the separate vertical electron trap structure will not limit the miniaturization of the channel length, and it does not consume a large gate voltage because it is not a multi-layer structure built at the gate terminal. In operation, due to the small operating voltage, it has a strong inhibitory effect on the extra electrical effects caused by the high electric field. Moreover, since the separated vertical electron energy trap structure has the gate oxide layer and the conductive layer effectively isolated from each other, there is no bit interference between the bits, and the excellent resistance is not caused by the charge distribution concentration. The resulting diffusion phenomenon and the difficulty of interpretation or even the wrong situation of It. The vertical architecture of the present invention has a tip charge accumulation at the upper end, which generates a stronger electric field to modulate the subcritical region (sub thresh〇ld, _ the voltage acting on the source 7 drain, forming a larger interpretation between the bits In addition, the present invention utilizes a symmetric vertical electron storage region (i.e., such electron trapping regions) formed outside the source and the drain, the electron storage region being generated by the held electrons. The synthetic electric field demodulation is truly used in the source and the infinite electric field to produce readability. The electron storage area is far away from the collision ionization area, so that interference during reading can be prevented, and it is a reliable memory element. [Embodiment] Referring to FIG. 1 to FIG. 1, a schematic diagram showing a method of manufacturing a 111758.doc 16 1310233 memory of a modulated source/drain voltage according to the present invention is shown. Referring first to FIG. 1, a board 1 is provided. The substrate 1 has a surface 11. In the embodiment, the substrate 1 is a Silicon-On-Insulator (SOI) substrate, which includes a first wafer 12, an oxide layer 13, and a second Wafer 14, the oxide layer = system The substrate 1 is also sandwiched between the first wafer 12 and the second wafer 14. It is understood that the substrate 1 may also be a single wafer. Referring to FIG. 2, the surface 11 of the substrate 1 is formed. - groove 15, the concave

The slot 15 has two side walls 151 and a bottom 152. In this embodiment, after the completion of the standard cleaning step and after the completion of the mask process, the LOCOS (STI) mating-mask defines the recess (4), and the second wafer 14 is etched by the active ions to form The groove 15. The groove 15 is an element active area. It should be noted that, in the present invention, the depth and shape of the groove 15 are not particularly limited, and the side walls 151 may be perpendicular to the bottom Μ or may have an inclination angle greater than or equal to 9 间 between the bottom 152. And the side walls 151 may also be curved. Referring to FIG. 3, an electron storage layer 16 is formed on the surface 11 of the substrate 1 and the recess 15. In the present embodiment, the material of the electron storage layer 16 is nitride. In the present embodiment, the electron storage layer 16 is formed by low pressure chemical vapor deposition (LPCVD). Referring to FIG. 4, the electronic storage layer 16 is partially removed to form two discontinuous electron energy trap regions 17, and the surface U of the substrate 1 and the "bottom σ" 52 ' of the recess 15 are exposed. The electron energy trapping zone 17 is a side 俾 _ s and a permeable layer 4 layer (Spaeer) which are left by the side wall residual technology, and are respectively located on the side soil 1 51 of the four slots 15 5 , and the The isoelectronic energy trap has a distance of 17 between them. 111758.doc 17 1310233 In the present embodiment, the electronic storage layer 16 is engraved with active ions, and the formed electron energy (4) 17 has a thickness of uniform, which is perpendicular to the sidewalls 151. The bottom 152 of the slot 15. Referring to FIG. 5, a conductive layer 18 is formed on the surface of the substrate 1, the electron trapping regions 17 and the bottom portion (5) of the recess 15. The conductive layer has a "closed-pole recessed region 181' on the surface, and the closed-pole recessed region (8) is located at the opposite of the electron energy. In the present embodiment, the material of the conductive layer 18 is polycrystalline, and the conductive layer is formed by low-pressure chemical vapor deposition, and then the upper surface of the electrical layer is subjected to multiple growth and etching. A gate recessed region 18 is formed which is relatively rounded. Referring to FIG. 6, a gate oxide layer 19 is formed on the conductive layer 18. Referring to FIG. 7, a gate-deuterated layer 2 is formed on the gate oxide layer 19. In the present embodiment, the material f of the gate electrode layer 2G is polycrystalline, and the gate vaporization layer 2 is formed by a low pressure chemical vapor deposition method. Referring to Fig. 8, the gate hardened layer 2 is removed by enthalpy to remove the remaining layer 〇2. In the embodiment of the present invention, the gate electrode layer 20 is engraved with active ions. The residual crucible 201 is located at a relative position of the gate recess region 181. Referring to Fig. 9, the residual stone eve 201 is grown to form a closed (four). The horizontal width of the closed pole 21 is less than the spacing between the electron trapping regions 17. In the present embodiment, the residual crystal growth method is used to grow the residual stone. Since the residual Shixi 201 is located at the relative position of the pole depression region i8i, the gate 21 has a self-aligning effect during the growth process, that is, the gate 21 is located in the electron energy trapped region after being grown. In the middle of it. 111758.doc 1310233 Referring to Figure 10, a gate protection layer 22 is formed over the gate 21 and the gate oxide layer 19. In the present embodiment, the gate protection layer 22 is also an oxide layer' having the same material as the gate oxide layer 19. Next, a source electrode 23 and a drain electrode 24 are formed on the conductive layer 18 by using an ion implantation technique, and the source electrode 23 and the drain electrode 24 are located in the conductive layer 18 opposite to the electron energy trap region 7 Inside.

Referring to FIG. 11, if necessary, the gate protection layer 22 and a portion of the gate oxide layer 19 are removed to expose the gate 21, the source 23, and the drain 24 to form a modulation source/汲The voltage of the pole can be trapped in the memory 2. Referring again to Fig. 11, a schematic diagram of the energy storage source of the modulated source/drain voltage of the present invention is shown. The energy storage source 2 of the modulation source/drain voltage includes a substrate 1 with a discontinuous electron energy trapping region I7, a conductive layer 18, a gate oxide layer 19, a gate 21, and a source 23; One bungee 24. The substrate 1 has a recess 15 having two side walls ΐ5ΐ and a bottom portion (1) which are symmetrical in shape. In the present embodiment, the substrate i is a germanium-covered insulating substrate, and the cladding layer 13 and the second wafer (4) are between the oxide (4) and the second wafer 14 . It can be understood that the substrate i can also be a single wafer. The electron trapping regions 17 are respectively located on the side wall 151 of the swell groove 15 and are used for storing electrons. The electron energy 妒p1 μ has a spacing. In the present embodiment, the electron trapping regions [7 are made of nitride having a uniform thickness] and perpendicular to the bottom 152 of the recess 15. The conductive layer 18 is located on the surface 11 of the substrate 1 , the electron energy trap 111758.doc -19· 1310233 * region 17 and the bottom portion 152 of the recess 15. The upper surface of the conductive layer i8 has A gate recessed area 181. The gate oxide layer 19 is located on the conductive layer U•. The 5th gate 21 is located on the gate oxide layer 19, and the horizontal width of the gate 21 is smaller than the pitch between the electron trap regions 17 with respect to the gate. In this embodiment, the conductive layer 18 and the gate 21 are made of polysilicon. The source 23 and the drain 24 are located on the conductive layer 18 and are respectively located on two sides of the gate 21, and the source 23 and the drain 24 are located on the inner side of the electron recessed area 17 . Referring again to FIG. 10, in other applications, the gate oxide layer 19 extends over the conductive layer 18, that is, over the source 23 and the drain 24. In addition, the gate 21 further includes a gate protection layer 22 for protecting the gate 2. In the present invention, the electron trapping region 17 and the upper channel and the gate 21 can be completely self-aligned. The effect. In addition, the separation of vertical electrons and the structure of the trap 17 will not limit the miniaturization of the channel length, and • because the multi-layer structure is not built at the gate extreme, it does not need to consume a large gate voltage. Moreover, due to the small operating voltage, the additional electrical effect due to the high electric field has a strong inhibitory effect. Moreover, since the separated electrons have the gate oxide layer 19 and the structure between the trapped electrons, The conductive layer 18 is effectively isolated, and there is no interference between the bits, and the diffusion phenomenon caused by the uneven distribution of the charge distribution is excellent, and the interpretation is difficult or even wrong. The vertical structure of the present invention is The upper end has a tip 〃% accumulation will generate a strong electric field to modulate the source/drain voltage of the element operating in the subcritical region (eSh〇ld reglon), which constitutes a larger interpretation between the bits than the 111758.doc 20-1310233 In addition, the present invention utilizes a symmetric vertical electron storage region (ie, the electron energy trap region 17) formed outside the source electrode 23 and the drain electrode 24, and the electron storage region is generated according to the held electrons. The synthetic electric field demodulation truly uses the electric field of the source 23 and the drain 24 to produce readability. The electronic storage area is far away from the collision ionization area, so that the interference during reading can be prevented, which is a reliable The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention, and those skilled in the art can make modifications and variations to the above-described embodiments without departing from the spirit of the invention. The range should be as listed in the scope of the printed patents described later. [Simplified Schematic] FIG. 1 to FIG. 11 are schematic diagrams showing a method of manufacturing a memory capable of modulating a source/no-pole voltage according to the present invention. 】 1 substrate 2 modulation source / drain voltage can be trapped in memory 11 substrate surface 12 first wafer 13 oxide layer 14 second wafer 15 groove 16 electron storage layer 17 electron energy trapping area 111758.doc 21 1310233 18 Conductive layer 19 Gate oxide layer 20 Gate Shi Xihua Zhan 21 Gate 22 Gate protection layer 23 Source 24 ί and pole 151 Groove sidewall 152 Groove bottom 181 Gate recessed area 20 1 residual 矽

111758.doc -22

Claims (1)

1310233 Patent application scope: - A method for manufacturing a memory capable of modulating a source/drain voltage comprises: (a) providing a substrate having a surface; (b) forming a surface on the surface of the substrate The groove has a groove, and the groove has two sides of soil and a bottom.卩, the sidewalls are symmetrically shaped; forming an electron storage layer on the surface of the substrate and the recess; (4) erroneously removing the electron storage layer (4) into: an electron (n) that is not (d) and exposed The surface of the substrate and the bottom b of the recess and the electron-trapping region are respectively located on two sidewalls of the recess, and the electron trapping regions have a spacing; (4) forming a conductive layer on the substrate The surface, the electron energy trapping region and the bottom portion of the recess have a gate recessed surface on the upper surface of the conductive layer; (〇 forms a gate oxide layer on the conductive layer; (g) forms a gate deuterated layer on the gate oxide layer; (h) partially removing the gate deuterated layer to leave a residual position in the gate recessed region; (i) growing the residual crucible to form a gate, wherein a horizontal width of the gate is less than the spacing of the electron energy trapping regions; (j) forming a gate protection layer on the gate and the gate oxide layer; and (k) forming a gate a source and a drain, wherein the source and the drain are located in the conductive layer relative to the first 2. The manufacturing method of claim 1, wherein the substrate is a substrate insulation 111758.doc 1310233 (Silic〇n_〇n_Insulat〇r, s〇i) substrate, including - a wafer, an oxide layer and a second wafer 'the oxide layer is interposed between the first wafer and the second wafer. 3. The method for manufacturing the substrate, wherein the substrate is A wafer. The manufacturing method of claim i, wherein the step (b) defines the groove by a mask and the substrate is etched with active ions to form the groove. The manufacturing method of the crucible, wherein the sidewall of the recess is perpendicular to the bottom of the recess, and the electron trapping region is perpendicular to the bottom of the recess. 6. The manufacturing method of claim 1, wherein the step (C) The formation methods in (e), (1), (§), and (J) are low pressure chemical vapor deposition (LPCVD). 7. The manufacturing method of claim 1, wherein the steps (4) and (h) The removal method is reactive ion etching. 8. The manufacturing method of claim 1 is the selective epitaxial growth method 9, such as the manufacturing method of claim 1, wherein the growth method in the step (1) is that the material of the electron storage layer is 1〇: The manufacturing method of claim i, wherein the conductive layer and the gate deuterated layer are polycrystalline. 11 The method of claim 1, wherein the step (k) is to form the source and the drain by ion implantation. Except for: the manufacturing method of item 1, wherein the step (k) further comprises the step of shifting the three-pole protective layer and a portion of the gate oxide layer. - a variable source/drain voltage capable memory, comprising: Hl758.do, 1310233 a substrate having a recess, the recessed two discontinuous electron energy trapping regions on the sidewall of the recess The slot has two side walls and a bottom portion for storing electrons, and each of the electron energy trapping sections has a spacing; a conductive layer is located on the surface of the substrate, and the bottom of the recess is on the conductive layer The electron energy trapping region and the mask have a gate depression and a gate oxide layer between the electron recessed regions of the gate recess, and a gate on the conductive layer is located at the gate oxide a layer, a region, the horizontal width of the gate is less than the equidistance; and a source and H are located on the conductive layer and are respectively located on two sides of the question pole. The source and the pole are located opposite to each other The inside of the electron energy trap. 14. 15. 16. 17. 18. The memory of claim 13, wherein the substrate is a "7-covered insulating substrate" comprising - a wafer, an oxide layer and a second wafer, the oxidation The layer is disposed between the first wafer and the second wafer. The memory of claim 13, wherein the substrate is a wafer. The memory of claim 13, wherein the recess θ < the sidewall is perpendicular to the bottom of the recess and the dielectric layer is perpendicular to the bottom of the recess. The memory of claim 13, wherein the conductive power conservation is related to the material of the gate is polysilicon. The memory located in the gate of claim 13 further includes a gate protection layer. H1758.doc