1309437 九、發明說明： 【發明所屬之技術領域】 本發明大體上係關於積體電路之製造，更明確言之，係 關於遮罩技術。 【先前技術】 為了滿足現代電子工業在可攜性、計算能力、記憶體容 量及能源效率的需求’積體電路不斷地愈做愈小。因此， 積體電路組成特徵（例如電子裝置及互連線寬）之尺寸也不 斷地縮小。特徵尺寸縮小的趨勢在例如動態隨機存取記憶 體（"dram")、快閃記憶體、非揮發性記憶體、靜態隨機 存取S己憶體（"SRAM”）、鐵電（"FE”）記憶體、邏輯閘陣列等 的記憶體電路或裝置中非常明顯。 例如，DRAM通常包含數以百萬計之完全相同的電路元 件’稱為s己憶體單元。就最一般性的形式而言，一記憶體 單凡通常由二個電子裝置組成：一儲存電容器及一存取場 效電晶體。每一記憶體單元為一個可定址的位置，其能夠 儲存一二進位元（"位元";^可透過電晶體將一位元寫到一 單元中，以及利用從參考電極感測儲存電極上的電荷來讀 取位疋。藉由縮小組成電子裝置及存取它們的導線的尺 寸，可縮小包括這些特徵的記憶體裝置的尺寸。因此，可 裝入更多的記憶體單元到記憶體裝置中，來提高儲存容 量 0 另-個例子是快閃記憶體(例如，電子可抹除可程式化 唯讀記憶體或”EEPRQM”），這種型式的記憶體—般而言是 109141.doc 1309437 每次以區塊為單位，而不是以一個字組為單位，來抹除及 重新牙王式化。典型的快閃記憶體包含一記憶體陣列，其包 含大量的記憶體單元。該等記憶體單元包括一能夠容納一 電荷的浮閘場效電晶體一單元中的資料取決於浮閘中是 否有電荷。該等單元通常被分組成所謂的”抹除區塊”的區 段中。-快閃記憶體陣列的記憶體單元一般而言係配置至 一”nor”架構（每-單元直接耗合至—位元線）或一 "NAND" 架構（若干單元耗合至若干單元的”字串"中’使每一單元間 接輕合至-位元線，且存取時必須啟動字串的其它單元） 中:藉由將浮閘充電，可以用隨機的方式對一抹除區塊中 的早兀丁電力上的程式化。可利用一區塊抹除操作把浮 閘的電荷消除，其中，技& 〇„ 抹除區塊内全部的浮閘記憶體係在 一早一的操作中抹除。 圖案間距係定義為’兩個相鄰的圖案特徵中，—完全相 同的點之間的距離。這此特徵一 俨式K &而d糸由一例如一絕緣 體或導體的材料中的開口所定義 區隔開來。因此，可以把間距理解為：把它們互相 > + 理解為，一特徵的寬度加上 該特徵與一相鄰特徵分開的寬度的和。1309437 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to the manufacture of integrated circuits, and more particularly to masking techniques. [Prior Art] In order to meet the needs of the modern electronics industry in terms of portability, computing power, memory capacity and energy efficiency, the integrated circuits are steadily getting smaller and smaller. Therefore, the size of the integrated circuit components (e.g., electronic device and interconnect line width) is continuously reduced. The trend of feature size reduction is, for example, dynamic random access memory ("dram"), flash memory, non-volatile memory, static random access S memory ("SRAM"), ferroelectric (" ;FE") memory circuits, logic gate arrays, etc. are very obvious in memory circuits or devices. For example, DRAMs typically contain millions of identical circuit elements, referred to as s-resonance units. In the most general form, a memory is typically composed of two electronic devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that is capable of storing a binary bit ("bit";^ can write a bit into a cell through the transistor and utilize sensing from the reference electrode to store The charge on the electrode is used to read the position. By reducing the size of the wires that make up the electronic device and accessing them, the size of the memory device including these features can be reduced. Therefore, more memory cells can be loaded into the memory. In the device, to increase the storage capacity. Another example is flash memory (for example, electronic erasable programmable read-only memory or "EEPRQM"). This type of memory is generally 109141. .doc 1309437 Erasing and re-mating each time in blocks rather than in a block. A typical flash memory contains a memory array that contains a large number of memory cells. The memory cell includes a floating field effect transistor capable of accommodating a charge. The data in a cell depends on whether there is charge in the floating gate. The cells are usually grouped into sections called so-called "erase blocks". - The memory cells of a flash memory array are typically configured to a "nor" architecture (each unit directly consumes to - bit line) or a "NAND" architecture (several units are lumped to several units) "string" in "make each unit indirectly light to the - bit line, and must start other elements of the string when accessing": by charging the floating gate, you can erase it in a random way Stylization of the early power in the block. A block erase operation can be used to eliminate the charge of the floating gate, wherein the technology & 〇 „ erase all the floating memory systems in the block in the morning one Wipe in operation. The pattern spacing is defined as the distance between two identical pattern features, the exact same point. This feature is a K K & and d糸 is an insulator or conductor The zones defined by the openings in the material are spaced apart. Therefore, the spacing can be understood as: inter-> + is understood to mean the width of a feature plus the sum of the widths of the feature and an adjacent feature.
【發明内容J —在本發明之-具时施财，提供—種在—積體 疋義圖案的方法，該方法 丞扳之一第一區域卜， 使用微影蝕刻於—第一光 一 M u山 曰中疋義稷數個特徵。在 低遮罩層中，使用間距增值法 車又 光阻層中的每一個特护令洋 生至 >、二個特徵。該較低遮声 ' s中的特欲包含迴圈端點。 10914l.doc 1309437 :::光阻層覆蓋一基板的第二區域，其包括 :::::。在該基板中導溝渠圖案穿過該較低遮: ;度的―刻於第二區域内。該等溝渠具有—溝渠 隹本發明之另一具 ά m w\ κ内 裡任~陳列Φ你· =複數條導線的方法，該方法包括提供—臈堆叠。該膜堆 疊包括-與複數個導電插頭接觸的基板、一覆蓋料導 番頭的絕緣膜、一覆蓋該絕緣膜的較低遮罩層及一形成於 =交：遮罩層之上的間隔物陣列…犧牲膜係沉積於較低 遮罩層及間隔物之陣列之上。於犧牲膜之—部分上形成二 次要遮罩。該次要遮罩在該間隔物陣列中定義—開口。可 選擇性地相對於該次要遮罩#刻該較低遮翠層及該犧牲 膜。該犧牲膜被敍刻而使該較低遮罩層 < 一部分曝露。該 =法進一步包括蝕刻該較低遮罩層及曝露該絕緣膜之—部 分。於該絕緣膜、該較低遮罩層及該犧牲膜之中㈣複數 個溝渠’以曝露該等導電插頭之至少—部分。執行—金屬 就〉儿積。然後’以鑲嵌製程形成一交替出現於金屬和絕綾 膜之間的平面。 '' 在本發明之另一具體實施例中，提供一種在一積體電路 中對鑲嵌特徵執行間距增值的方法，該方法包括提供—基 板。執行—第—遮罩程序，以便於該基板上定義-間隔^ 線陣列。該等間隔物線被複數個間隙隔離。執行一第二遮 t程序以阻隔該等間隔物線之—部分，以及在積體電:之 一邏輯區域中定義複數個互連。於該等間隔物線之間的間 109141.doc 1309437 金屬層以便在該等間隔物 線。以鑲嵌製程提供該積 隙中蝕刻出複數個溝渠。沉積一 線之間的間隙中形成複數條金屬 體電路一實質上平坦的表面。 在本發明之另-具體實施例中，提供—種在—基板上形 成積體電路組件的方法，該方法包括㈣技術來圖[Invention J] - In the present invention, when the method is implemented, the method of providing a pattern of in-situ ambiguity is provided, and the first region of the method is used to etch the first light-Mu There are several characteristics in the mountains. In the low-mask layer, each of the special effects of the pitch-increasing method and the photoresist layer is used to >, two features. The special feature in the lower opacity 's contains the loop endpoint. 10914l.doc 1309437::: The photoresist layer covers a second region of a substrate comprising :::::. A ditches pattern is passed through the lower mask in the substrate to be engraved in the second region. The ditch has a method of ditching, another ά m w\ κ of the present invention, and displaying a plurality of wires, the method comprising providing a stack of 臈. The film stack includes a substrate in contact with a plurality of conductive plugs, an insulating film covering the cover, a lower mask layer covering the insulating film, and an array of spacers formed on the mask layer The sacrificial film is deposited on the lower mask layer and the array of spacers. A secondary mask is formed on the portion of the sacrificial film. The secondary mask defines an opening in the spacer array. The lower embedding layer and the sacrificial film can be selectively engraved relative to the secondary mask #. The sacrificial film is etched to expose the lower mask layer < The method further includes etching the lower mask layer and a portion exposing the insulating film. And (4) a plurality of trenches in the insulating film, the lower mask layer and the sacrificial film to expose at least a portion of the conductive plugs. Execution—metals. Then, a plane which alternates between the metal and the insulating film is formed by the damascene process. In another embodiment of the present invention, a method of performing pitch enhancement on a tessellation feature in an integrated circuit is provided, the method comprising providing a substrate. Execute the -mask procedure to define a -interval array on the substrate. The spacer lines are separated by a plurality of gaps. A second masking process is performed to block portions of the spacer lines, and a plurality of interconnects are defined in a logical region of the integrated body. Between the spacer lines 109141.doc 1309437 metal layers to be at the spacer lines. A plurality of trenches are etched into the gap by a damascene process. A plurality of metal circuits are formed in the gap between the deposited lines to form a substantially flat surface. In another embodiment of the present invention, a method of forming an integrated circuit component on a substrate is provided, the method comprising (4) a technique
案化-第—光阻層及定義複數條線。使用間距增值技術在 由該複數條線所定義的區域週圍形成—間隔物㈣。該等 間隔物包含具有迴圈端點的伸長迴圈。於該等迴圈端點上 沉積一第二抗蝕層，以定義該基板之-阻隔區域。該方法 進一步包括選擇性地㈣穿過該等間隔物，於基板中形成 複數個溝渠，而不蝕刻於該等阻隔區域中。 【實施方式】 特欲尺寸持續縮小導致對形成這些特徵的技術更大的要 求。例如’微職刻f被用於在基板上形成例如線的特徵 圖案。這些特徵的尺寸可以用間距的概念來描述。然而， 由於光或韓射波長等光學因素，使得微影⑽⑶術有一最 門距的限制，在此最小間距以τ，便無法可靠地形成特 徵。因此，微影蝕刻技術的最小間距會限制特徵尺寸縮 小。 一種被提出來能夠把微影蝕刻技術的能力擴大到超過其 最小間距的方法是間距加倍。此一方法如圖示，、 詳見美國專利第5,328,810號（1994年7月12日），該整體揭 丁内合以弓丨用方式併入本文中。如圖i A，首先以微影蝕刻 在一光阻層中形成線！0的圖案，該光阻層覆蓋—臨時或可 109141.doc 1309437 擴充材料層20及一基板30。執行微影蝕刻時常用的波長包 括’但不限於157 nm、193 nm、248 nm或365 nm。然後如 圖1B所示，以一蝕刻步驟，例如各向異性蝕刻步驟，將該 圖案轉移到該臨時層20,藉以形成定位器或心軸4〇。可將 光阻線10剝除並對心軸40進行等向性蝕刻以增加鄰近心軸 40之間的距離，如圖1C所示。接下來在心軸4〇上沉積一間 隔物材料層50,如圖1D所示。然後以一定向間隔物蝕刻， 優先從水平表面蝕刻間隔物材料，而在心軸4〇兩側形成間 隔物60，如圖1E所示。然後去除剩餘的心軸4〇，只留下間 隔物60，這些間隔物共同作為用於圖案化的遮罩，如圖 所不。因此，在先前定義一個特徵和一個間隔（各具有寬 度F，間距2F)之一給定的圖案區域之處，同一個圖案現在 由間隔物60定義，包括二個特徵和二個間隔（各具有寬度 别’間距F)e結果，藉由間距加倍技術，使用微影姓刻技 術所得到的最小可能特徵尺寸實際上縮小了。 以上例子中，雖然間距實際上是減半，但此—間距縮減 傳統上係稱為間距"加倍"，或更廣泛地稱為間距”增值”。 亦P傳統上所稱以一特定因數”增值”間距實際上是將間 距以該因數縮減。在此保留傳統的術語。可以發現，藉由 在間隔物上形成間隔物’可進—步縮減能夠定義的特‘尺 寸。因此間距增值係廣泛地意指該程序，$管間隔物形成 的程序實施了多少次。 上由於間隔物材料層5G通常具有—單—厚度％(請參見圖 10及1E) ’且由於由間隔物6〇所形成的特徵尺寸通常與該 1〇9l4l.d0( •10- 1309437 :度：有關，因此間距加倍技術所 ;，度。然而，積體電路經常會包括不同= 徵。例如，隨機存取記憶 寸的特 有記愔駚--@ 通㊉在所5月的，'週邊”内含 有4體早几陣列和邏輯電路。在陣列内， 内: 兀通常是由導線連接，且在…〆體單 接點接觸以便連接随们 ’該等導線通常與定位 ㈣以便連接陣列到邏輯 位接點可能比導線大。此外，週邊電：=，例如定 體，最好比陣列中的電…例如電晶 以用卩使週邊特徵可 1… 形成，但使用-單-的遮罩-般而 。…、法獲仔在定義電路方面所需要的彈性，尤其 被限制只能沿抗蝕圖案側壁形成時。 ’、 一些被提出來用於在週邊和陣列形成圖案的方法包括三 個個別的遮罩。例如’在一種方法中，係使用一第一遮罩 及間距加倍’在一晶片之一區域内，例如在一記憶體裝置 的陣列區域内’形成一通常包含間隔物迴圈的間隔物圖 案。然後’執行一第二遮罩以便在該晶片之另一區域内形 成一第二圖案’例如在一記憶體裝置之週邊區域内。此第 二週邊圖案係在一覆蓋該間隔物圖案的層中形成。如此覆 蓋該等間隔物迴圈的中央部位，該等間隔物的迴圈端點則 露出以便執行蝕刻製程。然後，執行一第三遮罩以形成一 第二圖案，其包括連至及/或連自該週邊區域之互連。然 後，該經"切斷的”間隔物圖案與該第三圖案兩者都轉移至 一可相對於底下基板蝕刻之底下的遮罩層。如此可在電路 週邊區域形成不同尺寸（相互之間比較或與間隔物迴圈比 I09141.doc • 11 - 1309437 杈）的特徵。此類特徵 „ 匕括例如，互連圖案。這此特n 可以和間隔物迴圈重疊、 —符谜 併，且後續可加以蝕刻。 寸伋口 二=:=Γ❹來形…尺寸的特 穷更瑩圖案的間距增值特徵。 在特定的具體實施例中，一部分要 圖案，其間距小於用來處 土板的特徵Case - the first photoresist layer and define a plurality of lines. A spacer (4) is formed around the area defined by the plurality of lines using a pitch increment technique. The spacers comprise an elongated loop having an end point of the loop. A second resist layer is deposited on the end points of the loops to define a barrier region of the substrate. The method further includes selectively (iv) passing through the spacers to form a plurality of trenches in the substrate without etching in the barrier regions. [Embodiment] The continued narrowing of the desired size leads to greater demands on the technology for forming these features. For example, the 'micro-inscription f' is used to form a feature pattern such as a line on a substrate. The dimensions of these features can be described by the concept of spacing. However, due to optical factors such as light or the wavelength of the Han ray, the lithography (10) (3) has a maximum gate distance limitation, where the minimum spacing is τ, and the features cannot be reliably formed. Therefore, the minimum spacing of the lithography technique limits the feature size reduction. One method proposed to be able to extend the ability of lithography techniques beyond their minimum spacing is to double the pitch. Such a method is shown in the drawings, and is described in detail in U.S. Patent No. 5,328,810 (July 12, 1994), which is incorporated herein by reference. As shown in Figure i A, the line is first formed in a photoresist layer by lithography! A pattern of 0, the photoresist layer covers - temporary or may be 109141.doc 1309437 expanded material layer 20 and a substrate 30. Wavelengths commonly used in performing lithography etching include, but are not limited to, 157 nm, 193 nm, 248 nm, or 365 nm. The pattern is then transferred to the temporary layer 20 by an etching step, such as an anisotropic etching step, as shown in Figure 1B, thereby forming a locator or mandrel. The photoresist line 10 can be stripped and the mandrel 40 is isotropically etched to increase the distance between adjacent mandrels 40, as shown in Figure 1C. Next, a spacer material layer 50 is deposited on the mandrel 4, as shown in Fig. 1D. The spacer material is then etched in a certain direction, preferentially etching the spacer material from the horizontal surface, and spacers 60 are formed on both sides of the mandrel 4, as shown in Fig. 1E. The remaining mandrels 4〇 are then removed, leaving only the spacers 60, which together act as a mask for patterning, as shown. Thus, where a feature region and a spacing (one having a width F, spacing 2F) are previously defined for a given pattern region, the same pattern is now defined by spacer 60, including two features and two spaces (each having The width of the 'pitch F) e results, by the pitch doubling technique, the smallest possible feature size obtained using the lithography technique is actually reduced. In the above example, although the pitch is actually halved, this - pitch reduction is traditionally referred to as spacing "doubling", or more broadly, spacing "value added." Also traditionally referred to as "a value-added" spacing by a particular factor is actually the reduction of the spacing by this factor. The traditional terminology is retained here. It has been found that the specific size that can be defined can be further reduced by forming spacers on the spacers. Therefore, the increase in pitch is broadly meant to refer to the procedure, how many times the procedure for forming a spacer is implemented. Since the spacer material layer 5G usually has a single-thickness % (see FIGS. 10 and 1E) 'and because the feature size formed by the spacer 6〇 is usually the same as the 1〇9l4l.d0 (•10-1309437:degree :Related, so the spacing doubles the technology;, degrees. However, the integrated circuit often includes different = sign. For example, the special memory of random access memory - @通十 in May, 'peripheral' Inside the array, there are several arrays and logic circuits. Inside the array, the inner: 兀 is usually connected by wires, and the contacts in the body are connected so that the wires are usually connected with the wires (4) to connect the array to the logic. The contact may be larger than the wire. In addition, the peripheral power: =, for example, the body, preferably more than the electricity in the array ... such as an electron crystal to make the peripheral features 1... but use a - single-mask - In general, the method requires the flexibility required to define the circuit, especially when it is limited to be formed along the sidewalls of the resist pattern. 'Some methods proposed for patterning the perimeter and the array include three individual Mask. For example 'in one method Using a first mask and spacing doubles 'in a region of a wafer, such as in an array region of a memory device' to form a spacer pattern that typically includes a spacer loop. Then 'perform a second Masking to form a second pattern in another region of the wafer, such as in a peripheral region of a memory device. The second peripheral pattern is formed in a layer overlying the spacer pattern. a central portion of the spacer loop, the loop end of the spacer being exposed to perform an etching process. Then, a third mask is performed to form a second pattern including to and/or from the periphery Interconnection of the regions. Then, both the "cut" spacer pattern and the third pattern are transferred to a mask layer that can be etched under the substrate with respect to the bottom substrate. Features of dimensions (comparison with each other or with spacer loop ratio I09141.doc • 11 - 1309437 。). Such features include, for example, interconnect patterns. This feature n can overlap with the spacer loop - the riddle of the puzzle, and can be etched subsequently. Inch 二 2 =: = Γ❹ 形 ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... Characteristics of the soil board
Μ理該基板之微景彡_技術的最小 間距。此外，可栋蛀6 J 置陣列…， 實施例來形成具有電子裝 " 匕括邏輯或閘陣列及例如DRAM、 憶體（"ROM")、快閃々掊辨β ea ± 賈5己 1 «己隐體及閘陣列等揮發性或 記憶體裝置。此類奘荖ώ _ η早赞性 裝置中，可使用間距增值法形成例如晶 片陣列區域内的電晶體閑極電極和導線，而傳統的微影姓 刻法可用來形成(例如接觸器)位於晶片週邊的較大特徵。 製造一記憶體裝置之示範的遮罩步驟如各圖所示且 下。 圖2顯示—示範之部分製造的積體電路丨〇〇之俯視圖，例 如一記憶體晶片。一中央陣列區域102被-週邊區域104所 包圍。將可明瞭，在積體電路⑽製造之後，陣列102通常 會推集地殖人導線和例如電晶體及電容器等電子裝置。如 在此所討論者，陣列區域1G2内的特徵可以用間距增值法 开/成卩方面，週邊區域1G4選擇性地包括比陣列區域 1 2大的特f政這些較大的特徵，例如，包括各種類型的 邏輯電路，其圖案—般而言是以傳統微影㈣法形成，而 不是用間距增值法。位於週邊區域1〇4之邏輯電路，其複 109141.doc -12- 1309437 . ㈣幾何形狀使得間距增值法難以實施。相反地，陣列圖 ； 案典型的規則柵格則有助於間距增值。此外，由於電方面 的限制，週邊區域104内有些裝置需要較大的幾何形狀， 而使彳于相較於傳統的微影蝕刻法而言，間距增值法較不適 合&些裝置。除了相對尺度可能有差別以外，在其它具體 實施例中，積體電路1〇〇中的週邊區域1〇4和陣列區域 的相對位置與數目也可能有異。 圖3顯示圖2之部分製造的積體電路的一部分斷面圖，其 _ 包括卩車列區域1〇2及週邊區域1G4之部分。使用微影餘刻技 術將複數個溝渠蝕刻到基板丨〇8中，並在這些溝渠中填入 例如氧化物的絕緣體1〇5。絕緣體1〇5為一場隔離層，在一 不範的具體實施例中，其為一在一高密度電漿（"HDp")、 旋塗介電質（"SOD”）、流填或TE〇s製程中沉積的淺溝隔離 ("sti")層。在一示範的具體實施例中，該s〇D被沉積且緻 密化。 於基板之上形成一上部層間介電質（"ILD")絕緣體1〇6， 且藉由將接觸孔姓刻並填入導電插頭11〇來構成與比〇 ι〇6 的接觸。在一具體實施例中，該等導電插頭110包含多晶 矽’雖然在其他具體實施例中，可能使用其它導電材料。 一例如氮化物層的蝕刻防止層112之部分係置放於該絕緣 體106之上；餘刻防止層U2係用於形成該等導電插頭 110 °在特定的具體實施例中，絕緣體105係對齊基板/插 頭介面。然而，在其它具體實施例中，絕緣體105係延伸 稍微超過基板/插頭的介面，如圖3所示。 109141.doc •13- 1309437The minimum spacing of the micro-mirror technology of the substrate. In addition, an array can be arranged, and the embodiment can be used to form an electronic device with a logic or gate array and, for example, DRAM, memory ("ROM"), flash ββ ea ± 贾5 1 «Volatile or memory devices such as hidden bodies and gate arrays. In such a 奘荖ώ η η pre-sense device, a pitch-increment method can be used to form, for example, a transistor idler electrode and a wire in a wafer array region, whereas conventional lithography can be used to form (eg, a contactor). Large features around the wafer. An exemplary masking step for fabricating a memory device is shown in the figures below. Figure 2 shows a top view of a partially fabricated integrated circuit, such as a memory chip. A central array region 102 is surrounded by a peripheral region 104. It will be appreciated that after fabrication of the integrated circuit (10), the array 102 will typically push the ground conductors and electronic devices such as transistors and capacitors. As discussed herein, features within the array region 1G2 may be opened/incremented by a pitch increment method, and the peripheral region 1G4 selectively includes larger features than the array region 12, for example, including The various types of logic circuits, the pattern is generally formed by the traditional lithography (four) method, rather than the pitch increment method. The logic circuit located in the surrounding area is 1094, which is 109141.doc -12- 1309437. (4) The geometry makes the pitch increment method difficult to implement. Conversely, the typical rule grid of the array map helps the pitch increase. In addition, due to electrical limitations, some devices in the peripheral region 104 require larger geometries, and the pitch-increasing method is less suitable for <some devices than conventional microlithography. In addition to the possible differences in relative scales, in other specific embodiments, the relative positions and numbers of the peripheral regions 1〇4 and the array regions in the integrated circuit 1〇〇 may also differ. Fig. 3 is a partial cross-sectional view showing the integrated circuit of the portion of Fig. 2, which includes a portion of the brake train region 1〇2 and the peripheral region 1G4. A plurality of trenches are etched into the substrate 8 using a lithography technique, and an insulator such as an oxide 1 〇 5 is filled in the trenches. The insulator 1〇5 is a spacer layer. In an exemplary embodiment, it is a high-density plasma ("HDp"), spin-on dielectric ("SOD"), flow-fill or A shallow trench isolation ("sti") layer deposited in the TE〇s process. In an exemplary embodiment, the s〇D is deposited and densified. An upper interlayer dielectric is formed over the substrate (" The ILD") insulator 1〇6, and the contact with the 〇ι〇6 is formed by engraving the contact hole and filling the conductive plug 11〇. In a specific embodiment, the conductive plug 110 comprises a polysilicon 矽Although in other embodiments, other conductive materials may be used, a portion of the etch-preventing layer 112, such as a nitride layer, is placed over the insulator 106; a residual prevention layer U2 is used to form the conductive plugs 110. In a particular embodiment, the insulator 105 is aligned with the substrate/plug interface. However, in other embodiments, the insulator 105 extends slightly beyond the interface of the substrate/plug, as shown in Figure 3. 109141.doc •13 - 1309437
在圖3所示的示範具體實施例中，陣列區域m内的特徵 =寸比週邊區域HM内的特徵尺寸小。在—具體實施例 中，該等導電插頭m具有-大約50 nm的特徵尺寸。在一 較佳的具體實施例中，該等導電插頭11〇具有一在大約％ 腿和大約⑽㈣之間的特徵尺寸。尤其更佳是，該等導電 插頭具有一在大約32 5 nm和大約65 nm之間的特徵尺寸。 在其它具體實施例中可以使用具有其它不同特徵尺寸的導 電插頭110。關於形成導電插頭的額外技術細節可參考美 國專利中請案--------(隨本中請案附上；Attorney D()eke、t MICRON.313A ; Micron Docket 2004-1065.00/US)。 如圖4所示，於圖3所示之膜堆疊上沉積一絕緣膜ιΐ4， 將於其内形成鑲嵌溝渠。在一具體實施例中，該絕緣膜包 含一無摻雜的氧化物膜’例如一沉積自四乙基矽酸鹽 ("TE0S”）的氧化物膜，而在另一具體實施例中，該絕緣膜 包含一摻雜的氧化膜，例如BPSG或PSG。尚有其它具體實 施例可能使用其它非氧化物絕緣體。在一示範的具體實施 例中，絕緣膜114係沉積至一於積體電路中將要形成的導 體高度相應的厚度。 如圖5所示’於絕緣膜114之上沉積一硬遮罩層116。在 一具體實施例中，該硬遮罩層116包含非晶石夕，雖然於其 它具體實施例中可能使用其它的材料。 如圖6A所示，於該硬遮罩層11 6之上形成複數個間隔物 11 8。在一示範的具體實施例中，該等間隔物之形成係利 用如圖1A至1F所示的間距加倍技術、使用所揭示之光阻遮 109141.doc -14- 1309437 罩、轉移至一臨時層、等向性蝕刻及間隔物製程。在—示 範的具體實施例中，該等間隔物包含—可相對於其底下: 遮罩層116選擇性地進行蝕刻的低溫氧化物材料。例如， 在一具體實施例中，該等間隔物係在一低於約4〇〇。〇的溫 度下沉積。在另一具體實施例中’該等間隔物係利用一原 子層沉積製程沉積。示範的間隔物材料包括氧化矽、氮化 矽、多晶矽及碳。 間隔物118之間為間隙12〇，其對應於將要沉積導電材料 的積體電路區域。在如圖6A所示的示範具體實施例中，該 等間隙120在垂直方向上與該等導電插頭i丨〇對齊。 在一示範的具體實施例中，間隔物！丨8和間隙i 2〇之間的 間隔，在積體電路1〇〇的陣列區域1〇2和週邊區域1〇4内是 不同的。這一點進一步顯示於圖6B，其示意性顯示為該等 間隔物118和中間間隙12〇的俯視圖。圖沾亦顯示出，間隔 物11 8大致沿著形成於光可定義層中的輪廓線，而形成複 數個迴圈端點124。 如圖7所示’於間隔物118上應用一 barC 122。BARC 122係選擇性地以一旋塗製程應用，藉以提供一實質上平 坦的表面。將BARC 122應用於間隔物11 8上面之後，再應 用一第二遮罩。該第二遮罩最後會成為將沉積於積體電路 上面之光阻126的圖案。該光阻圖案定義一阻隔區域，將 間隔物118的迴圈端點124阻隔，並在週邊區域104内定義 一或多個開口 128。此如圖8A(側視圖）和8B(俯視圖）所 示。如圖8B所示’在一示範的具體實施例中，該第二遮罩 10914l.doc •15· 1309437 與間隔物118相距間隙12〇3的距離，且與間隔物迴圈端點 124相距間隙12〇b的距離。間隙12〇a、12〇b用於提供該第 二遮罩相對於該間隔物圖案的偏差。 在一示範的具體實施例中，開口 128的最小寬度取決於 微影蝕刻製程固有的解析度，在一具體實施例中，該解析 度相當低，只有loo nm ’在另一具體實施例中，只有65 nm，且另一具體實施例中只有45 nm。在其它具體實施例 中可能使用其它的尺寸。在一示㈣具體實施例中，電路 陣列區域104内的間隔物丨18相隔足以在它們之間”植入"接 觸器132的距離，以提供至積體電路其它層的互連。 在一不範的具體實施例中，該執行第二遮罩之後，對 BARC 122執行餘刻’如目9所示。在一修正的具體實施例 中，對BARC蝕刻之前’先將由該第二遮罩所定義的圖 案’包括阻隔區域，轉移至—巾間層。此類具體實施例 中，係以3亥中間層或單獨用BARC來阻隔間隔物丨丨8的迴圈 端點124。 繼BARC蚀刻之後’對硬遮罩層116進行㈣，可相對於 間隔物118選擇性地進行钕刻。結果得到圖iga(沿垂直於 間隔物迴圈的直線截切所得到的斷面圖）和圖1 〇B(沿間隔 物迴圈縱向截切所得到的斷面圖）的㈣。在一具體實施 例中該硬遮罩#刻係採取乾式钱刻製程。之後相繼去除 光阻126和BARC 122,然後進行氧化物㈣。此類具體實 &例中’ β氧化物#刻將同時把間隔物ιΐ8和絕緣膜的 曝路4刀去除。V電插頭11 〇提供一姓刻阻止的作用。結 109141.doc -16- 1309437 果得到如圖11所示的結構，其包括一使位在陣列區域102 内之導電插頭110露出的溝渠的圖案，以及一位在週邊區 域104内之硬遮罩層116中的其它開口 128的圖案。此順序 有利地降低了溝渠的有效高寬比。在一修正的具體實施例 中’在蝕刻圖10A和10B所示之絕緣膜114之前，並未先將 間隔物118去除。在基板材料係不能反射的具體實施例 中，可選擇性地省略BARC 122。 不論溝渠如何形成，圖10A、10B和11所示的蝕刻程序 都可有利地合併2個遮罩圖案：陣列區域丨02内由間隔物 118形成的圖案，以及週邊區域内由光阻ι26形成的圖案。 如此有效地形成兩種不同圖案的疊加，使得在積體電路 100未被第一光阻層126覆盖的的區域内，餘刻能夠穿過間 隔物118之間的間隙120。 接下來，如圖12所示，在一示範的具體實施例中，於部 分形成的的積體電路上沉積導電材料13〇。在沉積導電材 料130之前，可選擇先去除硬遮罩層116。適合的導電材料 包括，但不限於，鈦、氮化鈦、鎢、氮化钽和鋼。在一示 範的具體實施例中，導電材料13〇係沉積至一足夠把週邊 最寬的溝渠填滿的厚度。導電材料沉積之後，使用一化學 機械式平面化（"CMP")製程分隔溝渠中的導體並提供具有 平坦表面的積體電路。結果如圖丨3所示的結構。 ★圖14提供形成本發明所揭示之特定積體電路結構之—示 耗製程的流程圖。如圖$ ’操作區塊15〇中，於記憶體裝 之陣列區域内之一第一抗蝕層中定義複數個特徵。^ I09I41.doc 1309437 用來定義該等特徵的抗㈣的例子係光阻層和壓印抗姓 層。操作區塊152中，以這些特徵為基礎，使用間距增值 法在—較低遮罩層㈣義複數個間隔物迴圈。纟一修正的 具體實施财，該等間隔物迴圈係形成於該等已圖案化的 抗姓特徵上面，不過此並非最好的方式，因為光阻通常不 能而f受間隔物沉積和姓刻製程。.操作區塊156中，以一也 在積體電路之-週邊區域内定義特徵的第二抗隔該 4間隔物迴圈的端點。操作區塊158中，在該第二抗钮層 應用之後’對-位在間隔物之間的間隙中的絕緣層進行姓 刻，該钱刻係在一由該第二抗蚀層所定義的圖案中執行。 然後在操作區塊160中’於部分形成的的積體電路上執行 金屬填充及後續的CMP製程，藉以在該積體電路的陣列區 域内形成金屬線（操作區塊162)，以及在該積體電路的週邊 區域形成電互連（操作區塊164)。選擇性地使用該等互連連 接週邊區域内的積體電路組件，例如邏輯組件。或者，夺 第二遮罩可同時阻隔該等間隔物迴圈以^義例如電容琴/ 接觸器、電阻器等其它圖案。 ° 定二具體實施例中’該等週邊互連被選擇性地用於 形成陣列區域102和週邊p· 0 1Λ ^ 週邊£域104之間的電連接，如圖14的 操作區塊16 6所示。例如，^ 〇 圖16提供一個此種”架空"接觸 态的例子。如圖示，該# ⑷連接的接觸器146上接觸11包括複數個以互連線 圖17Α至17C提供圖14所f 述方法之一示範的具體實施例 109141.doc 1309437 的俯視圖。特定言之，圖I? _ 義之一第一遮罩〗34。在—且八顯不由一微影蝕刻程序所定 係定義於一光阻材料層中/、實知例中，該第一遮罩〗34 第-遮罩m係轉移至另—雖然在其它具體實施例中，該 示，藉由先以一等向钱刻—製層程=如非晶碳層。圓m顯 對收縮後之該第-遮罩實 、、’§該第—遮罩134，然後 隔物圖案136。應用一第…蝕刻加倍技術’而建立-間 干…# 金屬遮罩138產生圖所示之 不乾的結構。此結構中， ™ ,, ^ 間隔物圖案包括加寬的部分，配 置成用以容納來自積體 1刀配 電路其它層的接觸器139。 本發明所揭示之一 4b錄h + 二特疋的積體電路之製造技術提供遠 勝於傳統技術的優點。例 傳、，充方法而要用三個個別的 遮罩來疋義陣列區域、& M、m & 一 疋義週邊區域、以及去除電路特徵 的迴圈端點。而本發明裕姐_ 不^明所揭不之一些特定的技術允許在一 只使用二個遮罩的鑲嵌製程中形成間距縮小的特徵。如本 說月曰所述，在示範的具體實施例中，該可以用定義週邊 特徵所用之同一遮罩來阻隔陣列特徵的迴圈端點。 在特疋具體實把例之另一方面中，提供幫助電路設計人 員實現本發明所揭示之積體電路之製造方法的準則。遮罩 之組態與形成的積體電路圖案有間接的關係，尤其是當重 要的電路特徵是由間隔物迴圈之間的間隙定義時，這些間 隙有些被包圍’有些則否。該等特徵如本發明所揭示可利 用間距增值及鑲嵌技術形成。以下所述之準則提供給電路 設計人員作為指導方針，用以建造能夠以本發明所揭示技 術形成的電路。如以下所述，遵守這些準則來建造電路允 109141 .doc •19- 1309437 許，、利用二個遮罩即可混合使用不同間距尺寸的互連。特 定言之，、係使用—間隔物層遮罩（或”間隔物”）來定義電路 陣列區域内密集的互連線之間的間距縮減間隔物，以及使 用一金屬層遮罩（或”金屬”）來定義電路週邊區域内的 累。 在一不範的具體實施财’用於定義該間隔物與金屬的 設計準則係根據二個尺度因數。對於—給定的微影技術而 為其所能夠解析的最小特徵尺寸，d為兩個遮罩之間 最大容許的偏差。變數乂為一間距增值尺度常數(〇 < X < …其對應於在定義該等金屬線時所使用的間隔物迴圈的 特徵尺寸。由於使用單一的間距增值技術，因此利用本發 明所揭示之技術可達到的實際互連間距為f。 在-具體實施例中，該等間隔物迴圈係拉成複數條不互 相重疊或交叉的個別封閉迴圈。圖15顯示二個示範的間隔 物坦圈140 ’此圖係在製程中的積體電路簡單說明的示範 俯視圖。如圖示’該等間隔物迴圈具有一最小寬度^，及 一最小間隔（1_X)F。 此等具體實施例中’複數個間隔物迴圈140定義出複數 個金屬特徵144 °由於在較佳具體實施例中係使用鑲嵌製 程，因此該等間隔物迴圈之間的間隙（有些被包圍，有些 則否）定義後續將以導電金屬材料沉積（例如，以物理汽相 沉積或化學汽相沉積）或電錢的金屬特徵144。此外，金屬 特徵142只有一側由間隔物迴圈14〇定義。兩側都由間隔物 迴圈140定義的金屬特徵144具有一最小寬度（1_X)F。只有 109141.doc -20- 1309437 —側由間隔物迴圈14〇定義的金屬特徵142具有一最小寬度 ((l-x)F + D)。金屬特徵；^ -p ^ 行做亦可不受限於使用具有-最小寬 度係對應於微影技術之最小解析度F的間隔物迴圈140形 成。如圖15所示’金屬特徵144若以間隔物迴圈14〇分隔則 具有-最小間隔XF’而金屬特徵142若以空格或只在一側 以間隔物迴圈14 0分隔則且古 „ , 畑貝J具有—敢小間隔F。若間隔物迴圈 ⑽兩側都有金屬特徵142或144出現，則金屬被拉到 隔物迴圈刚接觸（亦即，金屬佔據其旁邊緊鄰的空間/。、若 間隔物迴圈嘱一側有金屬特徵142出現，則金屬特徵 144離間隔物迴圈140以-最小間隔為min(D，xF，0)分隔。 在此所解說之電路設計準則係基於本發明所揭示之積體 電路之製k技術。特定言之’使用特大的間隔物遮罩來 義後續關距料純纽Μ料岐料㈣所定義 之金屬線的間隔。 按照本發明所揭示之示範具體實施例所提供的準則來個 別定義金屬和間隔物層，讓電路設計人員能夠根據晶圓上 將出現的實際電路特徵來建造積體電路。這些準則有利地 解除了使用間距增值技術來形成電路特徵的固有限制。使 用尺度參數Χ讓這些設計準則可適用於未來能夠製 特徵尺寸的間距增值技術。 本發明所揭Μ特定的具體實施例可用於形成廣泛種類 的積體電路。這些積體電路的例子包括，但不限於 電子裝置陣列的電路，例如用於如DRAM、峨或 憶體等揮發性及非揮發性記憶體的記憶體單元陣列： 109141.doc •21 · 1309437 NAND快閃記憶體及具有邏輯或閘陣列的積體電路。例 如’該邏輯陣列可為—種場可程式化閘陣列6pg乂V其具 有一類似於記憶體陣列之核心陣列及—支援邏輯電路^週 邊。因此’使用本發明所揭示之技術所形成的積體電路可 為’例如，-記憶體晶片或一處理器，其可同時包含邏輯 陣列及嵌人的記憶體兩者；或可為其它具有邏輯或閘陣列 的積體電路。 雖=前文詳細解說本發明之—些具體實施例，但應能瞭 解’故些說明只是為了解釋的目的，並非要限制本發明。 應可明白’有可能做出不同於前述的特㈣造和操作，且 本發明所揭示之方法可用於積體電路之製造以外的相 置。 ’ 【圖式簡單說明】 附圖顯示積體電路及積體電路製造技術之示範的具體實 施例，這些具體實施例只是說明的㈣。附圖包括下列各 圖，不-定按照比例。®中相同的數字代表相同的零件。 圖1A為一其上形成具有複數條遮罩線的基板的斷面圖。 圖1B為在經過各向異性蝕刻製程將遮罩圖案轉移至一臨 時層内之後的圖1A之基板的斷面圖。 圖1C為在該等遮罩線被去除及經過一等向性"收縮"蝕刻 之後的圖1B之基板的斷面圖。 圖1D為在一間隔物材料沉積包覆心軸之後遺留在臨時層 的圖1C之基板的斷面圖。 圖1 E為在經過一定向間隔物蝕刻製程留下間距增值特徵 109141.doc -22- 1309437 或間隔物之後的圖ID之基板的斷面圖。 圖1F為在去除心軸之後的圖1£之基板的斷面圖。 圖2為一示範的部分形成的積體電路的示意俯視圖。 圖3為在該基板之内及之上形成複數個間距增值特徵之 後的圖2之部分形成的積體電路的示意斷面側視圖。 圖4為在其上形成一絕緣膜之後的圖3之部分形成的積體 電路的示意斷面側視圖。 圖5為在其上形成一硬遮罩層之後的圖4之部分形成的積 體電路的示意斷面側視圖。 圖6A為在其上形成複數個間隔物之後的圖5之部分形成 的積體電路的示意斷面側視圖。 圖6B為圖0A之部分形成的積體電路的示意俯視圖。 圖7為在其上形成一底部抗反射塗層（"BARC")之後的圖 6A之部分形成的積體電路的示意斷面側視圖。 圖8A為在其上形成一第二光阻圖案之後的圖7之部分形 成的積體電路的示意斷面側視圖。 圖8B為圖8A之部分形成的積體電路的示意俯視圖。 圖9為在蝕刻該底部抗反射塗層之後的圖8 a之部分形成 的積體電路的示意斷面侧視圖。 圖10 A為在银刻該硬遮罩層穿過該等間隔物及該第二光 阻圖案之後的圖9之部分形成的積體電路的示意圖；此圖 係沿一與一間隔物迴圈垂直的直線截切所得到的斷面圖。 圖10B為在触刻該硬遮罩層穿過該等間隔物及該第二光 阻圖案之後的圖9之部分形成的積體電路的示意圖；此圖 109141.doc -23· 1309437 係沿間隔物迴圈縱向截切所得到的斷面圖β 圖11為在蝕刻絕緣膜及去除該光阻、該B ARC及該等間 隔物之後的圖10A之部分形成的積體電路的示意斷面圖。 圖12為在其上沉積一導電材料之後的圖11之部分形成的 積體電路的示意斷面圖。 圖13在執行一化學機械平面化製程之後的為圖12之部分 形成的積體電路的示意斷面圖。 圖14之流程圖說明形成本發明特定積體電路結構之示範 的製程。 圖15為一包含間隔物迴圈及一金屬層之部分形成的積體 電路的示意俯視圖。 圖16為圖13之部分形成的積體電路，進一步在陣列區域 及週邊區域之間包含一架空接觸器的示意斷面圖。 圖17 A為利用微影蝕刻製程形成之一第一遮罩的配置 圖；該第一遮罩定義複數個心軸。 圖17B為在圖17A之心軸上執行一間距增值技術所得到 之一間隔物圖案的配置圖。 圖17C為對圖17B之間隔圖案應用一第二金屬遮罩所形 成之部分形成的積體電路的配置圖。 【主要元件符號說明】 10 線 20 臨時或可擴充材料層 30 基板 40 心軸 109141.doc •24- 1309437 50 間隔物材料層 60 間隔物 90 厚度 100 積體電路 102 陣列區域 104 週邊區域 105 絕緣體 106 絕緣體 108 基板 110 導電插頭 112 敍刻防止層 114 絕緣膜 116 硬遮罩層 118 間隔物 120 間隙 120a 間隙 120b 間隙 124 迴圈端點 122 底部抗反射塗層（BARC) 126 光阻層 128 開口 130 導電材料 132 接觸器 134 第一遮罩 109141.doc -25- 1309437 136 138 139 140 142 144 146 148 間隔物圖案 第二金屬遮罩 接觸器 間隔物迴圈 金屬特徵 金屬特徵 接觸器 互連線In the exemplary embodiment illustrated in Figure 3, the feature = inch in the array region m is smaller than the feature size in the peripheral region HM. In a particular embodiment, the electrically conductive plugs m have a feature size of - about 50 nm. In a preferred embodiment, the electrically conductive plugs 11A have a feature size between about % leg and about (10) (d). More preferably, the electrically conductive plugs have a feature size of between about 32 5 nm and about 65 nm. Conductive plugs 110 having other different feature sizes can be used in other embodiments. For additional technical details on the formation of conductive plugs, please refer to the US patent application ------- (attached to the request; Attorney D () eke, t MICRON.313A; Micron Docket 2004-1065.00/US ). As shown in FIG. 4, an insulating film ι 4 is deposited on the film stack shown in FIG. 3, and an inlaid trench is formed therein. In a specific embodiment, the insulating film comprises an undoped oxide film 'eg, an oxide film deposited from tetraethyl silicate ("TEOS)), and in another embodiment, The insulating film comprises a doped oxide film such as BPSG or PSG. Other embodiments may use other non-oxide insulators. In an exemplary embodiment, the insulating film 114 is deposited to an integrated circuit. The height of the conductor to be formed is correspondingly thick. As shown in Fig. 5, a hard mask layer 116 is deposited over the insulating film 114. In a specific embodiment, the hard mask layer 116 comprises amorphous rock, although Other materials may be used in other embodiments. As shown in Figure 6A, a plurality of spacers 11 8 are formed over the hard mask layer 116. In an exemplary embodiment, the spacers are The formation system utilizes the pitch doubling technique shown in Figures 1A through 1F, using the disclosed photoresist mask 109141.doc -14 - 1309437 cover, transfer to a temporary layer, isotropic etching, and spacer process. In a specific embodiment, the spacers Including - a low temperature oxide material that is selectively etchable with respect to the underlying layer 116. For example, in one embodiment, the spacers are at a temperature of less than about 4 Torr. In another embodiment, the spacers are deposited using an atomic layer deposition process. Exemplary spacer materials include tantalum oxide, tantalum nitride, polysilicon and carbon. The spacers 118 have a gap of 12 〇, It corresponds to an integrated circuit region where a conductive material is to be deposited. In an exemplary embodiment as shown in Figure 6A, the gaps 120 are aligned in the vertical direction with the conductive plugs i. In an exemplary implementation In the example, the interval between the spacers 丨8 and the gap i 2 , is different in the array area 1 〇 2 and the peripheral area 1 〇 4 of the integrated circuit 1 。. This is further shown in Fig. 6B. It is schematically shown as a top view of the spacers 118 and the intermediate gaps 12A. The figures also show that the spacers 11 8 form substantially a plurality of loop end points along a contour line formed in the photodefinable layer. 124. As shown in Figure 7, A barC 122 is applied to the spacer 118. The BARC 122 is selectively applied in a spin coating process to provide a substantially flat surface. After the BARC 122 is applied over the spacers 11, a second mask is applied. The second mask will eventually become a pattern of photoresist 126 to be deposited over the integrated circuit. The photoresist pattern defines a barrier region that blocks the loop end 124 of the spacer 118 and is within the peripheral region 104. One or more openings 128 are defined. This is illustrated in Figures 8A (side view) and 8B (top view). As shown in Figure 8B, in an exemplary embodiment, the second mask 10914l.doc • 15· 1309437 is spaced from the spacer 118 by a distance of 12 〇 3 and a distance of 12 〇 b from the spacer loop end 124. The gaps 12〇a, 12〇b are used to provide a deviation of the second mask from the spacer pattern. In an exemplary embodiment, the minimum width of the opening 128 depends on the resolution inherent to the lithography process. In a particular embodiment, the resolution is relatively low, only loo nm 'in another embodiment, Only 65 nm, and in another embodiment only 45 nm. Other dimensions may be used in other embodiments. In a preferred embodiment, the spacers 18 in the circuit array region 104 are spaced apart by a distance sufficient to "implant" the contactors 132 therebetween to provide interconnection to other layers of the integrated circuit. In an exemplary embodiment, after the second mask is executed, the remainder of the BARC 122 is performed as shown in item 9. In a modified embodiment, before the BARC is etched, the second mask will be used first. The defined pattern 'includes a barrier region, which is transferred to the inter-sheet layer. In such a specific embodiment, the loop end point 124 of the spacer 丨丨8 is blocked by a 3 kel intermediate layer or with a BARC alone. Then, (four) is performed on the hard mask layer 116, and the engraving can be selectively performed with respect to the spacer 118. As a result, a figure iga (a cross-sectional view taken along a line perpendicular to the spacer loop) and FIG. 1 are obtained.四B (cross-sectional view taken along the longitudinal section of the spacer loop) (4). In a specific embodiment, the hard mask # is a dry-cut process, and then the photoresist 126 and the BARC 122 are successively removed. Then carry out the oxide (4). This kind of concrete & At the same time, the spacer ι 8 and the exposure film of the insulating film are removed at the same time. The V-electric plug 11 〇 provides a function of blocking the last name. The knot 109141.doc -16- 1309437 is obtained as shown in FIG. It includes a pattern of trenches that expose the conductive plugs 110 in the array region 102, and a pattern of other openings 128 in the hard mask layer 116 in the perimeter region 104. This sequence advantageously reduces the trench Effective aspect ratio. In a modified embodiment, the spacers 118 are not removed prior to etching the insulating film 114 shown in FIGS. 10A and 10B. In a specific embodiment in which the substrate material is not reflective, The BARC 122 is selectively omitted. Regardless of how the trench is formed, the etching process illustrated in Figures 10A, 10B, and 11 can advantageously incorporate two mask patterns: a pattern formed by the spacers 118 in the array region 丨02, and a peripheral region. a pattern formed by the photoresist 126. The stacking of the two different patterns is effectively formed such that in the region where the integrated circuit 100 is not covered by the first photoresist layer 126, the remaining portion can pass between the spacers 118 Room 120. Next, as shown in Fig. 12, in an exemplary embodiment, a conductive material 13 is deposited on the partially formed integrated circuit. Before depositing the conductive material 130, the hard mask layer may be removed first. 116. Suitable conductive materials include, but are not limited to, titanium, titanium nitride, tungsten, tantalum nitride, and steel. In an exemplary embodiment, the conductive material 13 is deposited to a wide enough trench around the perimeter Filled thickness. After deposition of the conductive material, a chemical mechanical planarization ("CMP") process is used to separate the conductors in the trench and provide an integrated circuit with a flat surface. The result is the structure shown in Fig. 3. Figure 14 provides a flow chart of a process for forming a particular integrated circuit structure as disclosed herein. As shown in the $' operating block 15A, a plurality of features are defined in one of the first resist layers in the array region of the memory device. ^ I09I41.doc 1309437 Examples of anti-(four) used to define these features are the photoresist layer and the imprinted anti-surname layer. In operation block 152, based on these features, a pitch increment method is used to loop a plurality of spacers in the lower mask layer (four). In the specific implementation of the correction, the spacer loops are formed on the patterned anti-surname features, but this is not the best way, because the photoresist is usually not capable of being deposited by spacers and surnames. Process. In operation block 156, the second impedance of the spacer is defined by a second impedance that also defines features in the peripheral region of the integrated circuit. In the operation block 158, after the application of the second button layer, the insulation layer in the gap between the spacers is subjected to a surname, which is defined by the second resist layer. Executed in the pattern. Metal fill and subsequent CMP processes are then performed on the partially formed integrated circuit in operation block 160 to form metal lines (operation block 162) in the array region of the integrated circuit, and in the product The peripheral regions of the bulk circuit form an electrical interconnection (operation block 164). These interconnects are selectively used to connect integrated circuit components, such as logic components, within the peripheral region. Alternatively, the second mask can block the spacer loops at the same time to define other patterns such as a condenser/contactor, a resistor, and the like. In the second embodiment, the peripheral interconnects are selectively used to form an electrical connection between the array region 102 and the peripheral p. 0 1 Λ ^ peripheral domain 104, as in the operational block 16 of FIG. Show. For example, Figure 16 provides an example of such an "overhead" contact state. As shown, the contact 11 on the #(4) connected contactor 146 includes a plurality of interconnects provided in Figures 14A through 17C. A top view of a specific embodiment 109141.doc 1309437 exemplified by one of the methods. In particular, one of the first masks 34 of FIG. 1 is defined as a light defined by a lithography process. In the resistive layer, in the practical example, the first mask 34 is moved to the other mask - although in other embodiments, the indication is made by first aligning The lamination = such as an amorphous carbon layer. The circle m is used to converge the first-mask, then the § the first-mask 134, and then the spacer pattern 136. The application of an ... etching double technique is established - Interstitial...# The metal mask 138 produces a structure that is not shown in the figure. In this structure, the TM , , ^ spacer pattern includes a widened portion configured to accommodate other layers from the integrated circuit of the integrated circuit 1 Contactor 139. The manufacturing technology of the integrated circuit of 4b recording h + two special 提供 disclosed by the present invention provides far superior The advantages of the conventional technology. The example, the charging method uses three individual masks to delimit the array area, & M, m & a peripheral area, and the loop end point of the circuit feature is removed. Invention Yu Jie _ Some specific techniques that are not disclosed allow for the formation of a reduced pitch feature in a damascene process using two masks. As described in this example, in the exemplary embodiment, The same mask used to define the perimeter features can be used to block the loop endpoints of the array features. In another aspect of the invention, the circuit designer is provided to implement the fabrication of the integrated circuitry disclosed herein. The criteria of the method. The configuration of the mask has an indirect relationship with the formed integrated circuit pattern, especially when important circuit features are defined by the gap between the spacer loops, these gaps are somewhat surrounded by 'some are not These features can be formed using pitch enhancement and tessellation techniques as disclosed herein. The criteria described below are provided to circuit designers as a guideline for building the invention. Reveal the circuit formed by the technology. As described below, follow these guidelines to build the circuit. 109141 .doc •19- 1309437, using two masks to mix interconnects of different pitch sizes. In particular, Use a spacer layer mask (or "spacer") to define the pitch reduction between dense interconnect lines in the area of the circuit array, and use a metal layer mask (or "metal") to define the circuit perimeter Tire in the area. The design criteria used to define the spacer and metal are based on two scale factors. For a given lithography technique, the minimum feature size that can be resolved , d is the maximum allowable deviation between the two masks. The variable 乂 is a pitch increment scale constant (〇 < X < ... which corresponds to the feature size of the spacer loop used in defining the metal lines. Since a single pitch increment technique is used, the present invention is utilized The actual interconnect spacing achievable by the disclosed technique is f. In a particular embodiment, the spacer loops are drawn into individual closed loops that do not overlap or intersect each other. Figure 15 shows two exemplary intervals. The object circle 140 'This figure is an exemplary top view of the integrated circuit in the process. As shown in the figure, the spacer loop has a minimum width ^, and a minimum interval (1_X) F. In the example, a plurality of spacer loops 140 define a plurality of metal features 144 °. Because in the preferred embodiment, the damascene process is used, so the gap between the spacers is somewhat enclosed (some are surrounded, some are not Defining a metal feature 144 that will subsequently be deposited (eg, by physical vapor deposition or chemical vapor deposition) or electricity money with a conductive metal material. Further, only one side of the metal feature 142 is surrounded by spacers 14 〇 Definition. The metal feature 144 defined on both sides by the spacer loop 140 has a minimum width (1_X) F. Only 109141.doc -20- 1309437 - the metal feature 142 defined by the spacer loop 14 具有 has one The minimum width ((lx)F + D). The metal feature; ^ -p ^ can also be formed without limitation using a spacer loop 140 having a minimum resolution F corresponding to the minimum resolution F of the lithography technique. The metal feature 144 shown in Fig. 15 has a - minimum interval XF' if separated by a spacer loop 14 而 and the metal feature 142 is separated by a space or only on one side with a spacer loop 14 0 and is 古 , 畑The shell J has a small interval F. If the metal features 142 or 144 appear on both sides of the spacer loop (10), the metal is pulled to the spacer loop just after contact (ie, the metal occupies the space next to it). If the metal feature 142 appears on the side of the spacer loop, the metal features 144 are separated from the spacer loop 140 by a minimum spacing of min(D, xF, 0). The circuit design guidelines illustrated herein are based on The k-technology of the integrated circuit disclosed by the present invention. The spacing of the spacers is defined by the spacing of the metal lines defined by the subsequent blanks (4). The metal and spacer layers are individually defined in accordance with the guidelines provided by the exemplary embodiments of the present disclosure. Circuit designers can build integrated circuits based on the actual circuit characteristics that will appear on the wafer. These guidelines advantageously eliminate the inherent limitations of using pitch-added techniques to form circuit features. Using scale parameters allows these design criteria to be applied to the future. A pitch-added technique capable of producing feature sizes. The specific embodiments of the present invention can be used to form a wide variety of integrated circuits. Examples of such integrated circuits include, but are not limited to, circuits of electronic device arrays, such as for example Memory cell arrays of volatile and non-volatile memory such as DRAM, germanium or memory: 109141.doc • 21 · 1309437 NAND flash memory and integrated circuits with logic or gate arrays. For example, the logic array can be a field programmable gate array 6pg乂V having a core array similar to a memory array and a supporting logic circuit periphery. Thus, the integrated circuit formed using the techniques disclosed herein can be, for example, a memory chip or a processor that can include both a logic array and embedded memory; or can have other logic Or the integrated circuit of the gate array. The present invention has been described in detail with reference to the preferred embodiments of the invention. It should be understood that it is possible to make special (four) fabrications and operations other than those described above, and that the methods disclosed herein can be used for configurations other than the fabrication of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS The drawings show specific embodiments of an integrated circuit and an integrated circuit manufacturing technique, and these specific embodiments are merely illustrative (4). The drawings include the following figures, which are not to scale. The same numbers in ® represent the same parts. Figure 1A is a cross-sectional view of a substrate having a plurality of mask lines formed thereon. Figure 1B is a cross-sectional view of the substrate of Figure 1A after the mask pattern has been transferred to a temporary layer through an anisotropic etch process. Figure 1C is a cross-sectional view of the substrate of Figure 1B after the mask lines have been removed and subjected to an isotropic "shrink" etch. Figure 1D is a cross-sectional view of the substrate of Figure 1C remaining in the temporary layer after deposition of the spacer material onto the mandrel. Figure 1E is a cross-sectional view of the substrate of Figure ID after leaving a spacer-valued feature 109141.doc -22- 1309437 or spacer after a certain spacer etching process. Figure 1F is a cross-sectional view of the substrate of Figure 1 after removal of the mandrel. 2 is a schematic plan view of an exemplary partially formed integrated circuit. Figure 3 is a schematic cross-sectional side view of the integrated circuit formed in the portion of Figure 2 after forming a plurality of pitch enhancement features in and on the substrate. Fig. 4 is a schematic cross-sectional side view showing the integrated circuit formed in the portion of Fig. 3 after an insulating film is formed thereon. Figure 5 is a schematic cross-sectional side view of the integrated circuit formed in the portion of Figure 4 after a hard mask layer is formed thereon. Fig. 6A is a schematic cross-sectional side view of the integrated circuit formed in the portion of Fig. 5 after a plurality of spacers are formed thereon. Fig. 6B is a schematic plan view of the integrated circuit formed in the portion of Fig. 0A. Figure 7 is a schematic cross-sectional side view of the integrated circuit formed in the portion of Figure 6A after a bottom anti-reflective coating ("BARC") is formed thereon. Fig. 8A is a schematic cross-sectional side view of the integrated circuit formed in the portion of Fig. 7 after a second photoresist pattern is formed thereon. Fig. 8B is a schematic plan view of the integrated circuit formed in the portion of Fig. 8A. Figure 9 is a schematic cross-sectional side view of the integrated circuit formed in the portion of Figure 8a after etching the bottom anti-reflective coating. 10A is a schematic view of the integrated circuit formed in the portion of FIG. 9 after the hard mask layer passes through the spacers and the second photoresist pattern; the figure is looped along a spacer and a spacer. A cross section of a vertical straight line cut. FIG. 10B is a schematic view of the integrated circuit formed in the portion of FIG. 9 after the hard mask layer is passed through the spacers and the second photoresist pattern; FIG. 109141.doc -23· 1309437 FIG. 11 is a schematic cross-sectional view of the integrated circuit formed in the portion of FIG. 10A after etching the insulating film and removing the photoresist, the B ARC and the spacers. . Figure 12 is a schematic cross-sectional view showing the integrated circuit formed in the portion of Figure 11 after depositing a conductive material thereon. Figure 13 is a schematic cross-sectional view of the integrated circuit formed in the portion of Figure 12 after performing a chemical mechanical planarization process. The flowchart of Figure 14 illustrates an exemplary process for forming a particular integrated circuit structure of the present invention. Figure 15 is a schematic plan view of an integrated circuit including a spacer loop and a portion of a metal layer. Figure 16 is a schematic cross-sectional view of the integrated circuit formed in the portion of Figure 13 further including an empty contactor between the array region and the peripheral region. Figure 17A is a configuration diagram of a first mask formed by a photolithography process; the first mask defines a plurality of mandrels. Figure 17B is a configuration diagram of a spacer pattern obtained by performing a pitch increment technique on the mandrel of Figure 17A. Fig. 17C is a configuration diagram of an integrated circuit formed by applying a portion formed by a second metal mask to the spacer pattern of Fig. 17B. [Main component symbol description] 10 line 20 Temporary or expandable material layer 30 Substrate 40 Mandrel 109141.doc • 24 - 1309437 50 Spacer material layer 60 Spacer 90 Thickness 100 Integrated circuit 102 Array area 104 Peripheral area 105 Insulator 106 Insulator 108 Substrate 110 Conductive plug 112 Snake prevention layer 114 Insulation film 116 Hard mask layer 118 Spacer 120 Gap 120a Gap 120b Gap 124 Loop end 122 Bottom anti-reflective coating (BARC) 126 Photoresist layer 128 Opening 130 Conductive Material 132 contactor 134 first mask 109141.doc -25- 1309437 136 138 139 140 142 144 146 148 spacer pattern second metal mask contactor spacer loop metal feature metal feature contactor interconnect
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