TWI307897B - Input circuit and method for n-bit prefetch in a semiconductor memory device - Google Patents

Description

1307897 IX. Description of the invention: [Technical field to which the invention pertains] and more particularly to a semiconductor memory device, a data input circuit for a semiconductor memory device [Prior Art] Generally speaking, a semiconductor memory device Perform data pre-fetch operations to increase data access time. The data prefetching operation 1 is a method of internally transmitting data in response to a write command. Usually, data input of semiconductor memory devices

The circuit performs data pre-fetching operations in synchronization with the system and clock mode. The data input circuit responds to the write command and pre-fetches certain input data, that is, 2-bit data, 4-bit data, and 8-bit data. Since the semiconductor memory device is required to operate at a higher speed, the number of bits of the data to be pre-fetched also increases. Double data rate synchronous dynamic random access memory (DDR SDRAM) e^-f material access pre-extraction operation to 4-bit pre-fetch operation '丨currently developed to 8-bit pre-fetch operation 0 data input The circuit typically includes a plurality of + last few circuits, i.e., a number of latches corresponding to the number of bits of data to be prefetched. Figure 1 is a block diagram of the 2-digit pre-fetch data input circuit of the semiconductor sensation in the technology of the first month! The data input circuit comprises: a network private@@ 。 , , 10, which is used for receiving data DQ from an external device; a synchronization control unit 2 〇, which is used to generate a plurality of synchronous control signals DSRP, coronation and kiss room And a synchronization unit 3〇 for synchronizing the rotation of the buffer unit 1G to the plurality of synchronization control signals 112587.doc 1307897 DSRP, DSFP and DSTROB to output the aligned data DIO_OR and DIO_OF. The buffer unit 10 includes a buffer 12 for receiving data from an external device, and a delay unit 14 for delaying the output of the buffer 12 for a predetermined time and providing the delay data to the synchronization unit 30. The synchronization control unit 20 includes a buffer 21 for receiving the data selection communication number DQS and the reference signal VREF, and a driver 22 for receiving the output of the buffer 21 for outputting the first and second synchronous control signals DSRP and | a buffer 24 for receiving the clock signal CLK and the inverted clock signal /CLK; a driver 25 for driving the output of the driver 25 to output an internal clock signal ICLK; and a signal generator 26, It is used to receive the internal clock signal ICLK and the enable signal EN to generate a third synchronous control signal DSTROB. The third synchronous control signal DSTROB is generated by logically combining the internal clock signal ICLK with the enable signal EN. After the 2-bit data is input and aligned in the data input circuit, the aligned 2-bit data is synchronized in the system time > pulse (instant pulse signal CLK). The enable signal EN is generated from a circuit for performing an operation in response to a write command and is then supplied to the signal generator 26. The synchronization unit 30 includes an aligning unit 32 for aligning the output of the buffer unit 10 in response to the first and second synchronization control signals DSRP and DSFP, and a cross-domain unit 36 for aligning the unit 32 The output is synchronized to the third synchronous control signal DSTROB to output the aligned data DIO_OR and DIO OF. 112587.doc • 1307897 Alignment unit 32 includes ·····# left „ 锁存 latch benefit 33, which is used to respond to the first synchronous control signal belly P, latching the output of buffer unit 1〇; second 34, In response to the first _Di brother-synchronous control signal DSFp, latching the output of the first sub-bene; and the third latch & in response to the first control signal DSFP, respectively latching the buffer unit 1Q Output....

The cross-domain unit 36 includes a fourth latch 37 that carefully stores the output of the second latch 34 to output the aligned data, and a fifth latch 38 for The output of the third latch 35 is latched to output the aligned data dio_〇f, wherein the fourth and fifth latches 37 and 38 perform a latch operation in response to the third synchronous control §fl number DSTROB. Figure 2 is a timing diagram of the operation of one of the conventional data input circuits shown in Figure i. The operation buffer unit 10 of the conventional data input circuit will receive the data gauges and 〇F from the external device and output the internal data DIN, as will be described hereinafter with reference to Figs. The data 〇玟 and 01 输入 are respectively input to the buffer unit W t in a state in which the data selection communication number dqS2 is synchronized and the falling timing is synchronized. The data 0R is the first input data that is inserted into the buffer unit 1〇 in response to the first rising transition timing of the data selection communication number DQS. The data is input to the second input data in the buffer unit 1〇 in response to the data strobe §fl indicating the first falling transition timing of the DQS. The synchronization control unit 20 receives the data selection communication number DQS and the reference signal VREF, and generates first and second synchronous control signals DSRp and 112587.doc .1307897 'synchronized by the rising timing and the falling timing of the data selection communication number DQS, respectively. DSFP. The first latch 33 of the aligning unit 32 latches the internal data DIN, that is, the material 0R, in response to the first synchronous control signal DSRP. The second latch 34 is responsive to the second synchronous control signal DSFP to latch the output of the first latch 33. The third latch 35 latches the internal data DIN, that is, the material 0F, in response to the second synchronous control signal DSRF. Gp, the sequentially input data 0R and 0F are latched in parallel at the second latch 34 and the third latch 35, respectively. The synchronization control unit 20 generates a third synchronization control signal DSTROB synchronized with the internal • clock ICLK in response to the active enable signal EN. The enable signal EN takes effect in response to the rising timing of the clock signal CLK at the beginning of the data input, and fails in response to a rising transition timing below the clock signal CLK. The latches 37 and 38 of the cross-domain unit 36, in response to the third synchronous control signal DSTROB, latch the outputs F0_RAF0_F of the latches 34 and 35, respectively, and output the aligned data DIO-OR and DIO_OF, respectively. Since the third synchronous control signal DSTROB is synchronized by the internal clock signal ICLK, the aligned data DIO_OR and DIO-OF are the data aligned with the clock signal CLK. For reference purposes, the term "cross-domain" means the operation of changing a reference signal to a transmitted signal. In the above description, the data selection communication number DQS is changed to the clock signal CLK as a reference signal for transmitting data. In general, in DDR SDRAM, all internal operations in the core region are performed synchronously with the clock signal CLK. Therefore, the data input circuit performs a cross-domain operation to change the data selection communication number DQS to the clock signal CLK, 112587.doc 1307897 ' as a reference signal for the material data. Figure 3 is a block diagram of a prior art pre-fetch data input circuit of a semiconductor memory device of the prior art. j data input circuit includes buffer unit 4 (), synchronous control unit % and the same 'Yan Fanxian. The 4-bit pre-fetch data input circuit has substantially the same configuration as the 2-bit pre-fetch data input circuit shown in FIG. The number of latches arranged in the sync element is greater than the number of latches in the sync unit of Figure i. This is because the sync unit 6 is latched and aligned with the 4-bit data of the serial input. This data is synchronized by the rising timing or falling timing of the data selection communication number DQS. The synchronization control unit 50 generates the first and second synchronization control signals DSRP and DSFP in response to the data selection communication number DQS, and generates a third synchronization control signal DSTROB2 in response to the internal clock signal ICLK. After the latch operation of the latch unit 66, the third sync control signal DSTROB2 is generated by the sync control unit 5A. 4 is a timing diagram showing the operation of one of the data input circuits shown in FIG. The operation of the 4-bit prefetch data input circuit will be described hereinafter with reference to Figs. 3 and 4. The buffer unit 40 receives the data input from the external device, and outputs the internal data DIN 〇'. The synchronization control unit 50 receives the data selection communication number dqS and the reference signal VREF, and generates synchronization by the rising timing and the falling timing of the data selection communication number DQS. The first and second synchronous control signals DSRp^DSFP 〇112587.doc -10- 1307897 The aligning unit 62 sequentially transmits the internal 4-bit data DIN in synchronization with the first and second synchronous control signals DSRP and DSFP ( That is, the first data R, the second data 0F, the third data 1R, and the fourth data 1F are aligned to be aligned into two columns of data R〇_R, F〇_F, 1?1_11, and F1_F. The synchronization control unit 50 receives the clock signals CLK and /CLK and generates a third synchronization control signal dSTr〇b2 in response to the enable signal EN2.

The cross-domain unit 66 latches R〇_R, F0_F, F1_r&f1-F and outputs it as aligned data DIO OR, DIO OF, DI〇 synchronized with the third synchronous control signal DSTR〇B2. —1R^DI〇—1F. Therefore, by the pre-fetch operation of the conventional 4-bit pre-fetch data input circuit shown in FIG. 4, the sequentially input 4-bit data (10) and (4) are 4-bit aligned data m〇-〇R , m〇一〇f, di〇丨han and DIO IF. — If the above information 'data input circuit has the money (4) into two columns of the memory ° first 'data input circuit using the latch to all the bit data: listed as one of the two columns % # #弟弟Bessie, secondly, rearrange the first material into a parallel alignment of the first _杳#jL^ brother-Bei. In order to arrange the serial input, the number of latches in the required clothing is 2N-1+N, and the number is two positive. 2N-1 latches 3| are required for 'the first time, and the thighs are used for the second time. (d) and if there is an increase in the number of data phases _ s ^ for the prefetch operation, there may be more latches. Therefore, I & I need this, the day + west to be used for the larger bit of the pre-fetch operation | technology. 3⁄4,, the data input circuit in the conductor memory device. The body input circuit is 锫 丄 贝 贝 τ τ τ 与 与 与 引起 引起 引起 引起 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造SUMMARY OF THE INVENTION The present invention provides various embodiments of a data input circuit that minimizes the circuit area required for the pre-fetch operation even when the number of data bits in the pre-fetch operation increases. According to a first embodiment of the present invention, there is provided an input circuit for N-bit pre-extraction of one of the semiconductor memory devices, comprising: - a control signal generating unit 70 for responding to a clock signal and a data Selecting a communication number, generating a plurality of control signals, wherein the external input data is synchronized by the data selection communication; and a synchronization unit for aligning the input data to ^ by more than three data alignment operations ^ Bits are aligned in parallel, where N is an integer greater than two. According to a second embodiment of the present invention, an input circuit of a semiconductor memory device is provided, comprising: a control signal generating unit for generating a plurality of alignment control signals in response to the data selection communication number, and responding to a momentary_ The pulse signal generates a plurality of cross-domain control signals, wherein the external input data is synchronized by the data selection communication number; an alignment unit is used to input the ^^ bit by more than two data alignment operations Data alignment is data for parallel alignment; and a cross-domain unit for synchronizing the rotation of the alignment unit with the cross-domain control signal to output N-bit aligned parallel data, where N Is an integer of two or more. According to a second embodiment of the present invention, an input circuit of a semiconductor memory device includes: a control signal generating unit for generating first and second alignments in response to a clock signal and a data selection communication number Control 112587.doc

-12- 1307897 signal and a plurality of cross-domain control signals, wherein the external input data is synchronized by the data selection communication number; an aligning unit is responsive to the first and the second alignment control signals, N-bit input data is aligned to be aligned into two columns of data; and a cross-domain unit is used for two data synchronization operations to align the data aligned by the alignment unit with the plurality of cross-domains The control signal is synchronized to output N-bit aligned data in parallel, where N is an integer of two or more. According to a fourth embodiment of the present invention, an input circuit for a N-bit pre-extraction-semiconductor memory device is provided, comprising: a first data alignment unit for responding to a data selection communication Synchronizing one of the first control signals, aligning and outputting a predetermined number of external ν bit data sequentially input, wherein the Ν bit data input is synchronized by the transition timing of the data selection communication number; a latch unit, In response to a second control signal synchronized to a system clock, latching an output unit of the data aligning unit and a second aligning unit for generating synchronization with the clock of the system And a third control signal, the data aligned by the data alignment unit and the data latched by the latch unit are aligned into the aligned bit data. According to a fifth embodiment of the present invention, there is provided an input circuit for pre-fetching a semiconductor memory device with a bit, comprising: a data alignment sheet = two for a predetermined number of external Ν for aligning and outputting sequential inputs Bit data; a first cross-domain unit for latching an output of one of the data alignment units in response to a first cross-domain control signal; and a second cross-domain unit for responding to a first The second cross-domain control signal, the data aligned by the data alignment unit and the data latched by the first cross-domain unit are latched into a parallel pair of N-bit data of H2587.doc -13·1307897.

According to a sixth embodiment of the present invention, there is provided a method for operating a semiconductor memory device for N-bit pre-fetching, comprising: using a - alignment unit to sequentially input a predetermined one of the external N-bit data The number (four) of the bit data is aligned to the first-difficult element data of the parallel alignment; the first m-bit data is latched into the second data; and the alignment unit aligns the other data in the (four) bit data with Third parallel data; and aligning the second data and the first data into N-dimensional data aligned in parallel. [Embodiment] Hereinafter, an 8-bit pre-fetch data input circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings. Figure 5 is a block diagram showing an 8-bit pre-fetch data input circuit of a semiconductor memory device in accordance with a first embodiment of the present invention. As shown, the data input circuit for operating 8-bit pre-fetching includes a buffer unit 70, a synchronization control unit 80, and a synchronization unit 9. The buffer unit 7G includes a buffer 7 for receiving from an external device. The data DQ, and a delay unit 72, is for delaying the output of the buffer 71 by a predetermined time to output as internal data DIN to the synchronization unit 9A. The synchronization control unit 80 includes a buffer 8! for receiving The data selection communication numbers DQS and /DQS;, the driver 82 for receiving the output of the buffer 8i to output the first and second synchronization control signals DSRp and DSFp; the buffer 83' for receiving the clock signal CLK and /CLK; driver 84, which is used to drive the output of the driver 84, ICLK; and the signal generator 85, which is used as an internal clock signal to receive the internal clock signal 112587.doc -14·1307897; ICLK and enable signal ΕΝ to generate third synchronous control signal DSTROB 4. Synchronization unit 90 includes alignment unit 92, delay unit 94 and cross-domain unit 96 ° Alignment unit 92 aligns internal data DIN into two columns of data Delay unit 94 delays the output of the aligning unit 92 for a predetermined time to output to the delay unit 94. Here, the predetermined time is given to increase the time of the insufficient operating margin, which is selected by the data. The short difference between the transition timing of the communication number DQS and the transition timing of the clock signals CLK and /CLK is in the cross-domain. This difference is referred to as the tDQSS for the DDR SDRAM. The alignment unit 92 includes a total of fifteen locks. The fifteen latches of the aligning unit 92 are arranged to align the first data sequentially input in synchronization with the transition timing of the data selection communication number DQS into the second data aligned in two columns. 94 includes eight delays for respectively delaying the output of the second material of the self-aligned unit 92 to output the third data to the cross-domain unit 96. The cross-domain unit 96 includes eight latches for The latch outputs the third data from the delayed single stomach element 94 to output the 8-bit aligned parallel data DIO-OF, DIO-1F, DIO-2F, DIO_3F, DIO_OR, DIO-1R, DIO_2R and DIO-3R Therefore, the 8-bit pre-fetch data input circuit will be selected with the data. The 8-bit data (ie, OR, OF, 1R, 1F, 2R, 2F, 3R, and 3F) sequentially input by the signal DQS is aligned to the 8-bit aligned parallel data, namely DIO_OF, DI0_1F, DI02F, DIO_3F. , DIO_OR, DIO 1R, DIO 2R, and DIO 3R. 112587.doc -15- 1307897 ; Here, the first and second synchronous control signals DSRP and DSFP are sequentially applied four times in sequence. The third synchronous control signal DSTROB takes effect after the eighth data 3F input data input circuit. 6 is a block diagram showing an 8-bit pre-fetch data input circuit of a semiconductor memory device in accordance with a second embodiment of the present invention. • As shown in FIG. 6, the 8-bit pre-fetch data input circuit includes: a buffer unit. 1〇〇, which is used to receive data DQ from an external device to output as internal data DIN; and a synchronization control unit 200 for Receiving data selection communication number • DQS and /DQS timely pulse signals CLK and /CLK to generate a plurality of control signals DSRP, DSFP, DSTROB2 and DSTROB4; and a synchronization unit for synchronizing the output of the buffer unit 100 to the plurality of Control signals DSRP, DSFP 'DSTROB2 and DSTROB4, the output is 8-bit aligned data, ie DIO-OR, DIO_lR, DIO_2R, DIO_3R, DIO_OF, DI0_1F, DIO_2F and DIO_3F. Here, the synchronization unit includes an alignment unit 300, a first cross-domain unit 400, and a second cross-domain unit 500. The synchronization unit first aligns the internal data DIN into two aligned data, and secondly aligned into four columns of aligned data, and then finally aligned to aligned octets. Parallel data. In detail, the aligning unit 300 aligns the 8-bit serial data output from the buffer unit 100 into the first 4-bit data in four columns in response to the first and second synchronous control signals DSRP and DSFP. The second 4-bit data of the two columns. The first inter-domain unit 400 is latched into the first four bits of the four columns in response to the first cross-domain control signal DSTROB2. After the first cross-domain unit 400 latches the first 4-bit data, the second 4-bit data in two columns is transferred to the delay unit 340 I12587.doc -16 - 1307897; The second cross-domain unit 500 responds to the second cross-domain control signal DSTROB4, and latches the first 4-bit data output from the first cross-domain unit 400 and the second 4-bit data output from the self-aligned unit 300 to output It is the aligned 8-bit side-by-side data, namely DIO_OR, DIO_lR, DIO_2R, DIO_3R, DIO_OF, DIO_lF, DIO_2F and DIO_3F. The aligning unit 300 includes: a latching unit 320 for aligning the selected 4-bit data of the 8-bit data outputted from the buffering unit 100 into two columns of the first 4-bit data. And a delay unit 340 for receiving and delaying the first 4-bit data to output it to the first cross-domain unit 400. The latch unit 320 includes seven latches 321 to 327 (the seven latches 321 to 327 are arranged in two columns), and latches the previous latches in response to the first or second synchronous control signals DSRP and DSFP, respectively. The output. The latches 321 and 323 are latched from the internal data DIN of the buffer unit 100. In detail, the latch 321 latches the internal data DIN in response to the first synchronous control signal DSRP. The latch 322 responds to the output of the second synchronous control signal DSFP latch latch 321 and outputs it to the latch 324. The latch ® 323 latches the internal data DIN in response to the second synchronous control signal DSFP. The latch 324 latches the output of the latch 322 in response to the first synchronous control signal DSRP. The latch 325 latches the output of the latch 323 in response to the first synchronous control signal DSRP. Latch 326 is responsive to the output of second sync control signal DSFP latch latch 324. The latch 327 is responsive to the output of the second synchronous control signal DSFP latch latch 325. That is, the latches 321, 324, and 325 perform latching operations in response to the first synchronous control signal DSRP, respectively. Latches 322, 323, 326, and 327 are responsive to the second synchronous control signal 112587.doc -17-1307897 - DSFP for latching operations, respectively. Delay unit 340 includes four delays 342, 344, 346, and 348. The four delays 342, 344, 346, and 348 delay the outputs of the latches 322, 326, 323, and 327, respectively, for a predetermined time to output them to the first cross-domain unit 400. Since the delay unit 340 has a latch corresponding to the signal transmitted from the latch unit 320, the delay unit 340 can independently delay the output of the data signal from the latch unit 320. The four delay units 342, 344, 346, and 348 use a propagation delay obtained by a plurality of inverters, or an RC delay value obtained by a resistor and a capacitor for delay operation. The first cross-domain unit 400 includes four latches 420, 440, 460, and 480 for latching the outputs of the four delays 342, 344, 346, and 348, respectively, in response to the first cross-domain control signal DSTROB2. The second cross-domain unit 500 includes eight latches 510-580 for responding to the second cross-domain control signal DSTROB4, respectively latching the second four bits output from the four delays 342, 344, 346 and 348. Metadata, and the first 4 bits of data output from the four latches 420, 440, 460, and 480. B. The latches, first cross-domain unit 400, and second cross-domain unit 500 arranged in the aligning unit 300 may be D flip-flops and include a circuit for performing edge triggering operations. The synchronization control unit 200 includes an alignment control unit 220 for generating first and second synchronization control signals DSRP and DSFP synchronized with rising and falling edges of the data selection communication number DQS, and a cross-domain control unit 240, The first and second cross-domain control signals DSTROB2 and DSTROB4 are generated in response to the enable signals EN2 and EN4 and the pulse signals CLK and /CLK. 112587.doc -18·1307897; The alignment control unit 220 includes a buffer 222 for receiving the data selection communication numbers DQS and /DQS, and a driver 224 for receiving the output of the buffer 222 and generating the first and The second synchronous control signals DSRP and DSFP. The cross-domain control unit 240 includes a clock input unit 242 for receiving the clock signal CLK and the inverted clock signal /CLK and generating an internal clock • ICLK; and a cross-domain control signal generating unit 244 for responding The enable signal .EN2 generates a first cross-domain control signal DSTROB2 synchronized with the internal clock ICLK, and a second cross-domain control signal DSTROB4 synchronized with the internal clock ICLK i in response to the enable signal EN4. The clock input unit 242 includes a buffer 242a for receiving the clock signal CLK and the inverted clock signal /CLK, and a driver 242b for receiving the output of the buffer 242a and generating the internal clock ICLK. The cross-domain control signal generating unit 244 includes: a first generating unit 244a for generating a first cross-domain control signal DSTROB2 synchronized with the internal clock ICLK in response to the enable signal EN2; and a second generating unit 244b for In response to the enable signal EN4, a second B-domain control signal DSTROB4 synchronized with the internal clock ICLK is generated. The first generating unit 244a performs a logic operation on the internal clock ICLK and the enable signal EN2 to generate the first cross-domain control signal DSTROB2. The second generating unit 244b performs a logic operation on the internal clock ICLK and the enable signal EN4 to generate a second cross-domain control signal DSTROB4. The enable signals EN2 and EN4 are generated by a control circuit in response to a write command, and the enable signals EN2 and EN4 are asserted and disabled in response to the internal clock signal ICLK. 112587.doc -19· 1307897 • Fig. 7 is a timing chart illustrating the operation of one of the data input circuits shown in Fig. 6. An 8-bit pre-fetch data input circuit according to a second embodiment of the present invention will hereinafter be described with reference to Figs. 6 and 7. Here, 'R' and 'F' in Fig. 7 are abbreviations for distinguishing the data input in synchronization with the rising edge and the falling edge of the data strobe signal DQS. Figure 7 - The natural numbers before 'R' and 'F' indicate the order in which the data is entered. As shown in Fig. 7, first, the data is sequentially input to the input buffer unit i 同步 in synchronization with the rising edge and the falling edge of the data selection communication number DQS. The input buffer 100 receives the external data input and outputs the same data as the internal data DIN. The alignment control unit 220 generates first and second synchronization control signals DSRp and DSFP synchronized with the rising edge and the falling edge of the data selection communication number dqs, respectively. Since the second embodiment of the present invention receives 8-bit data, the first and first synchronous control signals DSRP and DSFP have four transition times, respectively. The latch unit 320 of the aligning unit 300 locks the first 4-bit data of the input 8-bit data into two columns in response to the first and second synchronization control signals DSRP and DSFP. That is, the latch unit 32, in response to the first and second synchronous control signals DSRP and DSFP, latches the sequentially input 4-bit data (ie, OR, OF, 1R, and 1F) into two using the latches 321 to 327. Column. The delay unit 340 delays the data latched by the latches 3 22, 326, 323, and 327 (ie, OR, OF, 1R, and 1F) to output the outputs F〇—R, F1_R, F〇_F, and F1_F to the first A cross-domain unit 400. In addition, when the enable signal EN2 is responded to the input of the fourth data (ie 1F) 112587.doc -20- 1307897

When the sequence is in effect, the cross-domain control unit 240 generates a first cross-domain control signal DSTROPB2 synchronized with the internal clock signal ICLK. The first cross-domain unit 400, in response to the first cross-domain control signal DSTROPB2, latches the outputs F0_R, F1_R, F0_F, and F1_F of the delay unit 340 to output them as outputs D_1R, D_0R, D_1F&D_0F. - Therefore, the sequentially input 4-bit data (i.e., OR, OF, 1R, and 1F) is aligned by the first cross-domain unit 400 into a parallel 4-bit data. While the first 4-bit data of the sequentially input octet data is latched at the first cross-domain unit 400, the latch unit 320 of the aligning unit 300 responds to the first and second synchronous control signals DSRP. And DSFP, the other 4-bit data of the input 8-bit data is latched into two columns. That is, the latch unit 320 latches the sequentially input 4-bit data (ie, 2R, 2F, 3R, and 3F) into two columns using the latches 321 to 327 in response to the first and second synchronous control signals DSRP and DSFP. . Delay unit 340 delays the data latched by latches 322, 326, 323, and 327 (i.e., 2R, 2F, 3R, and 3F) to output them as outputs F0_R, F1_R, FWF1_F. - In addition, when the enable signal EN4 is valid in response to the input timing of the eighth data (i.e., 3F), the cross-domain control unit 240 generates a second cross-domain control signal DSTROPB4 synchronized with the internal clock signal ICLK. The second cross-domain unit 500, in response to the second cross-domain control signal DSTROPB4, latches the outputs D_1R, D_0R, 0_1?, and D_0F of the first cross-domain unit 400 to output them as outputs DI0_1R, DIO_OR, DI0_1F, and DIO_OF, and The outputs F0_R, 112587.doc -21 - 1307897 FLR, F0_F, and F1_F of the latch delay unit 340 are output as outputs DI〇_2F, OIO-3F, DIO-2R, and DIO_3R. Therefore, the octet data (i.e., OR, 〇F, 1R, IF, 2R, 2F, 3R, and 3F) sequentially rotated by the second cross-domain unit 500 is aligned into the octet data of the parallel.

As described above, the 8-bit pre-fetching tribute input circuit according to the second embodiment of the present invention has two inter-domain units 4 and 5, and performs two cross-domain operations. The first cross-domain unit 4 aligns the first 4 bits of the input 8-bit data into aligned 4 bits in synchronization with the reference signal (ie, the first cross-domain control signal DSTROB2). Metadata. The second cross-domain unit 5 同步 is synchronized with the reference signal (ie, the second cross-domain control signal dstr〇b4), and the subsequent 4-bit data in the 8-bit and the first cross-domain unit 400 are input. The aligned 4-bit data is aligned to the aligned parallel 8-bit data. Since the cross-domain operation is performed twice, the number of lock states in the align unit 300 can be reduced. In particular, the 8-bit prefetch data input circuit according to the first embodiment of the present invention has fifteen latches for aligning the 8-bit serial data into two columns of 8-bit data. That is, according to the first aspect of the present invention, the 8-bit pre-length 1 data input circuit has only seven latches' to align the 4-bit serial data into two columns of 4-bit data. The alignment unit uses two cross-domain operations to align only the 4-bit serial data in the input 8-bit data into 4 digits and 歹-bee. Therefore, the eight latches of the input circuit are no longer needed. In addition, in the case of the first operation, the four additional latches of the first-cross-domain unit 400 are used in the cross-domain unit of the embodiment, 112587.doc • 22- 1307897 '420 , 440, 460 and 480. Although these four additional latches are required, the total number of latches required in the 8-bit prefetched data input circuit can be reduced. That is, the total number of latches is changed from the 23 latches in the first embodiment to the 19 latches in the second embodiment. As the total number of latches is reduced, the area of the 8-bit pre-fetch data input circuit can also be reduced. Therefore, the cost of the semiconductor having the 8-bit pre-fetch input circuit can be reduced. ® Although the 8-bit pre-fetch data input circuit is disclosed in the above, various alternatives, modifications, and equivalents may be used. For example, 5' those skilled in the art should understand that the data input circuit for 4-bit pre-fetching, 丨6-bit pre-fetching or 32-bit pre-fetching can be used in any type of semiconductor C memory device, or The number of bits may be modified to properly partition a complete input material, or it may be modified such that the control signal is selected for two or more cross-domain operations. • This application contains the subject matter of Korean Patent Application Nos. 2〇〇5_9〇919 and 2006-26260 (applied to the Korean Patent Office on September 29, 2005 and March 22, 2005, respectively). The entire contents of these patent applications are hereby incorporated by reference. While the invention has been described with respect to the specific embodiments thereof, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional 2-bit pre-fetch data input device of a semiconductor memory device, H2587.doc • 23·1307897; FIG. 2 is a conventional data input circuit shown in FIG. FIG. 3 is a block diagram of a conventional input device for pre-fetching data of a semiconductor memory device; FIG. 4 is a timing chart of operation of one of the data input circuits shown in FIG. 3; FIG. 6 is a block diagram of an 8-bit pre-fetch data input circuit of a semiconductor memory device according to another embodiment of the present invention; FIG. 6 is a block diagram of an 8-bit pre-fetch data input circuit of a semiconductor memory device according to another embodiment of the present invention; FIG. FIG. 7 is a timing diagram showing the operation of one of the data input circuits shown in FIG. 6. [Main component symbol description] 10, 40, 70, 100 buffer unit 12, 21, 24, 71, 81 > buffer 83 ' 222 · , 242a 14, 11, 94 delay unit 20 > 50, 80, 200 synchronization Control unit 12, 25' 82, 84, 224, 242b driver 26 > 85 signal generator 30, 60 > 90 synchronization unit 32 ' 62 ' 92 alignment unit 33 ' 34, 35, 37, 38 > 321 , 322 , 323 , 324 , 325 , 326 · 327 , 420 , 112587.doc • 24· .1307897 440 , > 460 , • 480 , .510 , 520 , 530 , • 540 , .550 , 560 570, 580 36, 96 cross-domain unit 66 ' 320 latch unit 220 alignment control unit 240 cross-domain control unit 242 clock input unit 244 cross-domain control signal generating unit 244a first generating unit 244b second generating unit 300 Alignment unit 340 delay unit 342, 344, 346, 348 delay 400 first cross-domain unit 500 second cross-domain unit 112587.doc 25

Claims (1)

/ D07§9^23982 Patent Application&quot; Chinese Patent Application Substitute Replacement (October 1997) X. Application Patent Park: A bit pre-fetch input circuit for semiconductor memory devices. The input circuit includes ·· The signal generating unit generates a plurality of control signals in response to a clock signal and a data selection communication number, wherein the external data is input in synchronization with the data selection communication number; and a synchronization unit is used for Perform a data alignment operation of at least three Second, to align the input data into N-bit parallel data, ^^ is a positive integer greater than one. 2. If the request item! is in the circuit 'where the synchronization unit performs the data alignment operation five times; at the first time, the N/2 bit pair of the input data: the first one in two columns Aligning the data; at the second time, aligning the first aligned data into the second aligned data in the N/2 column; at the second time, the other N/ of the input data. The 2-bit alignment is the third aligned data in two columns; at the fourth time, the third alignment is aligned: the fourth aligned data in the N/2 column And in the fifth-person day-to-shoulder 'the fourth phase is aligned with #, the material of the material and the material of the first: the material is aligned to the N-bit side by side data. 3. (4) Asking for the input circuit of the user, wherein the synchronization unit comprises: a synchronization unit 'in response to the -first control signal and the material ^: making money' to align the round entry data into the first-pair a second synchronization unit, the first synchronization unit responsive to a third control signal to align the output to the second aligned data; and 112587-971028.doc 1307897 cm ff — ———羊月' 9 repair (more) replacement page—the third synchronization unit, which is used to return to the -four control signal, the first synchronization unit and the second synchronization single open * ^ One of the outputs is aligned for the n-bit side-by-side data. 4. The input circuit of claim 3, wherein the first synchronization unit comprises a latch unit, the heart is responsive to the sequence (4) __ and the second control til number, and the input data is aligned to The first aligned data to output a first to N/2 transmitted data; and a delay unit for delaying the first to the transmitted data and outputting the delayed data To the second synchronization unit. 5. The input circuit of claim 4, wherein the latch unit comprises a plurality of latches arranged in a column, each of the latches responsive to the first control signal or the second control The signal latches one of the outputs of the previous latch, and the two latches of the M, J Tongsi first latch collectively receive the input data. 6. The input circuit of claim 5, wherein the delay unit includes n/2 delays for delaying the f output of the latch unit by a predetermined delay time. An input circuit, such as a month 6, wherein the second synchronization unit includes a latch 9 for latching the N/2 delayed burst outputs in the delay unit, respectively. Avoiding moxibustion 8. If you want to input the input circuit of item 7, _. ^ In the middle of the second synchronization, including N locks ^ for respectively latching the dedicated output of the N/2 delays in the delay unit; § Shifang per ^ ^, μ in the second synchronization unit The output of N/2 latches. The input circuit of the green item 8, wherein the first to the third synchronization unit 112587-971028.doc 1307897, I 1 'the mother latch jh τ^ν — — „ '一— ------- --------- A white is a D flip-flop, or a circuit for performing an edge-triggered operation. 'Inquirer 9's wheeled circuit, where the first to the third synchronization unit _ 5, the output of the plurality of latches is delayed by the plurality of delays arranged in the delay unit with different delay times. The input circuit of claim 10, wherein each of the delay units is delayed Each of the inverters includes a plurality of inverters connected in series. The input circuit of the item 10, wherein each of the delay units includes a resistor and a capacitor. 13. The input circuit of claim 9. The method further includes: buffering the input data for receiving the input data to output the internal data to the first synchronization unit. 4. The input circuit of claim 13, wherein the control signal generating unit comprises: An alignment control signal generating unit for generating an nickname with the data strobe a first control signal synchronized with the rising edge and a second control signal synchronized with a falling edge of the data selection communication number; and a cross-domain control signal generating unit for generating a response to a first enablement m The third control signal that is in effect, and the fourth control signal that is effective in response to the second enable signal. 15. The round-robin circuit of claim 14, wherein the cross-domain control signal generating unit comprises: - input early兀' is responsive to the external clock signal and the inverted external clock signal to generate an internal clock signal; 112587-971028.doc 1307897 - the first signal generating unit uses And the first enable signal to generate the third control signal in response to the internal clock signal; and the first signal generating unit responsive to the internal clock signal and the first enable signal to generate the fourth Control signal. The input circuit of claim 15, wherein the first signal generating unit generates the second control signal by logically combining the internal clock signal with the first enable signal. The input circuit of claim 16, wherein the input unit comprises: a buffer for receiving the clock signal and the inverted clock signal; and a driver for outputting based on one of the buffers And outputting the internal signal to the first signal generating unit and the second signal generating unit. The input circuit of claim 14, wherein the alignment control signal generating unit comprises: a buffering function for receiving the data selection communication number and an inverted data selection communication number; and a driver for using the buffer One of the punch outputs, the first and the second control signal are generated. 19. An input circuit for a semiconductor memory device, the input circuit comprising: a control signal generating unit for generating a plurality of alignment control signals in response to a data selection communication number, and generating a plurality of signals in response to a clock signal Cross-domain control signal, wherein external data is input by synchronizing with the data selection communication number; 112587-971028.doc 1307897, ' . .乂U. ; ...丄乂. i 1 ...-material unit, for Performing a data alignment operation at least once by the plurality of alignment control signals to align n-bit data of the rounded data; and - a cross-domain unit for synchronizing the output of the alignment unit In the cross-domain control signals, to output the N-bit aligned data, ^ is a positive integer greater than -. 20. The input circuit of claim 19, wherein the control signal generating unit comprises: an alignment control unit generating unit for generating synchronization with the data selection communication 5 - ascending timing or - descending timing The plurality of alignment control signals are generated by the cross-domain control signal, and the heart responds to a valid enable signal to generate the plurality of cross-domain control signals synchronized with the clock signal. 21. The requester circuit of claim 2, wherein the enable signal is asserted when the last resource of the n-bit data is entered into the circuit _. 22. The input circuit of claim 19, wherein the cross-domain unit comprises N latches n of the parallel row, for respectively latching the aligning unit in synchronization with the cross-domain control signals These rounds. 23. The input circuit of claim 22, wherein the aligning unit comprises: a plurality of latches for sequentially latching the wheeled data synchronized with at least the selected one of the plurality of alignment control signals; L late single 7L, which is used to delay the individual rounds of the plurality of latches 112587-971028.doc year and month fi more) positive page 1307897 * η μ ) St ^ i 24 · as claimed in claim 22 The circuit, wherein the cross-domain single touch: the spot latch ^ is a -D flip-flop, or - a circuit for performing an edge-triggered operation. 25: The input circuit of Π23, wherein the delay unit comprises a plurality of delays/'d delaying the input of the plurality of latches by different predetermined times. [1} 0 26. The input circuit of claim 25, further comprising: The buffer unit is configured to receive the input data to output internal data into the alignment unit. The input circuit of the item 21, wherein the aligning unit comprises: an aligning unit for synchronizing the output from the control signal to the first - alignment control signal and - The second alignment control signal, the formula 'aligns the internal data into two columns of the first aligned data, and the alignment unit, the poem is synchronized with the third alignment control information alignment data . The 旱 枓 枓 枓 枓 成 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28广广,, the internal data is latched into the first 'aligned negative material to output a first to Ν/2 transmitted data; and a delay unit for delaying the first latch The round of the unit. 29, such as the input circuit of the item 28, wherein the plurality of columns of the plurality of latches are tested, "the needle storage includes each of the latches arranged to latch the latches in response to the 112587-97I028.doc .wv ....-. , - 'ΰί. ·:νκ 1307897 ί, the alignment control signal or the second alignment control signal, latching one of the outputs of the previous latch, and the two columns The first latch receives the internal data. 30. The input circuit of claim 29, wherein the delay unit includes a first to a fourth extension "' for respectively delaying the output of the latch unit A predetermined time 'to output the delay profile to the second alignment unit. I, as in π, the input circuit of the 3G, wherein the second aligning unit includes a first to fourth latch H for closing the delay signal in the third alignment control signal type The output of the first to the fourth extension. ° 32. The input circuit of claim 31, wherein the cross-domain unit includes a latch, and the delay block is latched from the Η Τ _ in synchronization with the cross-domain control signal. . The outputs of the first to the fourth retarder, and the second to the second latching of the fourth to the fourth latch. The round-trip circuit of claim 32 wherein each of the cross-domain cells and each of the first and second aligning cells are a D flip-flop or a circuit for performing an edge-triggered operation. &lt; ”', 34. As in the request item 30, the circuit is crying + &amp; locks several locks after 5 Hz in the early stage » ^ The delay of the delay unit is delayed by time. The input circuit of the female ° month item 34, the farm includes a plurality of strings m delay Zhuozhong mother - delay device 乂 several series connected inverter. Shi November project 34 input circuit, the device includes φ, , A delay in each of the delays - a resistor and a capacitor 112587-971028.doc 1307897 _ &quot;* —*·*· rm I._ • One year Green Advice 37. As requested in Item 36 The input circuit includes: a buffer unit for receiving the underrun to the alignment unit. , Besaki, to input the internal data of the semiconductor memory device into a uniform Intrusion circuit, the turn-in-control signal generating unit, the direct-use circuit includes: a selected communication number, generates a first - a pulse signal and a number of cross-domain _ system ^. an alignment control signal and complex "" Fl ring, in which the external data is input in synchronization with this; In response to the second /./cloth and the second alignment control, the N-bit of the input data is pre-made; and the AA is aligned with the A5 domain. 'It is used to synchronize the aligned data from the aligning unit to a cross-domain control signal by performing a data synchronization operation at least - times to output N-bit aligned parallel data, (4) The input circuit is greater than - 39. The input circuit of claim 38, wherein the control signal generating unit comprises: an alignment control signal generating unit for generating a rising timing and a falling timing with the data selection communication number The first and second alignment control signals are synchronized; and the cross-domain control signal generating unit is configured to generate the plurality of cross-domain control signals synchronized with the clock signal in response to an active enable signal. The input circuit of claim 39, wherein the cross-domain control signal generating unit 112587-971028.doc &quot;ί〇. ' :': two:. ::: n 1307897 - includes: an input unit for use The clock signal and an inverted clock signal Generating an internal clock signal; a first cross-domain control signal generating unit for generating a first cross-domain control signal in response to the first enable signal and the internal clock signal; Responding to - the second generation of a second cross-domain control message A second cross-domain control signal generates a single enable signal and the internal clock signal number. 41. The input circuit of claim 39, wherein the first cross-domain control signal generating unit generates the first cross-domain control signal by logically combining the internal clock signal with the first enable signal. 42. The wheel circuit of claim 41, wherein the wheel circuit comprises: a buffer thief for receiving the clock signal and the inverted clock signal; and a driver for using the buffer One of the outputs generates the internal clock signal, and outputs the (four) clock signal to the first cross-domain control signal generating unit and the second cross-domain control signal generating unit. The input circuit of the monthly requester 41, wherein the alignment control signal generating unit comprises: - a buffer for receiving the data selection communication number and an inverted data selection communication number; and driving the stolen 'based on the buffer The output of the device generates the first and second alignment control signals. 112587-971028.doc </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; And the second alignment control signal, latching the input data into the first aligned data in two columns; and a delay unit for delaying the output of the latch unit. 45. The input circuit of claim 44, wherein (4) the latch unit comprises a plurality of latches arranged in two columns, each of the latches responsive to the first alignment (four) signal or the first: The control signal is aligned, latching one of its pre-latch outputs, and the first latches of the two columns receive the input data. The latch unit includes: in response to the first alignment control signal, in response to the second alignment control signal, outputting to turn it out as the first aligned 1307897 46. The input circuit of claim 45 is a first latch for latching the internal data; and a second latch for latching the data of the first latch;颂存1 is used to respond to the second alignment guard 1 #, 枓 'to turn it out as the second aligned data. A fourth latch for ... The mouth should be in the first alignment control brake neighbor, latching the second latch - round out; exhausting U唬 - fifth latch, basin field, latching the first: lock; In the first alignment control signal, one of the latches is turned out; a sixth latch test, the poor field is used to respond to the second pair of latches of the fourth latch thin Feng control, 〇] out, to output it as the third alignment 112587-971028.doc -10- a data of 1307897; and a seventh latch responsive to the second alignment control signal to latch the fifth lock at $, . . The wheel is turned out to take the fourth aligned asset, such as the one of the requester 46, whose t is not output. In the circuit, wherein the delay unit includes a plurality of delay values delaying the plurality of latches in the aligning unit 48. The input circuit of claim 47, comprising a resistor and a capacitor of each of the delay cells. Delay 49. The round-in circuit of claim 45, wherein the cross-domain unit comprises: a pre-cross-domain unit aligning data aligned from the alignment element for responding to the first cross-domain control signal, The bit data of the output of the unit is output to the PCT; and a primary cross-domain unit is aligned with the data of the pre-cross-domain metric. And the input of the second cross-domain control signal element is outputted into a queue of 50. The input thunder circuit of claim 49, wherein the pre-cross-domain unit comprises: The first pre-cross-domain unit, A is configured to align the first 4-bit data of the dedicated output of the aligning unit with the first cross-domain control signal to align the data into four columns And + 巧 a second pre-cross-domain single, Gan m is used to respond to the first cross-domain control signal, the alignment is single; Fj· 夕# # &amp; D Hai 4 output of the second 4 The bit data is aligned to be aligned into four columns of data. Θ 51. In the input circuit of claim 49, the inner/middle-phase cross-domain unit includes n locks 112587-971028.doc 1307897 牛月ΐ竣便)正米»·::· 存器, in response The output of the second cross-cell is rounded out: aligning the pre-cross-domain to query the aligned data. 52. The input circuit of claim 49, wherein the first pre-cross-domain unit includes a latch for returning to the 钤 ^ ^ 兀 兀 兀 兀 兀 兀 、 、 、 、 、 、 、 该 该 该 该The bit data is aligned to the data aligned into four columns. 53·=:Γ input circuit, where each of the first-pre-cross-domain units is: :...” D is anti-fasting or is used to perform - the edge touches the shoots. The knowledge 54. The semiconductor memory device of the pre-extraction of the bit element includes: the circuit '----data element' responsive to the first control signal generated by the synchronization of the selected communication number Aligning and outputting the predetermined external data in the bit data of the input input, wherein the bit data is input in synchronization with one of the data selection communication numbers, and a μ latch unit is used to respond Generating one of the second control signals in a synchronous-system clock mode to latch the first data aligning unit 1 output; and ~~ a second aligning unit responsive to being synchronized with the system The pulse mode generates a third control signal, and the output of the first data aligning unit and the output of the latch unit are aligned to be aligned in a bit position, wherein Ν is a positive integer greater than one. 55.=Request the input circuit of item 54, in which the returning person is the loser Data scheduled to take effect when the first enable signal to enable one and the second control signal, and the second one back shall enter into force on H2587-971028.doc -12- enabled when the input data of the first Ν Ν bits of information The input circuit of the conductor memory device &gt; 1307897 • The third control signal is enabled by the signal. The input circuit for the pre-fetching of the bit contains: a data aligning unit for aligning and rotating The predetermined data in the external N-bit data of the sequential input; the number-number-domain unit is used to respond to the -the-span control gas Z-storage output from the data aligning unit - the predetermined output Capital a second cross-domain unit for latching the predetermined data outputted from the output of the data aligning unit and the one of the first cross-domain units into a parallel alignment in response to the second cross-domain control N material. The input circuit of claim 56, further comprising: - a cross-domain control signal generating unit for the "cross-domain control signal" that is effective in an external system clock sequence The second cross-domain control signal. 58. The input circuit of claim 57, further comprising: a data alignment control signal generating unit for generating a data alignment signal and a synchronization timing and a falling timing respectively of the selected communication number and a second data alignment signal, wherein the baking aligning unit performs an alignment operation in response to the first and second data alignment signals. The input circuit of the monthly item 58, wherein the cross-domain control signal generating unit comprises: 112587-971028.doc -13- ^ΤΈΓζξ - '-τ year white repair (more) is replacing page j 1307897 an internal clock generation unit The first control signal generating unit is configured to generate the first cross-domain control signal in response to the internal clock and a first enable signal; And a second control signal generating unit responsive to the internal clock and a second enable signal to generate the second cross-domain control signal. 60. The input circuit of claim 59, wherein the first enable signal is enabled when the predetermined material is entered. 61. The input circuit of claim 60, wherein the second enable signal is enabled when the Nth data of the location data is entered. 62. The input circuit of claim 61, wherein the data aligning unit comprises: - a first alignment align it' for aligning the predetermined data for outputting two columns of first aligned data; a second alignment unit for aligning the first aligned data to the second aligned material. 63. The turn-in circuit of claim 62, wherein the first cross-domain unit comprises a plurality of latches corresponding to the number of outputs of the second alignment unit. 64. The input circuit of claim 63, wherein the first alignment early element comprises a plurality of delays corresponding to the number of bits of the first aligned data. 5. The input circuit of claim 64, wherein the cross-domain includes an amount corresponding to the second alignment unit, the number of the collars and the round of the first cross-domain unit The number of multiple latches. An operation method for a semi-conductor 6-conductor device for pre-fetching of a bit element, the method comprising: U2587'97l028.doc 1307897 1^* ^ '1; - ordering the external N-bit of the predetermined order input Yuan Zi isr ^ ^ 穴 π w eight &lt; external N pay; shoot the predetermined Μ bit data, ΙΝ '^ 辎 six points may be a bit of a parallel collocation data; latch the first Μ bit data, Bessie Taking the second data by rotation; by using the aligning unit, the remaining 枓 in the Ν Ν 资料 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出 输出嗲" ', HX second tribute, to output the aligned Ν position 兀 data. 彳10&lt; 67. The method of claim 66, wherein the reading the pre-location data comprises: aligning the predetermined Μ The bit data is outputted into two columns of data; and the data aligned in two columns is aligned to output the first-aligned bit data aligned in parallel. The method of Shiming seeking 67 is to synchronize In the __ data selection communication number mode is generated to align the first Μ Μ bit data, the f material selection communication number has a corresponding One of the N-bit data into one of the transition 69. The timing "of 68 May seeking entry method, wherein in response to - the first control signal in synchronization with the pulse of 'the second information is a latch system. 70. The method of claim 68, wherein the N-bit data is aligned in response to a second control signal _ synchronized to a system clock. 112587-971028.doc -15-