TWI307478B - Method for scheduling instructions for clustered digital signal processors and method for allocating registers using the same - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method for a clustered digital processor processor, in particular with respect to one A method of clustering digital signal processor scheduling instructions for a plurality of registered register files. [Prior Art] Most computers contain a form of high-performance data storage element called a scratchpad that is effectively used to achieve high performance during runtime. The process of selecting a language component to configure an instruction to a scratchpad and using the language component to move the data is called a "scratchpad configuration." The scratchpad configuration has a major impact on the final quality and performance of the code. Poor configuration can make the code lengthy and run-time less efficient. However, finding the "computer languages" 苐 4,571,678 "temporary 5 solution has proven to be computationally difficult to handle. A number of methods for register configuration have been disclosed. For example, ChaiHn et al., "Computer Language Volume 6, pages 47-57, and US patents.

The scratchpad configuration method for graphics coloring. Method of determination,

104278.doc Although the prior art towel can find a good solution for the scratchpad configuration algorithm, but because of *斩 left 5? SB I Α β. ‘1307478 processor, it will affect the processing noise. SUMMARY OF THE INVENTION The object of the present invention is to provide a method for cluster scheduling and register configuration, the digital processor refers to a temporary storage H file with access restrictions. 5 ❹ ❹ 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 丛 丛 丛 丛 丛 丛 丛 丛The functional unit and a first group of accesses shared by the functional unit having at least two functions: a temporary storage and a method of scheduling by the ^ instruction include the following steps: checking execution of the __ instruction Whether it is required from the first register file -.疋., Read the data in the early morning and the second early morning; and if the result of the check is yes, then sigh 巧 巧 巧 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Unit. The early element is transferred to the second. In addition, the method further includes the steps of: generating an additional virtual (10) (four) register, the virtual register is assigned to the first half of the first register slot... receiving The tribute transferred from the first unit of the first register slot case, and scheduling the instruction after the rewriting instruction. Further, the method may optionally include the following steps: checking whether there is an executable copy instruction The previous (pri〇r) operation cycle—a—and if there is a available cut operation cycle, schedules the overwrite instruction for the previous operation cycle. 104278.doc * 6 - l3〇7478 The method may include the following steps: Checking whether the two functional units need to access the first temporary register file during the operation cycle; and if the check result is yes, scheduling one of the two functional units to be accessed before the T3 functional unit according to a predetermined priority order The first Register file, the system according to a predetermined priority order depending on the type of the operand.

- In addition, the method may comprise the steps of: checking whether execution of an instruction = from the first cluster and a second cluster access data; if the result of the check is, J generates a replication instruction to extract data from the first cluster Transfer to the ~~ cluster; and schedule the instruction after the replication instruction. In addition, in addition to the first-temporary case, the cluster further includes a second register file of the connection to the function unit, and a third register file connected to the other function list 70. The invention also discloses a method for registering a temporary register, which comprises the following steps: generating a plurality of instructions from a program mother; assigning a plurality of virtual registers to the second file, the second register And the third register slot case to create - initial register file assignment (register file sS^ment 'RFA) map' - perform a scheduling process to calculate a first operation for the instruction Cycle; Execution - Simulated Annealing (4) Also (4) (10) Position (4) S A) Processing to correct the temporary storage number (Shanghai) (4)... and configuring the virtual register to the temporary register file and the first according to the register file 2 Three registers file. The medium fire processing includes the following steps: the operation of the circle is assigned in the register file; the scheduling process is performed to calculate a cycle for the instruction (four)'·Check whether the second operation cycle is smaller than the first operation 104278 .doc 1307478 The cycle; and if the result of the check is yes, then the change in the scratchpad file assignment map is maintained. [Embodiment] FIG. 1 illustrates the architecture of a Parallel Architecture Core (PAC) digital signal processor 10. The PAC digital signal processor 10 has a five-instruction (five-way is sue) very long instruction word (VLIW), which includes two arithmetic units (ALU) 20, two A load/store unit (LSU) 30 and a single scalar unit (B unit) 40. These LSUs 30 and ALUs 20 are arranged in two clusters 12A and 12B, each of which contains a pair of two functional unit (FU) types. The B unit (BU) 40 is independently configured and is responsible for branch operations, which are also capable of performing simple load/store and address arithmetic. The first register file (D1, D2, D3, and D4) 22 serves as a communication bridge between the clusters 12A and 12B. Only the BU 40 can access all of the first scratchpad files 22, and can perform a write operation across the clusters 12A and 12B. The second register file (Al, A2) 14, the third register file (AC1, AC2) 16 and the fourth register ' file (R) 18 are directly attached to the LSU 30, the ALU 20, respectively. And the *BU 40 is a private register that can only be accessed by the LSU 30, the ALU 20, and the BU 40, respectively. In particular, the first register file 22 uses a so-called "ping-pong" scratchpad file design in addition to spanning the two clusters 12A and 12B, which can achieve a reduction in power consumption. .

The PAC digital signal processor 10 is characterized in that it is a highly partitioned scratchpad file design, wherein each of the clusters 12A, 12B 104278.doc 1307478 in the architecture contains the first temporary storage including two units. The file file 22, the second register file 14 and the third register file 16, the second register file 14 and the first register file 16 are directly connected to the Lsu 3 and The alu 2 〇. Each of the first-storage files 22 has only a single set of access ports shared by the soup and the ALU 20. In particular, in each of the clusters μ' and 12B, each -VLIW contains control access to the first-storage file, 22 and the two functional units (FU, ie, the ALU2G and the LSU3G) At least two instructions and two bit positions are switched between φ. Therefore, in each operation cycle (〇Perati〇Cycle), each of the FUs can only access the dedicated first register broadcast 22 that is assigned by each instruction; two different ones to a single one The simultaneous access of the first register file 22 is mutually exclusive. Of course, the basic principle of this design is to reduce the number of scratchpad files to avoid slow access speed and high power consumption of a unified scratchpad file, but at the expense of an irregular architecture. With this design, the cross-interference between the scratchpad configuration and the instruction schedule is substantially increased, raising the typical phase ordering problem in the compiled code generation. Not only does the cluster design make the scratchpad cross-cluster access an additional problem, but the switching access nature of the "ping-pong," scratchpad file (ie, the first scratchpad file 22) also causes the scratchpad* to be assigned and The details of the instruction schedule are highly dependent on each other. For example, the following new code sequence shifts two constants into two virtual registers TN1 and ΤΝ2: mov TNI, 1 mov TN2, 2 Only when TN1 and TN2 are assigned to When the registers from different first register files 22 are different, the two instructions can be scheduled in parallel; if tni and 104278.doc • 1307478 TN2 are assigned to the same first register file Then, it can only be scheduled and executed in order. The solution of the present invention is to add a new pre-register configuration command by a optimization technique called simulated annealing technology (pre-stage) -register allocation instruction-scheduling phase) - Figure 2 through Figure 13 illustrate a C-bit, signal processor 10 scheduling instruction for executing the following C language code program # (pr〇Cedure) in accordance with one embodiment of the present invention. Method. First, as shown in Figure 2 and Figure 3. It is shown separately that these c language code programs are translated into a pseudo operation (pseud〇_〇perati〇n) form and a dependency graph. A total of 20 instructions from 1〇1 to i2〇 will be It is executed to complete the operations of these c language code programs. As shown in Fig. 4, an initial register file assignment (RFA) map is randomly generated. The left line tn3 to TN14 in the RFA diagram indicates The virtual scratchpad, and m, ai, etc. in the right row represent the physical scratchpad file in the PAC digital signal processor 1 。 int foo(int a, int b) { int c = a + b; a = (c » 2) - a * b; return a + c &〇xff; } Referring to Figure 5, the first three instructions 1〇1, old and i〇3 are directly scheduled in the period '' but then two The instructions 1〇4, 1〇5, and 1〇6 are directly scheduled because the unit D1 of the first register 22 in the cluster 12A has been used by the 104278.doc '1307478 LSU1 to execute the instruction 1〇 4. In other words, only the instruction "iw TN3, 0, 104 and 105 is scheduled in cycle 1, and the instruction ι〇6 "m〇vu TNI4, $0 is not scheduled in cycle 1 But can be scheduled in a later cycle 2, because the operand "loading" in the instruction 104, (lw) is designed to have an operand "moving instruction" in the instruction 106, (Melon's ^ higher priority. The method checks whether the two functional units (ALln and LSU1) need to access the first temporary register file 22 in the same operation cycle, and the root

Accessing the first register file by scheduling one of the two functional units (LSU1 30) before the other functional units (ALU1 20) according to a predetermined priority order based on the type of operation and the critical path status for scheduling twenty two. In particular, the instruction 104 1 105 takes three cycles to complete because the word is loaded from the memory. The operation element "m〇vih," in the finger ♦ 1〇3 is used to move an instruction in the high-order level of the vuw containing at least two instructions, and the operation element in the instruction 1〇6 is used in the movi.r Another instruction in the lower bit level of shifting _vuw. Referring to FIG. 6 and FIG. 7, another instruction 1〇7 “_τΝ7, complete, schedule 'but it is impossible' is because the unit D1 and the cluster 12β of the first broadcast 22 in the cluster 12Α The first register file Μ =: 3 cannot be accessed at the same time, because the m and the Μ unit are located in different clusters. This method enumerates the use of ^ in the unit (1) and the unit to transfer data between the meta-inserts into the eve I & - and assign it to two; I /. Generate a virtual register. The value of the cluster 12 of the first - register file 22 period 22 is transmitted via the local operation and via the previous cycle 5 (4) Sang Zuo was received by her order, and TN5 and 104278.doc -11 - 1307478 have equal values in the scratchpad files m and m. After using 鸠 to replace TN5, the instruction 107 is scheduled in the cycle. In 8, only access (1), not D1 and D3, is not allowed at the same time. The latter is not allowed.

In other words, the method checks whether execution of the instruction 1G7 requires access to data from the cluster UA and the cluster 12B, a generate-rewrite instruction to transfer data from the cluster 12B to the cluster, and to schedule the overwrite instruction The instruction 1G7 is scheduled in cycle 8 after cycle 5. In particular, the method checks if there is a previous operational cycle available to perform a rewrite instruction consisting of "" and "W," by the operand; and the rewrite instruction is scheduled for the previous operational cycle 5t. Similarly, generating Another virtual register τΝ15 and assigned to unit D3, the value of TN3 + is transmitted via the _ operation and received in TN15 via the bdr operation in cycle 4, and Tm5 and TN3 have in register file D1AD3 An equal value. This means that one of the TN3 operands can be replaced by TN15 and the instruction 109 is scheduled in cycle 7 after replacing TN3 with TN15. Further, as shown in FIG.

After the replacement period is used using TN15, the instruction 1〇8 is also scheduled in the period 8. Referring to Figure 9, the instructions 118 and 11 are scheduled in cycle 9, and cycle 10 is working because the command 11 〇 "fmulus TN11, TNU" (TN5 is multiplied by ΤΝ11, and the multiplied value is stored in ΤΝ11) One cycle of latency. The instruction lu is scheduled in the period u. Subsequently, as shown in Figures 1 and 11, instructions 112, 113, 114, 11 5 and 116 are sequentially arranged in cycles 12, 13, 14, 16 and 17. Referring to Figure 12, the instruction 1 P "sub TN12, TN8, TN9" (TN8 minus 104278.doc -12-1307478 TN9, and the subtraction value stored in TN12) is scheduled. However, TN8 is assigned to unit D1 in the cluster 12, and ΤΝ9 and ΤΝ12 are assigned to unit D4 in the cluster 12, meaning that the data sources are in different clusters. A virtual scratchpad 产生 17 is generated and selectively assigned to cells D3 and D4 or the third scratchpad file (AC2) 16 of the first scratchpad file 22. It is not possible to assign this unit D3 to TN17 because it will collide with the D4 (ping-pong constraint). This unit D4 is very suitable, and although AC2 will require additional rewriting operations, it is also possible. Assuming that TN1 7 is assigned to the unit D4, and the value in TN8 is transmitted by the bdt operation and received by the bdr operation in the previous cycle 1N in TN17, the instruction 117 is scheduled to cycle 18 after replacing tn8 by TNn. in. Subsequently, the instruction 119 "add ΤΝ13, ΤΝ7 ΤΝ12" (ΤΝ7 is added to ΤΝ12, and the added value is stored in TN13) is scheduled. However, tni2 is assigned to the unit D4 in the cluster 12, and ΤΝ7 and ΤΝ13 are assigned to the units D1 and D2 in the cluster 12A, meaning that the data sources are located in different clusters. The generate-virtual register is then assigned to the di, the value in tni2 is polled by the bdt operation and received by TN18 from the previous operation in the previous period i9, and the HQ is commanded after the replacement of tni2 by TN18 Scheduled in cycle 22. Referring to Figure 13, the final instruction 120 stores the results of the (AND) logical operation of the compute ΤΝ13 and TN14 in the virtual register assigned to the m. However, N13 and TN14 are assigned to the D2 and m respectively, and the direct command of the instruction is impossible because it will be a conflict (insurance constraint). Generating a virtual memory TN19 and assigning it to the D2, transferring the value in 懦4 to 104278.doc -13· 1307478 the τΝ19 and scheduling the instruction 12〇 in the periodic gate method to check whether the execution of the instruction 120 is Lu Zhi, the party must first read from the first-storage file 22:::-early (four) 2) and the second unit (m) read the data production order ("by ALIH 20 in cycle 22 The first unit = the state element (D1) from the first-storage slot 22, and the instruction is scheduled in the cycle 23 after the rewrite instruction is queued #一第一单19Λ 22. Therefore, A total of 23 cycles, insert 9

Rewrite the knowledge and generate 5 new virtual registers. 14 and 15 illustrate a flow chart of a method for configuring a scratchpad in accordance with an embodiment of the present invention. First, the present invention performs a step si 〇 2: randomly establishes an initial register file assignment and records the assignment in a register file assignment (RFA) map, which is randomly assigned from the code shown in FIG. Per-virtual scratchpad. The present invention then performs a step si〇4: performing a modified list scheduling of instructions, meaning that the operation is performed

The processing of the schedule shown in Figs. 5 to 13 is performed, and a variable (6) is set for the total schedule length in the calculated period. Subsequently, the present invention performs a step S106 of setting an initial value of a threshold, an energy, and a probability test (p-test) for a simulated annealing (SA) process, wherein the energy The initial value is greater than the initial value of the threshold and 〇< p_test <1. The present invention then proceeds to a step S108 of performing a simulated annealing process to adjust the value of the energy, the schedjen and the RFA map, and then performing a step snn to check if the value of the energy is greater than the threshold. If the value of the energy is greater than the threshold value, the present invention returns to perform the simulated annealing process to adjust the amount of energy 104278.doc -14 - 1307478, the sched-len and the step of the RFA diagram sl8; another In the aspect, if the value of the energy is not greater than the threshold, the present invention performs a step such as: retaining the final schedule and the RFA map as a round-out result. Subsequently, the present invention proceeds to step S132: formally configure the hardware register 1 according to the RFA map, ie, assign all of the virtual registers TN3 to 9 to the hardware register file 22 of the processor 10. 14, 14 and 16. The SA process in the reference step discussion is divided into several sub-steps. The SA process first performs a step S112 of randomly selecting a virtual scratchpad and assigning it to one of the different scratchpad slots in the processor 10 to cause at least one change in the tender map. According to the new RFA assignment change, the execution - step "Μ to re-edit the list schedule (meaning to perform a second schedule processing) and set a new_schedjen to the number of new cycles of the total schedule length. Subsequently, Step S116 is performed to check whether new_sched Jen (the operation period of the second scheduling process) is smaller than schedJen (the operation period of the first scheduling process), and if yes, perform a step S118 to reduce the energy, and sched- It is set to new_schedjen, and the change of the new RFA map is maintained. Otherwise, a step S120 is performed to generate a random number R between 1 and 1. Subsequently, a step S122 is performed to check if R is greater than p-coffee. If R is greater than p—[if, then perform a step S124 to reduce the energy by 1, set sched_len to newjched-len, and keep the new RFA map changed' and then return to step siio. Otherwise, perform a step S126. The energy is increased and the change of the new RFA map is restored' and then returned to the step su〇e. The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still be based on the present invention. The invention is not limited to the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should not be limited to those disclosed in the embodiments, but should include various alternatives to the present invention. And the modifications are covered by the following patent application. [Simplified Schematic] FIG. 1 illustrates the architecture of a parallel architecture core (PAC) digital signal processor; FIGS. 2 through 13 illustrate an embodiment of the present invention. A method for scheduling an instruction of a pAc digital signal processor; and FIGS. 14 and 15 are flowcharts illustrating a method for register configuration according to an embodiment of the present invention. [Description of main component symbols] 12A cluster 14 second Archive file 18 fourth register file 22 first register file 40 scalar unit 10 PAC digital signal processor 12B cluster 16 third register file 20 arithmetic unit 30 load / storage unit

TN3, TN4, TN5, TN6, TN7, TN8, TN9, TN10, TN11, TN12, TN13, TN14 virtual registers 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, m, 112 , 113, 114, 115, 116, 117, 118, 119, 120 instructions S102, S104, S106, S108, S110, S112, S114, S116, S118, S120, S122, S124, S126, S130, S132, step 104278.doc -16-

Claims (1)

1307478 Apparel patent scope: The instruction scheduling method of the packet digital signal processor, the processor = complex; a cluster, the per-cluster includes at least two functional units and one has a first unit, a second unit; And the first register file of the early group access shared by the functional units, the method comprising the following steps: checking whether executing an instruction requires a self-reservation-n object-scratch register The first case of the Tan case and the second unit read the data; if the result of the check is yes, a temporary copying command is generated to transfer the data from the first unit of the temporary file to the first Two units; and scheduling the 3H instruction after the rewriting instruction. The instruction sequence of the clustered digital signal processor of the 2. item includes the following steps: checking whether the two functional units need to temporarily store the n-slot; and if the material is to be accessed, the result of the check is yes. According to a ^ # ^ explosion pre-order priority, one of the two power moons is scheduled in another - knife file. The first temporary storage device 3 is accessed as early as 70. According to the industry 隹+# a one-t method of the request item 1, the D-group digital signal is judged to include the following steps: - Whether the previous operation cycle is achievable if the result Α θ a 仃 the rewrite instruction; and the instruction. If it is 疋' then schedule the overwrite in the previous operation cycle. 4. According to the request item industry method, ... the f-type digital signal processor's instruction schedule party accepts the mother a cluster of another white red wall and a temporary storage test; A temporary file and a third temporary file, and the method further comprises the following steps: 104278.doc • 17-