TWI305920B - Memory module for improving shock resistance - Google Patents

Memory module for improving shock resistance Download PDF

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Publication number
TWI305920B
TWI305920B TW95140634A TW95140634A TWI305920B TW I305920 B TWI305920 B TW I305920B TW 95140634 A TW95140634 A TW 95140634A TW 95140634 A TW95140634 A TW 95140634A TW I305920 B TWI305920 B TW I305920B
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Taiwan
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memory module
circuit board
printed circuit
memory
stress absorbing
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TW95140634A
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Chinese (zh)
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TW200822130A (en
Inventor
Wen Jeng Fan
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Powertech Technology Inc
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Description

1305920 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種記憶體模組,特別係有關於—種加 強抗震性之記憶體模組。 【先前技術】 在電腦主機、筆記型電腦等電子產品中,記 關鍵零組件,可重複插拔至主機板之記憶體插槽,以供電 腦系統之運算使用。在攜帶、搬運與更換的過程,記憶體模 組會有不慎掉落至地面之可能,然目前的記憶體模組不甚耐 摔’常會有故障損壞的情形。 如第1圖所示,一種習知記憶體模組1〇〇係包含一多層 印刷電路板110以及複數個記憶體封裝件12〇。該多層印刷 電路板m係具有兩較長側lu與兩較短側112,該些記憶 體封裝件12G係設置於該多層印刷電路板UG。該多層印刷 電路板110之-較長们11係設有複數個金手指113,且該 兩李父紐側112各形成有至少—圓狐形扣槽114,以能電性接 觸並結合固定至記憶體插槽。為相習知記憶體模組⑽之 时摔抗震性’會進行-掉落試驗(drGp test)。如第2圖所示, 習知記憶體模Μ⑽設定於一預定高度H,如5〇公分或_ 公分,並以不同角度呈自由落體落下並撞擊到水泥地面. 之後檢測將經衝擊試驗之後的記憶體模組⑽是否功能仍是 正常。然而目前記憶體模組100已知娜不良,不易 衝擊4驗,經研究發現是在該印刷電路板iiq與該些記憶體 封褒件120之接合界面發生斷裂,導致電性斷路。‘ _ 1305920 如第3圖所示,通常該些記憶體封裝件12〇係可為球栅 陣列式(BGA)封裝而包含有複數個銲球丨2丨,其係接合至其 基板之球墊122且不被一防銲層123覆蓋。此外,該多層印 刷電路板11〇係可設有複數個接球墊115且外露於其表面防 銲層Π6,以供該些銲球121接合。當自由落體落下時撞擊 到該印刷電路11G的應力會傳導至該些記憶體封裝件 ⑽’造成銲球121在„ 122或/與鲜们21在接球塾ιΐ51305920 IX. Description of the Invention: [Technical Field] The present invention relates to a memory module, and more particularly to a memory module for enhancing shock resistance. [Prior Art] In electronic products such as computer mainframes and notebook computers, key components are recorded and can be repeatedly inserted and inserted into the memory slot of the motherboard to power the brain system. During the process of carrying, carrying and replacing, the memory model group may be accidentally dropped to the ground, but the current memory module is not very resistant to falling. As shown in Fig. 1, a conventional memory module 1 includes a multilayer printed circuit board 110 and a plurality of memory packages 12A. The multilayer printed circuit board m has two longer sides lu and two shorter sides 112, and the memory packages 12G are disposed on the multilayer printed circuit board UG. The plurality of gold fingers 113 of the plurality of printed circuit boards 110 are provided with a plurality of gold fingers 113, and the two male parent sides 112 are each formed with at least a rounded fox-shaped buckle groove 114 for electrical contact and bonding to the same. Memory slot. In order to know the memory module (10), the shock resistance is measured by the drGp test. As shown in Fig. 2, the conventional memory module (10) is set at a predetermined height H, such as 5 〇 cm or _ cm, and falls freely at different angles and hits the concrete floor. After the test, the impact test is performed. Whether the memory module (10) is still functioning normally. However, at present, the memory module 100 is known to be poor and difficult to impact. It has been found that the interface between the printed circuit board iiq and the memory package member 120 is broken, resulting in an electrical disconnection. ' _ 1305920 As shown in FIG. 3 , generally, the memory package 12 can be a ball grid array (BGA) package and includes a plurality of solder balls 丨 2 丨 which are bonded to the substrate of the ball pad 122 is not covered by a solder mask layer 123. In addition, the multi-layer printed circuit board 11 can be provided with a plurality of ball pads 115 and exposed to the surface solder resist layer 6 for bonding the solder balls 121. The stress striking the printed circuit 11G when the free fall falls is conducted to the memory packages (10)' causing the solder balls 121 to be at 126 or/and the fresh 21 at the ball 塾ιΐ5

之銲接界面產生斷裂縫124或/與125,使得整個記憶體模组 產品無法運作。 【發明内容】 本發明之主要目的係在於提供一種加強抗震性之記憶體 模組,利用應力吸收槽孔使印刷電路板能緩衝衝擊力,防止 記憶體模組在摔㈣電輯料致產品失效之問題。 本發明的目的及姐、、表甘4士,^ 、/、技術問題是採用以下技術方案 實現的。依據本發明,一種纪愔 種。己隐體模組主要包含一多層印 電路板以及複數個記憶體封裳 ^多層印刷電路板係概呈 個:二 與兩較短側,其中-較長側係設有複數 個應力吸收槽孔·記恃體^至少一圓弧形扣槽與複數 路板之-表面。—⑽體封裝件錢置於料層印刷電 本發明的目的及解決其 進一步實現。 技術問題還可採用 以下技術措施The solder interface creates a crack 124 or/and 125 that renders the entire memory module product inoperable. SUMMARY OF THE INVENTION The main object of the present invention is to provide a memory module that enhances shock resistance, and uses a stress absorbing slot to enable a printed circuit board to buffer impact force and prevent a memory module from failing due to falling (four) electric materials. The problem. The object of the present invention and the technical problems of the sisters, the singers, the singers, and the technical problems are achieved by the following technical solutions. According to the invention, a species is known. The hidden body module mainly comprises a multi-layer printed circuit board and a plurality of memory packs, and the multi-layer printed circuit board system has two profiles: two and two shorter sides, wherein the longer side is provided with a plurality of stress absorbing grooves. The hole and the body of the body are at least one arc-shaped buckle groove and the surface of the plurality of road plates. - (10) Body Package Money Placed on the Layer Printed Power The purpose of the present invention and its further implementation. The following technical measures can also be used for technical problems.

在前述的記憶體模組中 列式(BGA)封裝而包含有 ’該些記憶體封裴件係 複數個銲球。 可為球栅 1305920 在前述的記憶體模組中,該多層印刷電路板係可設有複 數個接球墊’以供接合該些銲球。 在前述的記憶體模組中,該些接球墊係可為非銲罩界定 墊。 在前述的記憶體模組中,該些應力吸收槽孔係可為長條 形。 在前述的記憶體模組中,在同一較短側之該些應力吸收 槽孔係可為直線排列。 ® 在前述的記憶體模組中,該多層印刷電路板於遠離該些 金手指之另一較長側係另形成有複數個應力吸收槽孔。 在前述的記憶體模組中,該些位於較長侧之應力吸收槽 孔係可為直線排列。 在前述的記憶體模組中,該記憶體模組係可為雙直列記 憶體模組(DIMM,Dual In-Line Memory Module)。 在前述的記憶體模組中,部分之該些記憶體封裝件係可 φ 設置於該多層印刷電路板之另一表面。 【實施方式】 依據本發明之第一具體實施例’揭示一種加強抗震 性之記憶體模組。如第4及5圖所示’該記憶體模組2〇〇主 要包含一多層印刷電路板21〇以及複數個記憶體封裝件 220 ’另可包含適當數量之電容電阻等被動元件(圖未繪出)。 該多層印刷電路板210係包含多層線路層且為硬質。該 多層印刷電路板210係概呈矩形而具有兩較長側211與兩較 短側212,其中一較長側211係設有複數個金手指213,以 • 1305920 供插接至電腦或筆記型電腦主機板之記憶體插槽(圖未繪 出)並且孩兩較短側212各形成有至少一圓弧形扣槽2 j 4 . 與複數個應力吸收槽孔2!5。其中,該些圓弧形扣槽214係 可供記憶體插槽之兩側扣件加以扣接,以使該記憶體模組 200固定在對應之記憶體插槽而為不可脫出❶該些應力吸收 槽孔215係可為長條形或其它可吸震抗震之形狀。此外,該 多層印刷電路板210係具有一上表面216與一下表面217。 在本實施例中,該記憶體模組200係可為適用於筆記型電腦 之小型雙直列s己憶體模組(S〇_DIMM,Small Outline Dual In-Line Memory Module),在該上表面216與該下表面217 之同一側邊各形成有複數個雙面獨立之金手指213。 该些記憶體封裝件22〇係設置於該多層印刷電路板2丄〇 之一表面,例如可設置於該多層印刷電路板21〇之上表面 216或下表面217,或是上下表面216與217皆設置有記憶 體封裝件220。如第5圖所示,部分之該些記憶體封裝件22〇 φ 係可設置於該多層印刷電路板21 0之下表面2 1 7。再如第5 圖所示,在本實施例中,該些記憶體封裝件220係可為球栅 陣列式(BGA,Ball Grid Array)封裝而包含有複數個辉球 221。該些記憶體封裝件220之封裝架構係可為微間距球柵 陣列封裝(fine pitch BGA) ’或可稱之為窗口型球栅陣列封梦 (window BGA) ’其内封設有一記憶體晶片222,如動態隨機 存取記憶體之積體電路。每一記憶體封襞件220可另包含— 供電性訊號轉接之基板223、複數個供内部電性互連之鲜線 224與一電絕緣性之封膠體225。該晶片222係以—黏晶層 .1305920 226貼設於基板223上’但該晶片222之銲墊227係不可被 該基板223遮蓋’利用該些銲線224將該晶片222電性連接 至該基板223 ’並以該封膠體225密封該晶片222與該些銲 線224。而該些銲球221則接合在該基板223之另一表面之 球墊228。該些球墊228係外露於該基板223同一表面之防 銲層229。通常該些球墊228可為銲罩界定墊(solder MaskIn the above-described memory module, a BGA package includes 'the memory package's plurality of solder balls. It can be a ball grid 1305920. In the aforementioned memory module, the multilayer printed circuit board can be provided with a plurality of ball pads </ RTI> for engaging the solder balls. In the aforementioned memory module, the ball pads may be non-welded cover defining pads. In the foregoing memory module, the stress absorbing slots may be elongated. In the above memory module, the stress absorbing slots on the same shorter side may be arranged in a straight line. In the aforementioned memory module, the multilayer printed circuit board is formed with a plurality of stress absorbing slots on the other longer side away from the gold fingers. In the foregoing memory module, the stress absorbing cell holes on the longer side may be arranged in a straight line. In the foregoing memory module, the memory module can be a dual in-line memory module (DIMM). In the foregoing memory module, a portion of the memory packages are φ configurable on the other surface of the multilayer printed circuit board. [Embodiment] A memory module for enhancing vibration resistance is disclosed in accordance with a first embodiment of the present invention. As shown in FIGS. 4 and 5, the memory module 2 〇〇 mainly includes a multilayer printed circuit board 21 〇 and a plurality of memory packages 220 ′, and may also include a passive component such as a suitable number of capacitor resistors. Draw). The multilayer printed circuit board 210 comprises a plurality of wiring layers and is rigid. The multilayer printed circuit board 210 has a rectangular shape and has two longer sides 211 and two shorter sides 212. One of the longer sides 211 is provided with a plurality of gold fingers 213 for plugging into a computer or notebook type. The memory slot of the computer motherboard (not shown) and the two shorter sides 212 are each formed with at least one arc-shaped buckle groove 2 j 4 . and a plurality of stress absorbing slots 2! The arc-shaped buckle grooves 214 are fastened by the fasteners on both sides of the memory slot, so that the memory module 200 is fixed in the corresponding memory slot and is not detachable. The stress absorbing slot 215 can be elongated or otherwise shock absorbing and shock resistant. In addition, the multilayer printed circuit board 210 has an upper surface 216 and a lower surface 217. In this embodiment, the memory module 200 can be a small outline dual In-Line Memory Module (S〇_DIMM) suitable for a notebook computer. A plurality of double-sided independent gold fingers 213 are formed on the same side of the lower surface 217. The memory packages 22 are disposed on one surface of the multilayer printed circuit board 2, for example, on the upper surface 216 or the lower surface 217 of the multilayer printed circuit board 21, or the upper and lower surfaces 216 and 217. A memory package 220 is provided. As shown in FIG. 5, a part of the memory packages 22 φ φ can be disposed on the lower surface 2 17 of the multilayer printed circuit board 210. As shown in FIG. 5, in the embodiment, the memory packages 220 may be a Ball Grid Array (BGA) package and include a plurality of baubles 221 . The package structure of the memory packages 220 may be a fine pitch BGA or a window BGA. The inner package is provided with a memory chip. 222, such as an integrated circuit of dynamic random access memory. Each memory package 220 can further include a substrate 223 for powering signal transfer, a plurality of fresh wires 224 for internal electrical interconnection, and an electrically insulating sealant 225. The wafer 222 is attached to the substrate 223 by a die bond layer .1305920 226. However, the pad 227 of the wafer 222 is not covered by the substrate 223. The wafer 222 is electrically connected to the pad 224 by the bonding wires 224. The substrate 223 ′ and the wafer 222 and the bonding wires 224 are sealed by the encapsulant 225 . The solder balls 221 are bonded to the ball pads 228 on the other surface of the substrate 223. The ball pads 228 are solder resist layers 229 exposed on the same surface of the substrate 223. Usually, the ball pads 228 can be solder masks (solder masks)

Defined pad,SMD)或是非銲罩界定墊(N〇n_s〇ldei· MaskDefined pad, SMD) or non-weld cover definition pad (N〇n_s〇ldei· Mask

Defined pad,NSMD)。所謂「銲罩界定墊」係指該些球墊228 之周邊係被該防銲層229覆蓋,以圓形墊為例,即指該防銲 層229之開口直徑小於該些球墊228之直徑;相對地,所謂 「非銲罩界定墊」係指該些球墊228之周邊係不被該防銲層 229覆蓋,指該防銲層229之開口直徑應大於該些球墊228 之直徑。 再如第5圖所示,該多層印刷電路板21〇係可設有複數Defined pad, NSMD). The term "welding cap defining pad" means that the periphery of the ball pads 228 is covered by the solder resist layer 229. Taking the circular pad as an example, the opening diameter of the solder resist layer 229 is smaller than the diameter of the ball pads 228. In contrast, the term "non-welded cover defining pad" means that the periphery of the ball pads 228 is not covered by the solder resist layer 229, meaning that the opening diameter of the solder resist layer 229 should be larger than the diameter of the ball pads 228. As shown in FIG. 5, the multilayer printed circuit board 21 can be provided with plural

個接球墊218,以供接合該些銲球221。較佳地,該些接球 墊21 8係為非銲罩界定墊(NSMD),即該些接球墊21 8之外 側壁係不被該多層印刷電路板2〖〇之防銲層2 1 9覆蓋與界 疋藉以增加與對應之該些銲球22 1之接合力,減少該些接 球塾218與該些銲$ 221之銲接界面發生斷裂之可能。但非 限定地,該些接球墊218亦可為銲罩界定塾(smd)。 進一步具體說明該記憶體模組係具有加強抗震性 利用4夕層印刷電路板2 i 〇側邊形成之應力吸收槽 =5 ’可使得該多層印刷電路板2iq具有—體連接之彈性 威條230。當衝擊試驗時,該些彈性吸震條230係可往該 .1305920 力吸收槽孔2 1 5朝内潰縮再彈性回復形狀(如第5圖之箭頭 方向),大幅降低直接傳導至該些記憶體封裝件22〇之衝擊 應力,因此,該些銲球221與該些球墊228以及該些銲球221 ’與該些接球塾218之接合界面不易產生斷裂,明顯具有加強 抗震性之功效。 較佳地’該印刷電路板21G在同—較短側212之該些應 力吸收槽孔2 1 5係可為直線排列,以使對應形成之該些彈性 吸震條230具有相同寬度與一致之彈性吸震空間。通常該些 鲁彈性吸震條230之寬度約在!至3毫米(_),或與該印刷電 路板2 1 0之板厚相近即可。 在第二具體實施例中,揭示另一種加強抗震性之記憶體 模組,可適用於桌上型電腦之記憶體模組,如ddr4〇〇、 DDR2-533、DDR2-667 與 DDR2-800 等規格。如第 6 圖所示, 該記憶體模組300主要包含一多層印刷電路板3 1〇以及複數 個記憶體封裝件320。該些記憶體封裝件32〇係設置於該多 φ 層印刷電路板3H)之單一表面或上下表面。此外,該些記憶 體封裝件32〇係可為球柵陣列封裝(BGA)或其它封裝類型, 如薄小尺寸外觀封裝(TSOP)。 該多層印刷電路板310係概呈矩形而具有兩較長側311 與兩較短側312,其巾-較長側3n係設#複數個金手指 313,且該兩較短側312各形成有至少一圓弧形扣槽si*與 複數個第一應力吸收槽孔315,其形狀係可為長條形。較佳 地,該多層印刷電路板310於遠離該些金手指313之另—較 長側叫係另形成有複數個第二應力吸收槽孔316。在同一A ball pad 218 is provided for joining the solder balls 221. Preferably, the ball pads 21 8 are non-welded cover pads (NSMD), that is, the outer sidewalls of the ball pads 21 8 are not protected by the multilayer printed circuit board 2 The cover and the boundary are used to increase the bonding force with the corresponding solder balls 22 1 , and the possibility that the solder joints of the ball 218 and the solder joints 221 are broken may be reduced. However, without limitation, the ball pads 218 may also define a smd for the solder mask. Further specifically, the memory module has enhanced shock resistance. The stress absorbing groove formed by the side edge of the printed circuit board 2 i = = 5 ' can make the multilayer printed circuit board 2iq have a body-connected elastic strip 230 . When the impact test is performed, the elastic shock absorbing strips 230 can be crushed inwardly toward the .1305920 force absorbing slot 2 1 5 and then elastically restored to the shape (as indicated by the arrow in FIG. 5), thereby greatly reducing direct conduction to the memories. The impact stress of the body package 22 is such that the bonding surfaces of the solder balls 221 and the ball pads 228 and the solder balls 221 ′ and the ball 218 are less likely to be broken, and the shock resistance is enhanced. . Preferably, the plurality of stress absorbing slots 2 1 5 of the printed circuit board 21G on the same-shorter side 212 may be linearly arranged such that the corresponding elastic shock absorbing strips 230 have the same width and uniform elasticity. Shock absorption space. Usually, the width of the elastic shock absorbing strips 230 is about! It can be up to 3 mm (_) or close to the plate thickness of the printed circuit board 2 10 . In the second embodiment, another memory module for enhancing shock resistance is disclosed, which can be applied to a memory module of a desktop computer, such as ddr4〇〇, DDR2-533, DDR2-667, and DDR2-800. specification. As shown in FIG. 6, the memory module 300 mainly includes a multilayer printed circuit board 3 1 〇 and a plurality of memory packages 320. The memory packages 32 are disposed on a single surface or upper and lower surfaces of the multi-φ layer printed circuit board 3H). In addition, the memory package 32 can be a ball grid array package (BGA) or other package type, such as a thin small form factor package (TSOP). The multilayer printed circuit board 310 has a rectangular shape and has two longer sides 311 and two shorter sides 312, and the towel-long side 3n is provided with a plurality of gold fingers 313, and the two shorter sides 312 are respectively formed with The at least one arc-shaped retaining groove si* and the plurality of first stress absorbing slots 315 may be in the shape of an elongated strip. Preferably, the multilayer printed circuit board 310 is further formed with a plurality of second stress absorbing slots 316 on the other side of the longer side of the gold fingers 313. In the same

10 .1305920 較短側312之該些第一應力吸收槽孔315係可為直線排列; 該些位於較長側3U之第二應力吸收槽孔316亦可為直線排 列。藉由該些第一應力吸收槽孔3 15與第二應力吸收槽孔 316,可在該多層印刷電路板31〇之周邊構成一體連接之彈 (生吸震條330 ’以加強抗震性,防止該多層印刷電路板3丄〇 與該些記憶體封裝件320之接合界面產生斷裂。 以上所述,僅是本發明的較佳實施例而已,並非對本發 明作任何形式上的限制,雖然本發明已以較佳實施例揭露如 上,然而並非用以限定本發明,任何熟悉本項技術者,在不 脫離本發明之中請專利範圍内’所作的任何簡單修改、等效 ) 生變化與修飾,皆涵蓋於本發明的技術範圍内。 【圖式簡單說明】 第1圖:一種習知記憶體模組之俯視示意圖。 第2圖:繪示習知記憶體模組從高處依多種不同角度落下進 行掉落試驗之示意圖。 第3圖.繪不在掉落試驗之後習知記憶體模組之銲球斷裂處 之局部截面示意圖。 圖依據本發明之第一具體實施例,一種記憶體模組之 俯視不意圖。 第5圖.依據本發明之第一具體實施例,該記憶體模組依其 中一 §己憶體封裝件之局部截面示意圖。 第6圖.依據本發明之第二具體實施例,另一種記憶體模組 之俯視示意圖。 【主要元件符號說明】 1305920 10 地面 Η 局度 100 記憶體 模組 110 多層印 刷電路板 112 較短側 113 金手指 115 接球塾 116 防銲層 120 記憶體 封裝件 121 銲球 123 防銲層 124 斷裂縫 200 記憶體 模組 210 多層印 刷電路板 212 較短側 213 金手指 215 應力吸 收槽孔 216 上表面 218 接球塾 219 防銲層 220 記憶體 封裝件 221 銲球 223 基板 224 銲線 226 黏晶層 227 銲墊 229 防鋅層 3 0 0記憶體模組 3 1 0多層印刷電路板 3 12較短側 3 1 3金手指 3 15第一應力吸收槽孔 3 16第二應力吸收槽孔 320記憶體封裝件 111較長側 114扣槽 122球墊 125斷裂縫 211較長側 2 14扣槽 21 7下表面 222 晶片 225封膠體 2 2 8球塾 230彈性吸震條 3 11較長側 3 14扣槽 3 3 0彈性吸震條 1210.1305920 The first stress absorbing slots 315 of the shorter side 312 may be linearly arranged; the second stress absorbing slots 316 located on the longer side 3U may also be linearly arranged. By the first stress absorbing slots 3 15 and the second stress absorbing slots 316, an integrally connected spring (the raw shock absorbing strip 330 ′ can be formed around the multilayer printed circuit board 31 加强 to enhance the shock resistance and prevent the The joint interface between the multilayer printed circuit board 3 and the memory package 320 is broken. The above is only a preferred embodiment of the present invention and does not impose any form limitation on the present invention, although the present invention has The above description of the preferred embodiments is not intended to limit the invention, and any modifications and equivalents of the invention may be made without departing from the scope of the invention. It is encompassed within the technical scope of the present invention. [Simple diagram of the figure] Fig. 1: A schematic top view of a conventional memory module. Figure 2: A schematic diagram showing a conventional memory module falling from a height at various angles for a drop test. Fig. 3 is a partial cross-sectional view showing the break of the solder ball of the conventional memory module after the drop test. According to a first embodiment of the present invention, a memory module is not intended to be viewed from the top. Fig. 5 is a partial cross-sectional view showing a memory module according to a first embodiment of the present invention. Figure 6 is a top plan view of another memory module in accordance with a second embodiment of the present invention. [Main component symbol description] 1305920 10 Ground Η Bureau 100 Memory module 110 Multi-layer printed circuit board 112 Short side 113 Gold finger 115 Ball 塾 116 Solder mask 120 Memory package 121 Solder ball 123 Solder mask 124 Breaking crack 200 Memory module 210 Multi-layer printed circuit board 212 Short side 213 Gold finger 215 Stress absorbing slot 216 Upper surface 218 Ball 塾 219 Solder mask 220 Memory package 221 Solder ball 223 Substrate 224 Bond wire 226 Sticky Crystal layer 227 solder pad 229 anti-zinc layer 300 memory module 3 1 0 multilayer printed circuit board 3 12 shorter side 3 1 3 gold finger 3 15 first stress absorbing slot 3 16 second stress absorbing slot 320 Memory package 111 longer side 114 buckle groove 122 ball pad 125 broken crack 211 longer side 2 14 buckle groove 21 7 lower surface 222 wafer 225 sealant 2 2 8 ball 塾 230 elastic shock absorbing strip 3 11 longer side 3 14 Buckle groove 3 3 0 elastic shock absorbing strip 12

Claims (1)

1305920 十、申請專利範圍: 1、一種記憶體模組,包含: 、層p刷電路板,概呈矩形,其係具有兩較長侧與兩 較短側,其中—較長側魏有複數個金手指,且該兩較 短侧各形成有至少—圓弧形扣槽與複數個第一應力吸收 槽孔;以及 複數個δ己憶體封裝件,其係設置於該多層印刷電路板之 一表面。 如申叫專利範圍第1項所述之記憶體模組,其中該些 記憶體封裝件係為球柵陣列式(BGA)封裝而包含有複數 個銲球。 3、 如申請專利範圍第2項所述之記憶體模組,其中該多 層P席!電路板係设有複數個接球塾,以供接合該些銲球。 4、 如申請專利範圍第3項所述之記憶體模組,其中該些 接球塾係非銲罩界定墊(N〇n_s〇lder Mask Defined pad, NSMD)。 5、 如申請專利範園第丨項所述之記憶體模組其中該些 第一應力吸收槽孔係為長條形。 6、 如申請專利範圍第1項所述之記憶體模組,其中在同 一較短側之該些第一應力吸收槽孔係為直線排列。 7、 如申凊專利範圍第丨項所述之記憶體模組’其中該多 層印刷電路板於遠離該些金手指之另一較長侧係形成有 複數個第二應力吸收槽孔。 8、 如申請專利範圍第7項所述之記憶體模組,其中該些 13 1305920 第二應力吸收槽孔係為直線排列。 9、如申請專利範圍第丨項所述之記憶體模組,其中該記 憶體模組係為雙直列記憶體模組(DIMM, Dual In-Line Memory Module)。 1 0、如申請專利範圍第1項所述之記憶體模組,其中部分 之該些記憶體封裝件係設置於該多層印刷電路板之另一 表面。1305920 X. Patent application scope: 1. A memory module comprising: a layer p-brush circuit board, which is generally rectangular, and has two longer sides and two shorter sides, wherein - the longer side has a plurality of Wei a gold finger, and the two shorter sides are each formed with at least a circular arc-shaped groove and a plurality of first stress absorbing slots; and a plurality of δ-remembrance packages are disposed on the multilayer printed circuit board surface. The memory module of claim 1, wherein the memory package is a ball grid array (BGA) package and includes a plurality of solder balls. 3. The memory module described in claim 2, wherein the multi-layer P seat! The circuit board is provided with a plurality of ball sockets for engaging the solder balls. 4. The memory module of claim 3, wherein the ball 塾 is a non-welded mask defined pad (NSMD). 5. The memory module of claim 2, wherein the first stress absorbing slots are elongated. 6. The memory module of claim 1, wherein the first stress absorbing slots on the same shorter side are linearly arranged. 7. The memory module of claim 2, wherein the plurality of printed circuit boards are formed with a plurality of second stress absorbing slots on the other longer side away from the gold fingers. 8. The memory module of claim 7, wherein the 13 1305920 second stress absorbing slots are linearly arranged. 9. The memory module of claim 2, wherein the memory module is a Dual In-Line Memory Module (DIMM). The memory module of claim 1, wherein a part of the memory packages are disposed on the other surface of the multilayer printed circuit board.
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