TWI304989B - Method for screening slow bit memory cell - Google Patents

Description

Ι3Ό4989 IX. Description of the Invention: [Technical Field] The present invention relates to a method for screening defective memory cells, and particularly relates to erasing all memory blocks by using the first verification memory cell erasure failure The memory cell is skipped once and then the design of the next memory cell is verified and the second method of verifying the memory cell erasure is to screen the memory cell for the defective memory cell.

[Prior Art] Flash memory has the characteristics of saving data without power supply, and has the functions of erasing and writing, so it is widely used in various electronic products. The traditional (4) memory can be divided into a number of blocks, each of which has many memory cells. Each memory cell is used to record one bit of information: the memory cell has a heteropolar pole, a floating pole, a miscellaneous and a bet. The data of the memory cells is determined by the amount of electrons stored in the floating finances. When a high amount of electrons are stored in the floating gate, the gate voltage is higher at this time, and a higher voltage is required to be given to the control gate. For example, if the voltage is greater than 6 volts, the source and the impurity of the signal (10) can be turned on, The general definition is 〇 and is stylized. When the resources of the cell store a low amount of electrons in the floating gate, the voltage of the door is low, and only the dumping is needed. After the flash memory erases the data, a verification procedure is required to secure the capital.

TW2992PA 6 ' 1304989 , the correctness of being erased. In the erasing action, the entire memory block is erased, and the verification is usually performed in units of eight, sixteen or thirty-two bits (memory,). In the process of whether the data of the memory cell is 1, it will be verified one by one whether each address is erased. If the verified address fails to be erased, the memory block is electrically erased one or more times, and the address of the original verification failure is repeatedly verified and erased until the one that was originally verified to fail. The address is verified as a successful erase. Φ Perform the verification step for the next address. In the traditional method of screening defective memory cells, the above-mentioned erasing and verification procedure is applied to screen out memory cells that cannot be verified, and the main difference-differential is the verification condition when screening is more than that in general erasing. The verification conditions are more stringent, such as. Fig. 1 is a threshold voltage distribution diagram after a memory block is erased. When the threshold voltage (vt) of the memory cell is less than EV, the verification is performed during the erase verification. A lower gate voltage is applied during verification, so that the threshold voltage of the memory cell needs to be less than MR (marginread) to pass the verification, and the φ s cell that cannot be verified is the defective bit to be screened. However, the above verification method will result in some memory cells that have been verified as being erased successfully. Because the defective memory cells have not been verified, they must be erased continuously, and as the number of erasures increases, An over-event phenomenon occurs, which in turn leads to leakage currents. Therefore, the memory cell is difficult to program or the leakage current is consumed in the standby state, or when the other programmed memory cells are read, the memory cell is mistakenly judged as the erased state. [Summary of the Invention]

TW2992PA 7 * 1304989 & In view of the above, it is an object of the present invention to provide a method of selecting a defective memory cell. The other is: the under-verified memory cell erase fails and the memory block is erased. ^ After all the memory cells are recalled, the address is then skipped and the next address is used: the design of the cell verification, plus the second The sub-validation memory cell failure failed to screen the design of the defective memory cells, and the defect 5 cells can be effectively and clearly screened. Therefore, the probability of over-erasing of the memory cells is reduced, and the phenomenon that leakage current is generated by the memory cells is prevented. According to the object of the present invention, a screening method for defective memory cells is proposed for use on a memory. The memory can be divided into a number of memory blocks. Each memory block has N cells, and N is a positive integer greater than one. The N memory cell lines are a 1~N memory cell. In this method, 'verify whether the i-th memory cell is successfully erased, i is a positive integer less than or equal to N. If the i-th memory cell is successfully erased, it is checked whether the first memory cell is the Nth memory cell. If the i-th memory cell fails to be erased, erase the N memory cells of the memory block once and check whether the i-th memory cell is the Nth memory cell. If the i-th memory cell is not the Nth memory cell, verify whether the i+th memory cell is successfully erased. If the i-th memory cell is the Nth memory cell, it means that the normal memory cell has been erased, and the same memory block is subjected to a second verification to screen out the defective memory cell. Verify that the jth memory cell is successfully erased, and j is a positive integer less than or equal to N. If the jth memory cell is successfully erased, it is checked whether the jth memory cell is the Nth memory cell. If the jth memory cell fails to be erased, the jth memory cell is screened as a defective memory cell, and it is checked whether the jth memory cell is the Nth TW2992PA 8 • 1304989 memory cell. ^ If the jth memory cell is not the Nth memory cell, verify that the j+1th memory cell is erased successfully. If the jth memory cell is the Nth memory cell, the method ends. When this method is used for the screening of defective memory cells, the same operating conditions as the erase operation can be applied, and the voltage distribution map of the boundary voltage can be obtained as shown in Fig. 2 as an eraser. In addition to characterization, • and avoid the occurrence of over erase and its associated negative effects. The above described objects, features, and advantages of the present invention will become more apparent and understood. The following detailed description of the preferred embodiments of the present invention will be described in detail as follows: [Embodiment] Please refer to the third 4, FIG. 3 is a flow chart showing a method of screening defective memory cells in accordance with a preferred embodiment of the present invention. Figure 4 is a schematic illustration of the memory of the method of Figure 3. As shown in the figure, the screening method of the defective memory cell of the embodiment can be applied to a memory 2 (such as a flash memory) for effectively and clearly screening the defective memory cell (sl〇wbit memory cell). , thereby reducing the probability of memory cells producing excessive ervering (ervererase) and preventing leakage of memory cells. The memory 2 has at least one memory block 21, and the memory block 21 has N cells. N is a positive integer greater than 1, and n memory cells are a first to N memory cells. In the present embodiment, N is, for example, 25, and the 25 memory cells are a 1st to 25th memory cells. Among them, the number of the first memory cell is TW2992PA 9 1304989. The second memory cell of the abortion is 22 (2). And so on, the standard of a memory cell after the 25th method (the private will explain the following hundred first) in step U, verify whether the first memory cell is successfully erased, is a positive integer less than or equal to N. In the present embodiment, for example, the first record 22(1) is verified to be successfully erased.

If the first memory cell erase is successful, proceed to step 12 to check if the i-th memory cell is the Nth memory cell (the last memory cell). ^ If 'the first memory cell 22 (1) is verified to be erased successfully' then check if the first memory cell 22 ( 1) is the 25th memory cell 22 (25). When the right § 忆 忆 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 After the step of erasing, the process proceeds to step 12 to check whether the i-th memory cell is the first memory cell. For example, if the first memory cell 22(1) is verified as an erase failure, the first memory cell 22(1) to the 25th memory cell 22(25) of the memory block 21 are erased. After the erasing step, step 12 is performed to check whether the first memory cell 22 (1) is the 25th memory cell 22 (25). If the i-th memory cell is not the Nth memory cell, the value of 丨 is added to j. For example, the memory 20 can be added through its counter value and returned to step u to verify whether the i+th memory cell is wiped. In addition to success. For example, since the i-th memory cell 22 (1) is not the 25th memory cell 22 (25), the value of 丨 is +1, and returns to step 11 to verify whether the second memory cell 22 (2) is erased. success. Therefore, it can be verified one by one whether the first memory cell 22 (1) to the 25th memory cell 22 (25) are successfully erased. If the memory cell of the first memory cell 22 (丨) to TW2992PA 10 •1304989 of the 25th memory cell 22 (25) fails, the first memory cell 22 of the memory block 21 is erased ( 1) to the 25th memory cell 22 (25) - times. That is to say, if the first memory cell 22 (丨) to the 25th memory cell 22 (25) encounters the failure of the μ memory cell erasure verification, the first block of the § memory block 21 is erased. 1 memory cell 22 (1) to 25th memory cell 22 (25) Μ, Μ is a positive integer less than or equal to 25. If the i-th memory cell is the third memory cell, indicating that the first memory cell 22 (1) to the 25th memory cell 22 (25) of the memory block 22 have all been verified one by one, proceed to step 14. Re-verify the same memory block to screen out the defective memory cells. Verify that the jth memory cell is erased successfully. 'j is a positive integer less than or equal to N. In the present embodiment, j starts from 1, for example, to verify whether the first memory cell 22(1) is successfully erased. If the sound of the memory cells is successfully erased, the process proceeds to step 15 to check whether the jth memory cell is the Nth memory cell. For example, it is checked whether the first memory cell 22 (1) is the 25th memory cell 22 (25). If the jth memory cell erase verification fails, the process proceeds to step 16, where the jth memory cell is screened and recorded as a defective memory cell. Wherein, when the jth memory cell is screened as a defective memory cell, the address of the jth memory cell can be recorded. For example, if the first memory cell 22 (1) erases the verification failure, the first memory cell 22 (1) is screened and recorded as a defective memory cell. After the screening step, and performing step 15, it is checked whether the jth memory cell is the Nth memory cell. For example, it is checked whether the first memory cell 22 (1) is the 25th memory cell 22 (25). If the jth memory cell is not the Nth memory cell, the value of j is incremented by 1, for example, by adding a value through the counter, and returning to step 14, verifying the +1th

TW2992PA 11 • 1304989 The j cell was successfully removed. For example, since the first memory cell 22 (1) does not have the 25th s memory cell 22 (25)', it is verified whether the second memory cell 22(2) is successfully erased. If the jth memory cell is the Nth memory cell, indicating that the first memory cell 22 (1) to the 25th memory cell 22 (25) of the memory block 22 have all been verified one by one, the method is terminated. Therefore, the verification process shown in the above step 11 is to verify the flow of the memory cells 21 for the first time. In addition, the above step 14 is a second verification process after the subsequent step, verifying whether there are still memory cells in the same memory block that cannot be verified by erasing, and classifying them as defective memory cells to be screened, and further Provides a baseline for subsequent repair of defective memory cells. As for how to verify whether the memory cell is successfully erased in steps 11 and 14, the following is exemplified, but the technique of this embodiment is not limited thereto. Further, as shown in FIG. 4, the memory 20 further has word lines wi to W5, source lines S1 to S5, and bit lines B1 to B5, and the word lines W1 to W5 are horizontally arranged in parallel, and the bit lines B1 to B5 are provided. It is set in parallel in the longitudinal direction. The word line wi~W5 and the bit line B1~B5 are vertically staggered. The word line wi~W5 is electrically connected to the control gate CG of the corresponding memory cell, and the control gate of the same column of memory cells is the same. One word line is electrically connected. The bit lines B1 to B5 are electrically connected to the corresponding pole D of the memory cell, and the gates of the same row of memory cells are electrically connected to the same bit line. The source lines S1 to S5 are electrically connected to the source S of the corresponding memory cell. The source s of the same column of memory cells is electrically connected to the same source line. The source lines of the same memory block are ultimately electrically connected together to achieve an erase operation in units of memory blocks. Please refer to Figure 5, 12

TW2992PA 1304989 is a cross-sectional view of a single memory cell of the memory of FIG. As shown in Fig. $, the memory 20 has a radiance 3 〇, the i-th memory cell 22 (1) to the 25th memory cell 22 (25), and the word line W1 〜 W5 of the memory block 21 The source lines S1 to S5 and the bit lines B1 to B5 are disposed on the germanium substrate 3A. In step 11, first, a first voltage higher than the threshold voltage is applied to the control gate CG of the i-th memory cell, for example, a voltage is applied through the corresponding word line to make the drain and source of the memory cell Generate channels between them. Next, applying φ to add a suitable second voltage to the drain D of the i-th memory cell, for example, applying a voltage through the corresponding bit line, so that a voltage difference between the plasma cell and the source is generated. Current. Then, the current between the source S and the drain D of the second memory cell is measured by the sense amplifier to be greater than a first erase verify current value, for example, by transmitting the corresponding bit line and the sense amplifier. Current. If the current between the source S and the dipole D of the i-th δ cell has a larger value than the first erasing and verifying current value, it is determined that the i-th memory cell is verified by the first erasing. If the current between the source S and the drain D of the i-th memory cell is less than or equal to the first eraser except the verify current value, it is determined that the i-th memory cell fails the first erase test. The first voltage and the second voltage are, for example, 4 volts (v) and 1 volt (V), respectively, and the first erase verify current value is 20 microamperes (#A). Similarly, in step 14, first, a third voltage higher than the threshold voltage is applied to the control gate CG of the j-th memory cell, for example, a voltage is applied through the corresponding word line to make the drain of the memory cell and A channel is created between the sources. Next, a suitable fourth voltage is applied to the drain D of the jth memory cell. For example, a voltage is applied through the corresponding bit line to cause a voltage difference between the drain and the source of the memory cell to generate a current. Then, through the sense amplifier, the current between the source S and the drain D of the B04989 memory cells is greater than a second erase verify current value, for example, to transmit the corresponding bit line and sense. The amp measures the current. If the current between source 8 and drain D of the jth memory cell is greater than the second erase verify current value', the jth memory cell is verified by the second erase. If the current between the source S and the drain D of the jth memory cell is less than or equal to the second erase verify current value', the jth memory cell is determined not to pass the second erase verify. Wherein the 'third voltage and the fourth voltage are 4 volts (v) $ and 1 volt (V) respectively. The second erase verify current value is 20 microamperes (#a). In principle, the same verification conditions should be used for steps 11 and 14. As for how to verify whether the memory cell is the last memory cell in steps 12 and 15, the following is exemplified, but the technique of this embodiment is not limited thereto. In step 12, the address c counter (Address c〇unter) value i is the preset final value N. If the address counter value j is equal to the preset final value N ', then the process proceeds to step 14 for the second verification of the same memory area; if the address counter value i is not equal to the preset final value N, the address counter is incremented. φ returns to step 11 to erase the next memory cell. Similarly, in step 15, the comparison of the address counter (Address c_ter) value 1 is the preset final value N. If the address counter value i is equal to the preset final value N, the defect memory cell screening process is ended; if the address counter value i is not specific to the pre-no final value N, the address counter is incremented by one and returned to the step pair. The next memory cell is erased and verified. As for the flow of how to erase all the memory cells of the memory block 21 in step 13, the following is exemplified, but the technique of the embodiment is not limited thereto. Please refer to Figure 6, first, float the source s of each memory cell and

TW2992PA 14 1304989 > and pole D. Next, a suitable negative polarity voltage is applied to the control gate CG of each of the memory cells, e.g., to apply a voltage through the corresponding word line. Then, a voltage is applied to the germanium substrate 30. The voltages applied to the control gate and the germanium substrate are, for example, -8 volts and 9 volts, respectively. Then, the electrons originally stored in the floating gate will be injected into the crucible substrate 30 due to the Fowler-Nordheim electron tunneling (FN tunneling) effect, so that the threshold of the memory cell The voltage drops to achieve the erase effect. The screening method for the defective memory cell disclosed in the above embodiment of the present invention, the first verification of the memory cell erasure failure and erasing all the memory cells in the memory block once, then performing the verification of the next memory cell, plus The second verification § the design of the memory cell is a defective memory cell, and the defective memory cell can be effectively and clearly screened. Therefore, the probability of over-erasing of the memory cells is further reduced, and the phenomenon that the memory cells generate leakage current is prevented. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. TW2992PA 15 1304989 Layout Diagram Brief Description of the Drawings Figure 1 shows the threshold voltage after the erase of the conventional memory block. Fig. 2 is a diagram showing the voltage distribution of the unrestricted memory cell in accordance with the present invention. ~a Figure 3 is a flow chart showing a method of screening for defects 依照 in accordance with a preferred embodiment of the present invention. , ^之之

Fig. 4 is a view showing a window of a memory which is applied by the method of Fig. 3. Fig. 5 is a view showing a single memory of the memory of Fig. 4. The sixth Lin is the electricity when the memory cells of Figure 5 are erased; the birth = 乍. [Main component symbol description] 20 : Memory

21 ··Memory block 22 (1)~22 (25): The first memory cell 3〇: The 25th memory cell B1~B5 of the 矽 base: Bit line CG: Control gate D ·> and pole FG: Floating gate S: source S1~S5: source line W1~W5: word line

TW2992PA 16

Claims (1)

ΟΌ 4989 Patent Application Area 97. ||i£ Replacement Page 1. A method for screening defective memory cells for a memory having N memory cells 'N is a positive integer greater than 1, The N memory cells are a first to N memory cells, and the method includes: verifying whether the i-th memory cell is successfully erased, i is less than or equal to a positive integer; and if the i-th memory cell is successfully erased 'Check whether the first memory cell is the Nth memory cell; when the first memory cell erase fails, erase the N memory cells once, and check whether the i-th memory cell is the first N memory cells; and if the i-th memory cell is not the N-th memory cell, verify whether the i+i memory cell is successfully erased. 2. The method of claim 2, wherein each of the memory cells has a control gate, a source, and a drain, and the step of verifying the third cell shock comprises: a voltage is applied to the control gate of the ith memory cell; a second voltage is applied to the drain of the ith memory cell, the first voltage is different from the second voltage; Whether the current between the source and the drain of the memory cell is greater than a erase verify current value. 3. The method of claim 2, wherein: the current between the source and the drain of the first memory cell is greater than the erase verify current value 'determines the ith memory Cell verification by erasing; and TW2992PA 17 ISO4989 If the current between the source and the gate of the i-th memory cell is less than S equal to 5 erase erase verify current value, it is determined that the i-th memory cell is not verified by erasure. 4. The method of claim 2, wherein the first voltage and the second voltage are 4 volts (V) and 1 volt (v), respectively, and the erase sigh current value is 20 microamperes ( "A). 5. The method of claim 1, further comprising: if the i-th memory cell is the first memory cell, verifying whether the j-th memory cell is successfully erased, and j is less than or equal to N a positive integer; if the jth memory cell is successfully erased, check whether the first memory cell is the Nth memory cell; if the jth memory cell erase fails, the jth memory cell is screened a defective memory cell, and checking whether the jth memory cell is the Nth memory cell; u if the jth memory cell is not the Nth memory cell, verifying whether the +1th memory cell is erased Success; and if the jth memory cell is the Nth memory cell, the method ends. 6. The method of claim 5, wherein each of the memory cells has a control gate, a source and a drain, and the step of verifying the first memory cell further comprises: applying a a first voltage is applied to the control gate of the jth memory cell; a second voltage is applied to the pole of the jth memory cell, the first voltage is different from the second voltage; and the first j is measured The current between the source and the drain of the memory cell is TW2992PA 1304989 No greater than a erase verify current value. 7. The method of claim 6, wherein: if the current between the source and the pole of the jth memory cell is greater than the erased test stream value, determining the jth memory The cell is verified by erasing; and the current between the source and the drain of the j-th memory cell is less than or equal to the erase verifying power, and the j-th memory cell is not verified by erasing. 8. The method of claim 6, wherein the first voltage and the second voltage are 4 volts and respectively! For volts, the erased verify current value is 20 microamperes. 9. The method of claim 5, wherein the step of checking the jth memory cell further comprises: checking whether the address of the jth memory cell is the address of the Nth memory cell. The method of claim 9, wherein: if the address of the jth memory cell is the address of the Nth memory cell, determining the jth memory cell is the Nth a memory cell; and if the address of the jth memory cell is not the address of the Nth memory cell, determining that the jth memory cell is not the Nth memory cell. 11. The method of claim 5, wherein the step of screening the j-th memory cell as the defective memory cell further comprises: recording the address of the j-th memory cell. 12. The method of claim 1, wherein the step of checking the TW2992PA 19 • 1304989 i-th memory cell further comprises: checking whether the address of the i-th memory cell is the N-th memory cell Address. 13. The method of claim 12, wherein: if the address of the i-th memory cell is the address of the Nth memory cell, determining the i-th memory cell is the N-th memory Cell; If the address of the i-th memory cell is not the address of the first: N memory cells, it is determined that the i-th memory cell is not the N-th memory cell. 14. The method of claim 1, wherein the step of erasing the N memory cells further comprises: electrically erasing the N memory cells once. The method of claim 14, wherein the flash memory has a substrate, the N memory cells are disposed on the substrate, each of the cells has a control gate, a source and a drain, the step of electrically erasing the N memory cells further comprises: floating the source and the drain of each of the memory cells; applying a first voltage to each of the memory cells The control gate; and applying a second voltage to the base, the first voltage trace of the second TW2992PA 20