1303071 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種邏輯電路，且特別是有關於一種 可應用於内容可定址記憶體之樹狀AND型比對電路 (match circuit)裝置。 【先前技術】 内容可定址記憶體（Content Addressable Memory，簡 稱CAM)之資料搜尋速度限制及主要功率消耗來源之一是 其比對電路。比對電路之設計大致分為n〇r型比對電路 與NAND型比對電路裝置兩種。NAND型比對電路裝置雖具 有低功率的特性，但是搜尋速度相當慢。n〇r型比對電路 雖具有局速搜尋的特性，但功率消耗卻十分可觀。儘管有 許多可改善NOR型比對電路的功率消耗的電路設計方 法。例如，藉由降低電壓擺幅與減少直流電流等方式，但 在大容量的内容可定址記憶體中，上述兩種方式還是無法 有效改善NOR型比對電路的功率消耗問題。 第 1 圖是一種現有的 PF-CDPD(Pseudo-footless clock-and-data precharged dynamic)邏輯電路，其已被 用來設計CAM的比對電路400，此電路架構是採用AND型 比對電路裝置，將多數動態AND型邏輯閘410這種依序串 接的電路型態，只要其中一級動態AND型邏輯閘410比對 失敗，則其後面所有的邏輯閘均不做求值動作。此電路型 態如同NAND邏輯閘的精神，所以功率消耗極低。另一方 1303071 面，因為所有的N型電晶體411 (NMOS : N型金屬氧化半 導體）的閘極G輸入皆在動態AND型邏輯閘410求值動作 前就已確定。故若單一級的所有輸入皆為邏輯「1」（即單1303071 IX. Description of the Invention: [Technical Field] The present invention relates to a logic circuit, and more particularly to a tree-like AND type match circuit device applicable to content addressable memory. [Prior Art] One of the sources of data search speed limitation and main power consumption of Content Addressable Memory (CAM) is its comparison circuit. The design of the comparison circuit is roughly classified into two types: n〇r type comparison circuit and NAND type comparison circuit device. Although the NAND type comparison circuit device has a low power characteristic, the search speed is rather slow. Although the n〇r type comparison circuit has the characteristics of speed search, the power consumption is considerable. Although there are many circuit design methods that can improve the power consumption of the NOR type comparison circuit. For example, by reducing the voltage swing and reducing the DC current, in the large-capacity content addressable memory, the above two methods cannot effectively improve the power consumption of the NOR-type comparison circuit. 1 is a conventional PF-CDPD (Pseudo-footless clock-and-data precharged dynamic) logic circuit, which has been used to design a CAM comparison circuit 400, which adopts an AND type comparison circuit device. The majority of the dynamic AND-type logic gates 410 are sequentially connected in a circuit type. As long as the first-order dynamic AND-type logic gates 410 fail to match, all subsequent logic gates are not evaluated. This circuit type is like the spirit of a NAND logic gate, so power consumption is extremely low. The other side is 1303071 because the gate G inputs of all N-type transistors 411 (NMOS: N-type metal oxide semiconductors) are determined before the dynamic AND logic gate 410 is evaluated. Therefore, if all inputs of a single level are logical "1" (ie, single
一級所有資料比對成功），則N型電晶體411的汲級D與 源級S皆為「〇V:零電位」，所以有如虛擬接地般的效果， 使付PF-CDPD的每一級都如同僅有兩個反相器般，速度 即可大幅提昇。但因每一級動態AND型邏輯閘410能串 接的N型電晶體411個數受限於電荷分配效應（charge shanng effect)，故當資料寬度變長時，整個比對電路4〇〇 的延遲也會隨之變長。 牌厌L遲問題，第2圖之現有比對電路則利用平行 處理方式，將關鍵路徑的部份電路抽離出來，被抽離的電 路之每-級可在同-時間運算，而其餘在改變後的關鍵路 私上的邏輯閘因為串接的N型電晶體數目變少，所以運曾 速度得以加快。相對於第之電路，第 = 卻會增加時脈訊號的負載，造成内 :路方式 另一方面，第1圖電路利用前面閘級比 能；:閘級是否求值的特性在第2圖電路也不 王毛揮，因此功率消耗也會較大。 據上所述，第！圖之比對電路4〇〇雖 消耗，但卻可能有延遲問題。第 中田降低功率 運算速度，但卻無法有效克服功率_^電_可加快 此點有必要再尋求最佳的解決方式。、問題。故針對 1303071 【發明内容】 持低功率消耗的特| 本發明的目的就是在提供—種可應用於内容可定址 δ己憶體之龍AND型比對電路裝置，心改盖現有内容 可定址記憶體之娜型比對電路裝置之運算速度，並維 —本發明的另—目的就是在提供—種可制於内容可 定址記憶體之樹狀AND型比對電路裝置，用以解決現有 内容可定址記憶體t職型比對電路雖具有高速搜尋的 特性’但消耗功率卻很大的缺點。 根據本發明之上述目的，提出一種可應用於内容可定 址記憶體讀狀AND型比對電料置，其使用樹枝狀連 結許多AND型比對邏輯閘電路。 依照本發明一個實施例，在多數個AND型比對電路 群組彼此間以-個第-AND邏輯閘呈樹枝狀相互連接， 可以有效的提升電路之搜尋速度，並可超越現有馳型 比對電路。 依照本發明一個實施例，包含有一個内容可定址記憶 體細胞元’以及分別與該内容可定址記憶體細胞元連接的 -個寫入/搜尋緩衝器、—個位址解碼器、—個位元線負載 及-個比對f路。該比對電路具有多數個A·型比對電 路群組，且料AND型比對電路群組彼此間以-個第一 AND邏輯閘呈樹枝狀相互連接。以上在提升了電路運算的 平仃度’不但不增加時脈的負載’也因為AND型邏輯電 路轉態變動率低的關係’因此能保有現有NAND型的好 1303071 處，大幅節省功率消耗。 根據上述’可知本發明之可應用於内容可定址記憶體 之樹狀AND型比對電路裝置確實具有下列優點： 1·提升電路運算的平行度，以提高内容可定址記憶體 的搜尋速度。 2·因為AND型邏輯電路轉態變動率較少的緣故，故 可以減少電路之充放電的機會，以降低功率消耗。 【實施方式】 參照第3圖，是本發明的第一實施例的電路圖。 本發明之可應用於内容可定址記憶體之樹狀and比 對電路裝置的實施例，包括二個AND型比對電路群組i 〇〇 及100’，彼此間以第一 AND邏輯閘110呈樹枝狀相互連 接在該等AND型比對電路群組1〇〇及100，的輸入端，以 及一連接在該等AND型比對電路群組i 00及1〇〇,輸出端 的第二AND邏輯閘120。 該第一 AND邏輯閘11〇具有一輸入端1U及一輸出端 該輸入端hi由外部饋入一 cLK(Clock:時脈）訊號。 第一 AND邏輯閘110之其他細胞元的輸入端113及113, 接至内容可定址記憶體中同一列之不同細胞元（圖未示）的 輸出。 該等AND型比對電路群組ι〇〇、1〇〇，相互平行地連 接在該第一 and邏輯閘no與該第二AND邏輯閘12〇之 間。而且’該等AND型比對電路群組ι〇〇及1〇〇，分別由 1303071 夕數個AND閘ίο!、1〇1，依序串接組成，ι〇ι、⑻，分別 表不100、100’比對電路群組中的AND閘。最前的and 邏輯閘1〇1、1〇1’的一輸入端1011均連接至該第- AND 邏輯閘110的輸出端112，最末的AND邏輯閘1〇1、1〇1， 的一輸出端1012均連接至該第二AND邏輯閘12〇的一輸 入端121 〇 相較於現有内谷可定址記憶體的Nand型比對電路 | 速度慢的缺點，本發明利用樹狀連接的AND型比對電路 以相互平行的該等AND型比對電路群組1〇〇、1〇〇，之架 構’可以提升搜尋速冑。而1，再相較於内容可定址記憶 體的NOR型比對電路消耗功率高的缺點，因本發明之時 脈訊號的負載未增加，所以内容可定址記憶體的消耗功率 不因平行度增加而上升。故本發明AND型比對電路裝置 應用於内容可定址記憶體上，具有比對速度快以及消耗功 率低之優點。 如上所述，本發明是利用樹枝狀的連接方式達到預期 的功效與目的。第4圖是該第一實施例之採用串接比對的 AND型比對電路。而樹狀AND型比對電路的平行度可藉 由分枝的層數來提升。在第4圖中，每一個圓圈内部「心 代表-個AND閘。而該「n」的等效電路見第7圖，第7 圖中的200表示此AND閘101的負載（L〇ad)，而1〇2中的 N型電晶體1021的數目代表第4圖圓圈内部「n」中細胞 元（cell)的數目’容後詳述。 參照第5圖，是本發明之第二實施例，說明分枝層數 l3〇3〇7i 2以兩層的實施架構。參照第6圖，是本發明之第三實施 列’說明分枝層數舉以三層的實施架構。由第5、6圖 =分枝層度越多，平行度越高，而搜尋速度可能越快。 圖中’每-個圓圈内部的、代表_個綱 .其結構等效於第4圖中圓圈内部的「n」，此不再贊述。 +此外’再參照第7圖，第7圖是說明第4、5、6、圖之 第-、二、三實施例之圓圈内部的「〜，即單一級的纏 閑1〇1。第4、5、6圖表示單一筆的比對線，在一般的應 用中’因CAM中通常都有數千筆不等的資料，由此可知 時脈訊號（Φ)的負載相當重，故時脈訊號緩衝器的功率 也相當可觀。在本發明的樹狀AND型比對電路並不會增 加時脈的負載，如第4、5、6圖所示，時脈訊號（φ)曰^ 負載在三個架構中均相同，因此時脈負載並無增加，故讓 内谷可疋址§己憶體在功率消耗上，能有更好的表現。此 外树狀and型比對電路每一級是否作求值動作，乃取 决於上一級的比對結果，如此，也保有現有NAND型比對 電路低功率的好處。 參閱第8圖，將本發明樹狀AND型比對電路實現於 128位元寬度的内容可定址記憶體（Cam : content Addressable Memory)的架構，其中該内容可定址記憶體包 含一寫入/搜尋緩衝器 130(write and search buffers)、一位 址解碼器 140(address decoder)、一負載位元線 150(bit-line load)、一内容可定址記憶體細胞元i6〇(c〇ntent Addressable Memory Cell :簡稱 CAM Cell)，及一比對電 1303071 路170(match circuit)。該寫入/搜尋緩衝器130、該位址解 碼器140、該位元線負載150及該比對電路170均分別與 該内容可定址記憶體細胞元160連接。 當CAM作寫入動作時，blen為高準位。此時，該負 載位元線150(bit-line load)電路關閉，而該寫入/搜尋緩衝 器130(write and search buffers)將欲寫入該内容可定址記 憶體細胞元160(CAM Cell)的值送入寫入位元線（WBLP、 WBLN) 〇接著，該位址解碼器140(address decoder)將解碼 後的選擇到的字元線（word line)，驅動到高準位；此時寫 入位元線（WBLP、WBLN)的數值得以寫入該内容可定址記 憶體細胞元160(CAM Cell)。當内容可定址記憶體做比對 動作時，外部輸入的資料經由該寫入/搜尋緩衝器130(write and search buffers)送入搜尋位元線（SBLP、SBLN)與該内容 可定址記憶體細胞元160(CAM Cell)所儲存的值作比對， 若内容可定址記憶體儲存的值與外部輸入的資料吻合，則 該内容可定址記憶體細胞元160(CAM Cell)中inner的點會 經由搜尋位元線（SBLP、SBLN)被充電到高準位。 參照第9圖與第10圖，第9圖是第8圖之該比對電 路170(match circuit)中單一個AND邏輯閘放大圖，其中 A、B、C、D、E、F表示共有六個内容可定址記憶體細胞 元；第10圖則是第9圖的等效電路。而若單一級AND閘 101中的細胞元102(Cell)比對結果全部吻合，則AND閘 101中Nl、N2、N3、N4、N5、N6的電晶體閘極（G)會被 設為高準位，則LML(Local Match Line :局部比對線）在Φ 11 1303071 ^號為:準位時（也即是電路求值的相位），會輸出為高準 =合:：求值動作，因此，當整物 '' 、 圖中ML〇ut<n>則會輸出為高準位。 的以第11圖來說明第8圖中内容可定址記憶體 、日、 <。當外部ci〇ek為高準位時，φ為低準位，此If all the data of the first stage is successful, the D grade D and the source level S of the N-type transistor 411 are both “〇V: zero potential”, so the effect is like a virtual ground, so that each stage of the PF-CDPD is like With just two inverters, the speed can be greatly improved. However, since the number of N-type transistors 411 that can be connected in series by each level of the dynamic AND type logic gate 410 is limited by the charge shanng effect, when the data width becomes longer, the delay of the entire comparison circuit 4〇〇 It will also grow longer. The card is a late L problem. The existing comparison circuit of Figure 2 uses a parallel processing method to extract part of the circuit of the critical path. Each phase of the extracted circuit can be operated in the same time, while the rest The changed logic gate of the critical road is speeded up because the number of N-type transistors connected in series is reduced. Compared with the first circuit, the first = will increase the load of the clock signal, resulting in the internal: way, on the other hand, the circuit of Figure 1 uses the previous gate ratio specific energy;: the characteristics of the gate stage is evaluated in the circuit of Figure 2 It is not Wang Mao, so the power consumption will be larger. According to the above, the first! Although the ratio of the graph is consumed by the circuit 4, there may be a delay problem. No. Zhongtian reduces the power calculation speed, but can't effectively overcome the power _^ electricity _ can be accelerated. It is necessary to find the best solution. ,problem. Therefore, for 1303071 [Summary of the Invention] The purpose of the present invention is to provide a dragon AND type comparison circuit device which can be applied to a content addressable δ hexamed body, and to modify the existing content addressable memory. The operation speed of the body type comparison device, and the other purpose of the present invention is to provide a tree-like AND type comparison circuit device which can be fabricated into a content addressable memory to solve the existing content. The address memory t-type comparison circuit has the disadvantage of high-speed search characteristics but consumes a large amount of power. SUMMARY OF THE INVENTION In accordance with the above objects of the present invention, a data-addressable memory read-like AND type alignment device is proposed which uses a plurality of AND type alignment logic gate circuits in a dendritic connection. According to an embodiment of the present invention, a plurality of AND-type comparison circuit groups are connected to each other by a --AND logic gate in a dendritic shape, which can effectively improve the search speed of the circuit and can exceed the existing type comparison. Circuit. According to one embodiment of the present invention, a content addressable memory cell element is included, and a write/search buffer, an address decoder, and a bit are respectively connected to the content addressable memory cell element. The line load and the - pair of f roads. The comparison circuit has a plurality of A-type comparison circuit groups, and the AND-type comparison circuit groups are connected to each other in a dendritic shape by a first AND logic gate. In the above, the degree of flatness of the circuit operation is improved, and the load of the clock is not increased because of the low rate of change of the AND logic circuit. Therefore, the existing NAND type can be kept at 1303071, and power consumption is greatly saved. According to the above, it can be seen that the tree-shaped AND type matching circuit device applicable to the content addressable memory of the present invention has the following advantages: 1. The parallelism of the circuit operation is improved to improve the search speed of the content addressable memory. 2. Since the AND type logic circuit has a small rate of change in the state of transition, it is possible to reduce the chance of charging and discharging of the circuit to reduce power consumption. [Embodiment] Referring to Figure 3, there is shown a circuit diagram of a first embodiment of the present invention. An embodiment of the tree-shaped and aligning circuit device of the present invention, which is applicable to a content-addressable memory device, includes two AND-type matching circuit groups i 〇〇 and 100 ′, which are represented by a first AND logic gate 110 Dendritic interconnects at the input of the AND type alignment circuit groups 1 and 100, and a second AND logic connected to the AND type comparison circuit group i 00 and 1 〇〇, the output Gate 120. The first AND logic gate 11 has an input terminal 1U and an output terminal. The input terminal hi is externally fed with a cLK (Clock: Clock) signal. The input terminals 113 and 113 of the other cell elements of the first AND logic gate 110 are connected to the outputs of different cell elements (not shown) in the same column of the content addressable memory. The AND type matching circuit groups ι , 1 , are connected in parallel with each other between the first and logic gates and the second AND gates 12A. Moreover, 'the AND type is compared to the circuit group ι〇〇 and 1〇〇, respectively, by 1303071, the number of AND gates ίο!, 1〇1, in sequence, ι〇ι, (8), respectively, not 100 , 100' aligns the AND gates in the circuit group. An input terminal 1011 of the first AND logic gate 1〇1, 1〇1' is connected to the output terminal 112 of the AND-AND logic gate 110, and an output of the last AND logic gate 1〇1, 1〇1, The terminal 1012 is connected to an input terminal 121 of the second AND logic gate 12A, which is slower than the Nand type comparison circuit of the existing inner valley addressable memory. The present invention utilizes a tree-connected AND type. The comparison circuit is parallel to the AND type to compare the circuit groups 1〇〇, 1〇〇, and the architecture 'can improve the search speed. However, compared with the disadvantage that the NOR type comparison circuit of the content addressable memory consumes a high power, since the load of the clock signal of the present invention is not increased, the power consumption of the content addressable memory is not increased by the parallelism. And rise. Therefore, the AND type comparison circuit device of the present invention is applied to content addressable memory, and has the advantages of faster alignment speed and lower power consumption. As described above, the present invention utilizes a dendritic connection to achieve the desired efficacy and purpose. Fig. 4 is an AND type comparison circuit using the serial alignment of the first embodiment. The parallelism of the tree AND type comparison circuit can be improved by the number of layers of the branches. In Fig. 4, the inside of each circle "the heart represents an AND gate. The equivalent circuit of the "n" is shown in Fig. 7, and the 200 in Fig. 7 indicates the load of the AND gate 101 (L〇ad). The number of N-type transistors 1021 in 1 〇 2 represents the number of cells in the "n" inside the circle of FIG. 4 is described in detail later. Referring to Fig. 5, there is shown a second embodiment of the present invention, which illustrates an implementation architecture in which the number of branch layers l3〇3〇7i 2 is two layers. Referring to Fig. 6, there is shown a third embodiment of the present invention, which illustrates an implementation architecture in which the number of branching layers is three layers. From Figures 5 and 6 = the more branches, the higher the parallelism and the faster the search speed. In the figure, the inside of each circle represents the _ syllabus. Its structure is equivalent to the "n" inside the circle in Fig. 4, which is no longer praised. + In addition, referring to Fig. 7, FIG. 7 is a diagram showing the inside of the circle of the fourth, fifth, sixth, second, third, and third embodiments, that is, a single level of entanglement 1〇1. Fig. 5 and Fig. 6 show a single comparison line. In general applications, there are usually thousands of data in CAM. It can be seen that the load of the pulse signal (Φ) is quite heavy, so the clock The power of the signal buffer is also considerable. The tree-AND type comparison circuit of the present invention does not increase the load of the clock, as shown in Figures 4, 5, and 6, the clock signal (φ) 曰 ^ is loaded. The three architectures are the same, so the clock load does not increase, so the inner valley can be better than the power consumption in the memory. In addition, the tree and type comparison circuit is used for each level. The evaluation action depends on the comparison result of the previous stage. Therefore, the advantage of the low power of the existing NAND type comparison circuit is also preserved. Referring to FIG. 8, the tree AND type alignment circuit of the present invention is implemented in a 128-bit width. The content of the contentable memory (Cam: content Addressable Memory), where the content can be addressed to the memory package A write/search buffers 130, an address decoder 140, a bit-line load, and a content addressable memory cell element i6〇 (c〇ntent Addressable Memory Cell: CAM Cell for short), and a matching circuit 1303071 match circuit. The write/search buffer 130, the address decoder 140, the bit line load 150 and the The comparison circuit 170 is respectively connected to the content addressable memory cell 160. When the CAM performs a write operation, blen is a high level. At this time, the load bit line 150 is turned off. The write and search buffers 130 send the value of the content addressable memory cell 160 (CAM Cell) to the write bit line (WBLP, WBLN). The address decoder 140 drives the decoded selected word line to a high level; at this time, the value of the written bit line (WBLP, WBLN) can be written into the content. Addressing memory cell 160 (CAM Cell). When the content can address the memory for comparison The externally input data is sent to the search bit line (SBLP, SBLN) and the value stored in the content addressable memory cell 160 (CAM Cell) via the write and search buffers 130 (write and search buffers). In comparison, if the value stored in the content addressable memory matches the externally input data, the point in the content addressable memory cell 160 (CAM Cell) will be charged via the search bit line (SBLP, SBLN). To high standards. Referring to FIG. 9 and FIG. 10, FIG. 9 is an enlarged view of a single AND logic gate in the matching circuit 170 of FIG. 8, wherein A, B, C, D, E, and F represent a total of six. The content can address the memory cell elements; the 10th figure is the equivalent circuit of Figure 9. If the cell meta 102 (Cell) alignment result in the single-stage AND gate 101 is all matched, the transistor gate (G) of N1, N2, N3, N4, N5, and N6 in the AND gate 101 is set to be high. For the level, the LML (Local Match Line) is Φ 11 1303071 ^ when the level is: the level (that is, the phase of the circuit evaluation), the output is the high level = combined:: evaluation action, Therefore, when the whole object '', ML〇ut<n> in the figure is output as a high level. The content of the addressable memory, day, < in Fig. 8 will be explained in Fig. 11. When the external ci〇ek is at a high level, φ is a low level, this
時外。P.的貝料（Sln<() : 127>)經由該寫入/搜尋緩衝器 13〇(Write and Search buffers)送入搜尋位元線（SBLp、 SBLN) ’並與内容可定址記憶體中每個位摘儲存資料作 比對。當clock位於負緣時’ φ進入正緣，此時，樹狀and 型比對線開始做求值動作，將每—級中每個位元的比對結 果結合並傳送至下—級，而整個内容可定址記憶體的比對 結果最後會同時輸出至MLQUt<255 : 〇>。 參照第12圖，是本發明之樹狀AND型比對電路實現 於積體電路中的佈局方式示意圖。第13圖是第12圖之範 圍300内的線路圖。整個比對電路包含數個and邏輯閘 101、101’，每一個AND邏輯閘1〇1、ι〇ι，包含數個細胞 元102 102與負載200、200’（參閱第1〇圖）。本發明是將 每一個AND型比對電路以併貼方式相鄰佈設，不同群組 的該等AND型比對電路則透過負載2〇〇、2〇〇，相連接。 至於不同比對電路群組彼此間的連接方式（參閱第13 圖），是將該等負載200、200,以跳線方式相互間隔相連接， 第12圖的第一組負載2〇〇不列入計算的情形下，奇數位 置的該等負載200的一輸出端201與下一奇數位置的該等 負載200的一輸入端202相連接。偶數位置的該等負載 12 1303071 200的輸出端20 Γ與下一偶數位置的該等偶數位置的該 等負載200,的一輸入端2〇2,相連接。藉由此跳線連接方 式使彳于各個不同群組之AND型比對電路（每一個AND 型比對電路包含數個細胞元1〇2、1〇2，與一負載2〇〇、2〇〇，) 得以並貼連接。 本發明藉由第12、13圖之細胞元（Cell)與負載（L〇ad) 之相互併貼的佈局方式，不但使佈局結構簡潔、易實現， 而LML之利用跳蛙（Leap_fr〇g)的跳線方式，使得每一級間 跳線的雜散電容具有一致性，讓每一級的延遲時間更相 近。 值得一提的是，因樹狀and型比對電路具有高度的 佈局規律性，使得採用本發明之AND型比對電路的内容 可定址記憶體（CAM)的編譯器（Compiier)在開發上更加容 易。 根據上述，本發明之可應用於内容可定址記憶體之樹 狀AND型比對電路裝置具有下列優點： 1 ·本發明使用and型的比對電路，可減少電路轉態變 動的機會，大幅減少功率消耗，相較於現有NOR型比對 電路之功效消耗大的缺失，本發明可獲得低消耗功率之功 效。 2·本發明因採用樹狀連結的AND型比對電路結構，因 不增加時脈訊號（Φ)的負載，所以不但功率消耗不會提 升，搜尋速度也隨之加快，相較於現有NAND型比對電路 搜尋速度慢的缺失，本發明之低功率與高速度的AND型 •1303071 比對電路’對於現㈣容可定址記憶體（cam)之應用可以 得到相當的助益。 3·樹狀AND型比對電路適宜以併貼方式佈設於積體 ，路中，在電路設計上，採㈣線方式（Leap_fmg ••跳娃） 完成連接，不但容易實施且方便快速，且提高佈局之規律 性，使得每一級間跳線的雜散電容一致，而使每一級的延 遲時間更相近，因此也特別適用於記憶體編譯器（Mem〇ry Compiler)的開發運用，並有助於縮短編譯⑽沖㈣的 開發時間。 更值得一提的是，本發明可應用於内容可定址記憶體 之樹狀AND型比對電路裝置具有低消耗功率、高搜尋速 度的優點，於應用上，可以增進網路路由器、硬體搜尋引 擎、樣本比對器等應用之性能，以提高產業運用之好處。 雖然本發明已以一實施例揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内’當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1圖是現有PF-CDPD AND型電路圖。 第2圖是現有PF-CDPD AND型加速版電路圖。 1303071 第3圖是繪示本發明第一實施例的可應用於内容可定 址記憶體之樹狀AND型比對電路裝置的電路圖。 第4圖是繪示本發明第一實施例的單層分枝比對電 路。 第5圖是繪示本發明第二實施例之兩層分枝的比對電 路。 第6圖是繪示本發明第三實施例之三層分枝的比對電 路。 第7圖是繪示第4圖、第5圖與第6圖之其中一個AND 型比對電路的等效電路。 弟8圖疋繪示本發明樹狀and型比對電路實現於内 容可定址記憶體的電路架構圖。 第9圖是繪示第8圖中之該比對電路的其中一個and 邏輯閘的放大圖。 第10圖是繪示第9圖AND邏輯閘的等效電路圖。 弟11圖是繪示本發明之時序圖。 第12圖是繪示本發明實施於積體電路板上的佈局圖。 第13圖是繪示f 12圖之其中三組and型比對電路 與三組負載以跳線連接的佈局結構。Time is out. The bedding material of P. (Sln<(): 127>) is sent to the search bit line (SBLp, SBLN) via the write/search buffers 13(' and is stored in the content addressable memory Each location is stored for comparison. When the clock is at the negative edge, 'φ enters the positive edge. At this time, the tree and type comparison lines begin to perform the evaluation operation, and the comparison results of each bit in each level are combined and transmitted to the lower level. The alignment of the entire content-addressable memory is finally output to MLQUt<255: 〇>. Referring to Fig. 12, there is shown a schematic diagram of a layout pattern of the tree-like AND type comparison circuit of the present invention implemented in an integrated circuit. Figure 13 is a circuit diagram within the range 300 of Figure 12. The entire alignment circuit includes a plurality of and logic gates 101, 101', each AND logic gate 1 〇 1, ι ι, containing a plurality of cell 102 102 and loads 200, 200' (see Figure 1). In the present invention, each of the AND type comparison circuits is adjacently arranged in a side by side manner, and the AND type type comparison circuits of different groups are connected through the load 2〇〇, 2〇〇. As for the connection mode of different comparison circuit groups (refer to FIG. 13), the loads 200 and 200 are connected in a jumper manner, and the first group of loads in FIG. 12 is not listed. In the case of calculations, an output 201 of the loads 200 at odd locations is coupled to an input 202 of the loads 200 at the next odd location. The outputs 20 of the even-numbered positions 12 1303071 200 are connected to an input 2 〇 2 of the loads 200 of the even-numbered positions at the even-numbered positions. By means of the jumper connection method, the AND type comparison circuit of each different group is used (each AND type comparison circuit includes several cell elements 1〇2, 1〇2, and a load 2〇〇, 2〇) 〇,) can be connected and attached. The present invention adopts the layout manner of the cells and the load (L〇ad) of the figures 12 and 13 to not only make the layout structure simple and easy to implement, but also utilizes the leapfrog (Lap_fr〇g) of LML. The jumper mode makes the stray capacitance of the jumpers between each level consistent, making the delay time of each level more similar. It is worth mentioning that the compiler of the content-addressable memory (CAM) using the AND type comparison circuit of the present invention is more developed due to the high layout regularity of the tree-type comparison circuit. easily. According to the above, the tree-shaped AND type matching circuit device applicable to the content addressable memory of the present invention has the following advantages: 1. The present invention uses the AND type comparison circuit to reduce the chance of circuit transition change and greatly reduce The power consumption can achieve the effect of low power consumption compared to the lack of power consumption of the existing NOR type comparison circuit. 2. The present invention adopts a tree-connected AND type comparison circuit structure, and since the load of the clock signal (Φ) is not increased, the power consumption is not increased, and the search speed is also accelerated, compared with the existing NAND type. In contrast to the lack of slow search speed of the circuit, the low power and high speed AND type 1303051 comparison circuit of the present invention can be quite useful for the application of the current (four) capacitive addressable memory (cam). 3. The tree-shaped AND type comparison circuit is suitable to be arranged in the form of a joint, in the road, in the circuit design, the (four) line method (Leap_fmg •• jump baby) is completed, not only easy to implement, but also convenient and fast, and improve The regularity of the layout makes the stray capacitance of the jumpers between each level consistent, and the delay time of each level is more similar, so it is also particularly suitable for the development and application of the memory compiler (Mem〇ry Compiler) and helps Shorten the development time of compiling (10) Chong (4). It is worth mentioning that the present invention can be applied to the tree-AND type comparison circuit device of the content addressable memory, which has the advantages of low power consumption and high search speed, and can improve network router and hardware search in application. The performance of applications such as engines and sample comparators to improve the benefits of industrial applications. Although the present invention has been disclosed in an embodiment of the present invention, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious, the detailed description of the drawings is as follows: FIG. 1 is a conventional PF-CDPD AND type circuit diagram. Figure 2 is a circuit diagram of the existing PF-CDPD AND type accelerated version. 1303071 Fig. 3 is a circuit diagram showing a tree-like AND type comparison circuit device applicable to content addressable memory according to the first embodiment of the present invention. Fig. 4 is a view showing a single layer branching comparison circuit of the first embodiment of the present invention. Fig. 5 is a view showing a two-layer branching comparison circuit of the second embodiment of the present invention. Fig. 6 is a view showing a three-layer branching comparison circuit of the third embodiment of the present invention. Fig. 7 is a diagram showing an equivalent circuit of one of the AND type comparison circuits of Figs. 4, 5, and 6. Figure 8 illustrates the circuit architecture of the tree-and-type comparison circuit implemented in the content addressable memory of the present invention. Figure 9 is an enlarged view showing one of the AND logic gates of the comparison circuit in Figure 8. Fig. 10 is an equivalent circuit diagram showing the AND logic gate of Fig. 9. Figure 11 is a timing diagram showing the present invention. Figure 12 is a layout diagram showing the implementation of the present invention on an integrated circuit board. Fig. 13 is a view showing a layout structure in which the three sets of the type-matching circuit and the three sets of loads are connected by jumpers in the figure f12.
15 1303071 【主要元件符號說明】 100 ： AND型比對電路群組 101 ： AND閘 102 ： 細胞元 1021 :N型電晶體 1011 :輸入端 111 : 輸入端 120 ： 最後級AND邏輯閘 113, •細胞元的輸入端 130 ： 寫入/搜尋緩衝器 150 ： 負載位元線 170 ： 比對電路 200, :比對電路之負載 201， :輸出端 202, :輸入端 400 : 比對電路 411 : N型電晶體15 1303071 [Description of main component symbols] 100 : AND type comparison circuit group 101 : AND gate 102 : Cell element 1021 : N type transistor 1011 : Input terminal 111 : Input terminal 120 : Last stage AND logic gate 113 , • Cell Input 130 of the element: write/search buffer 150: load bit line 170: comparison circuit 200, : load 201 of the comparison circuit, output terminal 202, input terminal 400: comparison circuit 411: N type Transistor
100’ ： AND型比對電路群組 101，： AND 閘 102’ ：細胞元 1012 :輸出端 11 〇 :第一 AND邏輯閘 112 :輸出端 113 ··細胞元的輸入端 121 :輸入端 140 :位址解碼器 160:内容可定址記憶體細胞 元 2〇0 :比對電路之負戴 201 :輸出端 202 :輸入端 410 :動態N型邏輯閑100': AND type comparison circuit group 101,: AND gate 102': cell element 1012: output terminal 11: first AND logic gate 112: output terminal 113 · cell input terminal 121: input terminal 140: Address Decoder 160: Content Addressable Memory Cell Element 2〇0: Negative Wear of Alignment Circuit 201: Output 202: Input 410: Dynamic N-type Logic
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