1302013 09665twf2.doc/d 97-03-31 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種高密集度（high density)半導體 元件，且特別有關在一微晶片（microchip)上一種隔離半導 體元件的方法。 【先前技術】 成功的高密集度積體電路的成功產品如處理器 (processor)、控制器（controller)與記憶體（memory)均依賴 隔離一電路中的個別元件與圍繞其之元件的能力而定。近 來的積體電路包括有數百萬形成於一單一半導體基底上的 密集堆疊電晶體（densely packed transistor)、二極體 (diode)、電容器（capacitor)以及電阻器（resistor)。而個別 的元件被與其他元件隔離，以防止如漏電流（leakage current)或受鄰近元件干擾（cross-talk)等情形發生。而用 於電性隔離的兩種標準方法是矽的局部氧化法（local oxidation of silicon，簡稱LOCOS)以及淺溝渠隔離法 (shallow trench isolation，簡稱 STI)。 在矽的局部氧化法製程中，係在半導體基底的非主動 區域（non-active region)中成長場氧化物（field oxide)。這 個隔離製程已廣泛應用於前一世代（previous generation) 之積體電路的金氧半導體（metal oxide semiconductor，簡 稱M0S)元件中，如N型金氧半導體（NMOS)、P型金氧半 導體（PM0S)以及互補式金氧半導體(CMOS)元件。然而， 矽的局部氧化法之技術包含兩個限制，而使元件尺寸明顯 5 1302013 09665twf2.doc/d 97-03-31 縮減。在矽的局部氧化法之製程中，會在場氧化區域邊緣 發生成長不完全（undergrowth)如鳥嘴（bird beak)的氧化 物，而造成對元件密集度而言不想要的限制。因此，矽的 局部氧化法之製程在積體電路的製造中有效的元件最大數 量將被限制。場氧化物也會垂直延伸而在主動與非主動區 域間形成非平面地形（non-planar topography)。這個非平 面地形將導致後續微影製程中的困難度，譬如影像的解析 問題、由於這些限制，矽的局部氧化法之技術會無法用於 如約〇·35微米以下的元件尺寸之半導體製程內。 一種更適合元件尺寸低於0·35微米之超大積體（ultra large scale integrated，簡稱ULSI)電路製造的製程是淺溝 渠隔離法。在淺溝渠隔離法之製程中，先於一半導體基底 中形成一溝渠’其步驟是先形成保護層，然後蝕刻穿過部 分位於欲形成隔離溝渠的部位之保護層。接著，施行許多 步驟以用適當的介電質或介電質的化合物(combi nation)塡 入溝渠中。藉由幾乎垂直蝕刻形成尺寸在微米或次微米之 範圍內的溝渠’可維持一元件之密集陣列（dense array)結 構之有用區域(valuable area)。而一種用於形成隔離溝渠 的標準方法是沉積1/濕式鈾刻/沉積2 (deposition彳，wet etch, deposition 2)技術，包括在—溝渠內部形成—第一溝 渠塡充層(fill layer)，再施行一濕式蝕刻，以去除部分第一 溝渠塡充層，隨後形成—第二溝渠塡充層，以完全塡滿溝 渠。 一 因爲淺溝渠隔離法在半導體基底上所需之面積很 小，而使兀件能更密集分布，所以其已成爲超大積體電路 6 1302013 09665twf2.doc/d 97-03-31 的較佳隔離方法。而較密集的分布能在電路製造上增進其 速度與功率。淺溝渠隔離結構也具有相當平的地形，可幫 助後續微影製程並減少失誤。 然而，在淺溝渠隔離法的製造中尙有未解決的問題仍 舊限制的元件密集度。有關淺溝渠隔離技術的其中一個問 題是在溝渠塡入層中的空隙（void)或裂縫（seam)。這些空 隙或裂縫舉例來說是在約0.25微米或以下之尺寸發生，或 是在約0.4微米以上的深度發生。這些裂縫會不利於鄰近 元件的電性特徵，進而成爲元件失誤的途徑（path)。因此， 需要創造相當窄以及相當深的無裂縫形成之溝渠隔離結 【發明内容】 有鑒於此，本發明提供一種製造隔離溝渠的方法，以 減少或消除溝渠中形成裂縫與空隙的可能性（possibility) 或是或然性（probability)，而滿足上述需求。因此，本發明 的隔離溝渠之形成可降低鄰近元件中的失誤。 在此揭露的發明藉由於塡充層之間施行一濕式旋蝕 刻處理來提供有效控制裂縫或空隙的形成之方法。這種濕 式旋蝕刻處理可選擇提供橫向鈾刻率或垂直蝕刻率，以製 造出或是接近極微小或所欲之高寬比（aspect ratio)。 根據本發明提出在一半導體基底上的一積體電路上 的一種製造至少一隔離溝渠的方法，包括(a)提供一半導體 基底，其具有一墊氧化層（pad oxide layer)、一氮化層以及 一圖案化光阻層。（b)去除部分氮化層、墊氧化層與半導體 7 1302013 97-03-31 09665twf2.doc/d 基底，以形成至少一溝渠。（C)去除光阻層，以及(d)在溝渠 內部形成一第一塡充層。隨後(e)以濕式旋蝕刻回蝕刻第— 塡充層。⑴於第一塡充層上形成—第二塡充層。而在去除 先阻層之後可於溝渠底部（bottom)與內壁（sidewall)上形成 一氧化襯層（oxide liner)。 依據本發明提出另一種形成至少一隔離溝渠的方 法，包括提供一半導體基底，其具有至少一溝渠位於其中， 而溝渠有一溝渠側壁與一溝渠底部。然後，在溝渠內部形 成一第一塡充層。隨後，施行一蝕刻製程，其中以較從溝 渠底部大之速率或是較溝渠底部大之程度（extent)從溝渠 側壁去除部分第一塡充層。之後，於第一塡充層上形成一 第二塡充層。 去除部分氮化層、墊氧化層與半導體基底的方法例如 是一非等向性蝕刻（anisotropic etch)或一等向性蝕刻之後 的非等向性蝕刻。而第一塡充層可包括用矽烷(silane, SiH4) 之筒密度電獎化學氣相沉積製程（high density plasma chemical vapor deposition，簡稱 HDPCVD)所形成的氧化 物。可用矽烷與氧（〇2)的混合物形成氧化物，其中矽烷流 量(flow)從50到100 SCCM、氧的流量則從80到150 SCCM。沉積時間可從10秒到30秒。而第二塡充層也可 包括化學氣相沉積製程（CVD)、電漿化學氣相沉積製程 (PECVD)或低壓化學氣相沉積製程（LPCVD)所形成的氧化 物。第二塡充層之形成包括流入80到140 SCCM之矽烷 與130到200 SCCM的氧之第一步驟，之後還有流入110 8 1302013 09665twf2.doc/d 97-03-31 到180 SCCM之矽烷與180到250 SCCM的氧之第二步 驟。 而至少一溝渠的尺寸如寬度是在0.25到0.18微米之 間。在濕式旋蝕刻期間的晶圓（wafer)旋轉速率(spin speed) 可被改變或調整，以製出一較寬的頂部溝渠尺寸與一較小 的階梯高度(step height)，藉以產生一較低高寬比的部分 塡入溝渠（partially-filled trench)。而濕式旋蝕刻可包括用 一緩衝氧化物蝕刻(buffered oxide etch，簡稱BOE)劑與 稀氫氟酸(diluted hydrofluoric acid，簡稱DHF)的混合物 (mixture)，且其組成範圍從約10:1到約500:1。在濕式旋 蝕刻期間被去除的氧化物是在100埃到300埃之間。在濕 式旋蝕刻期間，晶圓可被水平放置與水平旋轉，或是被垂 直放置與垂直旋轉。而且，至少一溝渠包括數個溝渠。 本發明又提出一種方法，包括(a)決定隔離溝渠的一幾 何特徵（geometrical characteristic)，以及（b)產生一濕式 旋蝕刻配方，用於一沉積1/濕式旋鈾刻/沉積2(dep〇Sm〇n 1, wet spin etch, deposition 2)溝塡順序（trench filling sequence)，其中濕式旋鈾刻配方是依照預定的幾何特徵 所產生的。而幾何特徵可以是隔離溝渠的高寬比。濕式旋 飩刻配方更可包括選擇一旋轉速率來訂立，其中具高高寬 比的隔離溝渠可選擇較大之旋轉速率，而具相對較小高寬 比的隔離溝渠則可選擇較小之旋轉速率。 一種不需按先後順序的塡充隔離溝渠之方法，可包括 (a)施行一沉積1/濕式旋飩刻/沉積2溝塡技術，以塡充具 1302013 09665twi2.doc/d 97-03-31 一第一高寬比的一第一溝渠，以及（b)施行一沉積1/濕式旋 触刻/丨几積2溝填技術’以塡充具一^第一局寬比的一^第一^溝 渠，其中第一高寬比大於第二高寬比，而且在(a)中之濕式 旋蝕刻的旋轉速率大於在（b)中之濕式旋蝕刻的旋轉速率。 於此揭露的任何特徵或特徵之結合是包含於本發明 之範圍中，其中從內文與說明書中以及由熟悉此技術者的 知識均可明顯瞭解其所提供之包含在任何結合的特徵並非 互相矛盾。本發明其他優點與觀念將於接下來的描述與申 請專利範圍中詳述。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 【實施方式】 本發明之較佳實施例將詳細描繪以作爲參考，並以附 圖圖解。無論在哪裡只要在圖示中使用相同或類似的參考 標號，在說明書中就是與其相關的相同或類似的部分。請 注意圖不是非常簡化的形式且非精準的比率。於此揭露的 参考資僅用於方便與明晰的目的，如使用與圖示有關的方 向性用語像是頂部、底部、左、又、上、下、在上、在下、 低於、後面以及前面。這些方向性用語在任何方法上並不 是用來限制本襞明的範圍。 雖然於此揭露有關某一種圖解的實施例，但是應知這 些實施例是用來舉例而非限定。之後詳細說明的目的雖然 是詳述示範的實施例，但實施例的修改、選擇與同等物應 10 1302013 97-03-31 09665twf2.doc/d 被理解爲之後的申請專利範圍所定義的本發明精神與範 圍。舉例來說，熟悉此技藝者在實施本發明時應知也可用 除氧化物之其餘介電材質替代氧化物來塡充隔離溝渠 (isolation trench)。同樣也可在隔離溝渠中用除氧化物之 其餘襯層（liner)來替代氧化襯層。 已知並理解於此所描述之製造步驟與結構並不包含 積體電路製造的完整製程。本發明也可施行於慣例用於技 術上的各類積體電路製造技術，且於此包含的一般施行製 程步驟僅用於提供本發明的理解。 請特別參照第1圖，第1圖是本發明在中間製程階段 (intermediate processing stage)的一積體電路之剖面示 意圖。這種積體電路包括一半導體基底30、一墊氧化層（pad oxide layer)32、一氮化層34以及一光阻層37。而半導體基 底30例如是砍、砂鍺（silicon germanium)或砷化鎵（gallium arsine)，且以標準方法準備如清洗晶圓（wafer)、沿著晶圓 表面產生一裸露區（denuded zone)等。然後，在半導體基 底30上成長厚度約100埃到250埃之墊氧化層32,或藉由化 學氣相沉積製程（chemical vapor deposition，簡稱CVD) 來沉積適當厚度的墊氧化層32。 氮化層3 4如氮化矽能在墊氧化層3 2上藉由化學氣相 沉積製程沉積。而氮化層34可利用相當慢速的氧化與擴 散，於隔離溝渠形成期間防止半導體基底3〇之主動區不希 望氧化的情形發生。氮化層34也可在未來的製程步驟期間 作爲阻障層（barrier layer)或是硏磨終止層（polishing 1302013 97-03-31 09665twf2.doc/d1302013 09665twf2.doc/d 97-03-31 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a high density semiconductor component, and more particularly to a microchip. A method of isolating a semiconductor component. [Prior Art] Successful products of successful high-density integrated circuits, such as processors, controllers, and memories, rely on the ability to isolate individual components in a circuit from the components surrounding it. set. Recent integrated circuits include millions of densely packed transistors, diodes, capacitors, and resistors formed on a single semiconductor substrate. Individual components are isolated from other components to prevent situations such as leakage current or cross-talk. The two standard methods for electrical isolation are local oxidation of silicon (LOCOS) and shallow trench isolation (STI). In the local oxidation process of germanium, a field oxide is grown in the non-active region of the semiconductor substrate. This isolation process has been widely used in metal oxide semiconductor (M0S) devices of previous generations of integrated circuits, such as N-type gold oxide semiconductors (NMOS) and P-type gold oxide semiconductors (PM0S). And complementary metal oxide semiconductor (CMOS) components. However, the technique of local oxidation of niobium contains two limitations, which make the component size significantly reduced by 5 1302013 09665twf2.doc/d 97-03-31. In the process of partial oxidation of bismuth, undergrowth of oxides such as bird beaks occurs at the edge of the field oxidation region, causing undesirable restrictions on component density. Therefore, the maximum number of components effective in the fabrication of the integrated circuit of the tantalum local oxidation process will be limited. Field oxides also extend vertically to form non-planar topography between active and inactive regions. This non-planar topography will lead to difficulties in subsequent lithography processes, such as image resolution problems. Due to these limitations, the technique of 局部 local oxidation can not be used in semiconductor processes such as component sizes below about 35 μm. . A process that is more suitable for the manufacture of ultra large scale integrated (ULSI) circuits with component sizes below 0. 35 microns is shallow trench isolation. In the shallow trench isolation process, a trench is formed prior to a semiconductor substrate. The step is to first form a protective layer and then etch the protective layer over the portion where the isolation trench is to be formed. Next, a number of steps are performed to break into the trench with a suitable dielectric or dielectric compound. A trench having a size in the range of micrometers or submicrometers formed by almost vertical etching can maintain a valuable area of a dense array structure of an element. A standard method for forming isolated trenches is to deposit a 1/wet etch (deposition 彳, deposition 2) technique, including forming inside the trench - a first trench fill layer Then, a wet etching is performed to remove part of the first trench filling layer, and then a second trench filling layer is formed to completely fill the trench. Because the shallow trench isolation method requires a small area on the semiconductor substrate, and the component can be more densely distributed, it has become a better isolation of the oversized integrated circuit 6 1302013 09665twf2.doc/d 97-03-31. method. A denser distribution can increase its speed and power in circuit manufacturing. The shallow trench isolation structure also has a fairly flat topography that can help with subsequent lithography processes and reduce errors. However, there are unresolved issues in the manufacture of shallow trench isolation methods that still limit the component density. One of the problems with shallow trench isolation techniques is the void or seam in the trench's intrusion layer. These voids or cracks occur, for example, at a size of about 0.25 microns or less, or at a depth of about 0.4 microns or more. These cracks can be detrimental to the electrical characteristics of adjacent components and thus become a path for component errors. Therefore, there is a need to create a relatively narrow and relatively deep trench-free trench isolation junction. SUMMARY OF THE INVENTION In view of the above, the present invention provides a method of fabricating an isolation trench to reduce or eliminate the possibility of cracks and voids in the trench (possibility) ) or probability, to meet the above needs. Thus, the formation of the isolation trenches of the present invention can reduce errors in adjacent components. The invention disclosed herein provides a means of effectively controlling the formation of cracks or voids by performing a wet etch process between the entangled layers. This wet spin etch process can optionally provide a lateral uranium engraving rate or a vertical etch rate to produce or approach a very small or desired aspect ratio. A method of fabricating at least one isolation trench on an integrated circuit on a semiconductor substrate in accordance with the present invention includes (a) providing a semiconductor substrate having a pad oxide layer, a nitride layer And a patterned photoresist layer. (b) removing a portion of the nitride layer, the pad oxide layer, and the semiconductor 7 1302013 97-03-31 09665twf2.doc/d substrate to form at least one trench. (C) removing the photoresist layer, and (d) forming a first buffer layer inside the trench. Subsequently, (e) the first ruthenium layer is etched back by wet spin etching. (1) Forming a second filling layer on the first filling layer. An oxide liner can be formed on the bottom and the sidewall of the trench after the first resist layer is removed. Another method of forming at least one isolation trench is provided in accordance with the present invention, comprising providing a semiconductor substrate having at least one trench therein, the trench having a trench sidewall and a trench bottom. Then, a first filling layer is formed inside the trench. Subsequently, an etch process is performed in which a portion of the first ruthenium layer is removed from the sidewall of the trench at a greater rate than the bottom of the trench or an extent greater than the bottom of the trench. Thereafter, a second buffer layer is formed on the first buffer layer. The method of removing a portion of the nitride layer, the pad oxide layer, and the semiconductor substrate is, for example, an anisotropic etch or an anisotropic etch after an isotropic etch. The first buffer layer may include an oxide formed by a high density plasma chemical vapor deposition (HDPCVD) of silane (SiH4). A mixture of decane and oxygen (?2) can be used to form an oxide wherein the decane flow is from 50 to 100 SCCM and the oxygen flow is from 80 to 150 SCCM. The deposition time can range from 10 seconds to 30 seconds. The second buffer layer may also include an oxide formed by a chemical vapor deposition process (CVD), a plasma chemical vapor deposition process (PECVD), or a low pressure chemical vapor deposition process (LPCVD). The formation of the second buffer layer includes a first step of flowing 80 to 140 SCCM of decane with 130 to 200 SCCM of oxygen, followed by a flow of decane with 110 8 1302013 09665 twf2.doc/d 97-03-31 to 180 SCCM. The second step of oxygen from 180 to 250 SCCM. At least one trench, such as a width, is between 0.25 and 0.18 microns. The wafer spin speed during wet spin etching can be changed or adjusted to produce a wider top trench size and a smaller step height to create a comparison. The low aspect ratio portion is partially-filled trench. The wet spin etching may include a mixture of a buffered oxide etch (BOE) agent and a diluted hydrofluoric acid (DHF), and the composition thereof ranges from about 10:1. It is about 500:1. The oxide removed during wet spin etching is between 100 angstroms and 300 angstroms. During wet spin etching, the wafer can be placed horizontally and horizontally, or vertically and vertically. Moreover, at least one trench comprises a plurality of trenches. The present invention further provides a method comprising (a) determining a geometrical characteristic of the isolation trench, and (b) producing a wet spin-etching recipe for a deposition 1/wet uranium engraving/deposition 2 ( Dep〇Sm〇n 1, wet spin etch, deposition 2) A trench filling sequence in which a wet uranium engraving formulation is produced in accordance with predetermined geometrical features. The geometric feature can be the aspect ratio of the isolation trench. The wet rotary engraving recipe may further include selecting a rotation rate to be established, wherein the isolation trench having a high aspect ratio may select a larger rotation rate, and the isolation trench having a relatively small aspect ratio may select a smaller one. Rotation rate. A method for filling an isolation trench without prioritization may include (a) performing a deposition 1/wet rotary enthalpy/deposition 2 gully technique to fill the apparatus 1302013 09665twi2.doc/d 97-03- 31 a first ditch of a first aspect ratio, and (b) performing a deposition 1/wet-spinning engraving/single-splitting 2 ditch filling technique to fill a ^1 first width ratio The first trench, wherein the first aspect ratio is greater than the second aspect ratio, and the rate of rotation of the wet spin etch in (a) is greater than the rate of spin of the wet spin etch in (b). Combinations of any of the features or features disclosed herein are included in the scope of the present invention, and it is apparent from the text and the description and the knowledge of those skilled in the art that the features included in any combination are not mutually exclusive. contradiction. Other advantages and concepts of the present invention will be described in detail in the following description and claims. The above and other objects, features, and advantages of the present invention will become more fully understood from The examples will be described in detail as a reference and illustrated in the accompanying drawings. Wherever the same or similar reference numerals are used in the drawings, the same or similar parts in the description are. Please note that the graph is not a very simplified form and a non-precise ratio. The reference materials disclosed herein are for convenience and clarity only, such as using the directional terms associated with the illustrations such as top, bottom, left, back, up, down, up, down, below, back, and front. . These directional terms are not intended to limit the scope of this description in any way. Although an embodiment of the invention has been disclosed herein, it is understood that these embodiments are by way of example and not limitation. The detailed description is to clarify the exemplary embodiments, but the modifications, selections, and equivalents of the embodiments should be understood as the invention defined by the scope of the following claims. Spirit and scope. For example, those skilled in the art will appreciate that the isolation of the isolation trench can be accomplished by replacing the oxide with the remaining dielectric material of the oxide. It is also possible to replace the oxide liner with the remaining liner of the oxide in the isolation trench. It is to be understood and understood that the fabrication steps and structures described herein do not include a complete process for the fabrication of integrated circuits. The present invention is also applicable to various types of integrated circuit manufacturing techniques conventionally used in the art, and the general execution process steps included herein are merely for providing an understanding of the present invention. In particular, reference is made to Fig. 1, which is a schematic cross-sectional view of an integrated circuit of the present invention in an intermediate processing stage. The integrated circuit includes a semiconductor substrate 30, a pad oxide layer 32, a nitride layer 34, and a photoresist layer 37. The semiconductor substrate 30 is, for example, chopped, silicon germanium or gallium arsine, and is prepared by standard methods such as cleaning a wafer, creating a denuded zone along the surface of the wafer, and the like. . Then, a pad oxide layer 32 having a thickness of about 100 angstroms to 250 angstroms is grown on the semiconductor substrate 30, or a pad oxide layer 32 of a suitable thickness is deposited by a chemical vapor deposition (CVD). A nitride layer 34 such as tantalum nitride can be deposited on the pad oxide layer 32 by a chemical vapor deposition process. The nitride layer 34 can utilize relatively slow oxidation and diffusion to prevent the active region of the semiconductor substrate 3 from undesired oxidation during isolation trench formation. The nitride layer 34 can also serve as a barrier layer or a honing stop layer during future process steps (polishing 1302013 97-03-31 09665twf2.doc/d
Stop)。在沉積氮化層34之前，於晶圓上成長或沉積的墊氧 化層32可作爲—緩衝物（buffe〇，藉以緩和半導體基底3〇 與氮化層34之間因爲譬如不同膨脹係數（c〇efficient of expansion)之因素所造成的應力（stress)。接著，可提供光 阻層37至氮化層34上，並且以相關的已知微影原理來圖案 化光阻層37。於本實施例中，圖案化光阻層37可具有從約 〇·1微米到約1微米寬的開口，且爲符合隔離溝渠所要求的 尺寸，其較佳範圍爲從約0.20微米到約0.24微米。 然後’請參照第2圖，利用傳統方法等向性蝕刻以及 /或是非等向性蝕刻氮化層34與墊氧化層32，譬如乾式或 濕式蝕刻，藉以去除未被光阻層37覆蓋的部分。而在第3 圖中’可持續等向性以及/或是非等向性蝕刻至半導體基底 30內，以助於形成具有約0.2微米至0.3微米深的溝渠。 每一溝渠可包括兩溝渠側壁(trench sidewall)39以及延伸 至兩溝渠側壁39間的一溝渠底部(trench bottom)41。於本 實施例中的溝渠側壁39是傾斜於溝渠底部41，且溝渠底 部41包括完全延伸在溝渠側壁39間的一大致上平坦的表 面。而形成之溝渠側壁39可與溝渠底部41例如呈約60 度到約90度的角度。在一修改過的實施例中，連結溝渠側 壁39至溝渠底部41的角落（corner)是圓的。之後可用已 知的標準剝除(strip)與灰化(ash)步驟去除光阻。 隨後，如第4圖之剖面圖所示，施行一熱氧化(thermal oxidation)製程，以於溝渠側壁39以及溝渠底部41成長一 氧化襯層(oxide line〇43。當這層氧化襯層是用來使溝渠外 12 1302013 09665twf2.doc/d 97-03-31 型變圓時，其厚度可成長至400埃與600埃之間。氧化襯 層43可供三種基本功能：溝渠外型的圓化、降低在半導體 基底30中因蝕刻所導致的應力以及保護氧化物凹陷（oxide recess)。此外這層氧化襯層43更可增進矽與二氧化矽的 界面品質（interface quality)。 第5圖是第4圖之結構在施行一第一氧化物沉積後形 成一第一氧化層45的示意圖。在兩相鄰氧化層間的邊界 (boundary)是以虛線表示。第一氧化層45可用化學氣相沉 積製程包括：高密度電漿化學氣相沉積製程（high density plasma CVD，簡稱HDPCVD)、常壓化學氣相沉積製程 (atmospheric CVD，簡稱APCVD)以及次壓化學氣相沉積 製程(sub-atmospheric CVD，簡稱SACVD)來沉積，而較 佳者係用矽烷（silane，SiH4)與氧（02)在矽烷流量(flow)從 50 至[J 100 SCCM (standard cubic centimeters per minute)、氧的流量從80到150 SCCM、沉積時間則從10 秒到30秒之高密度電漿化學氣相沉積製程來進行沉積。而 最後形成的第一氧化層45於溝渠底部41的厚度是1000 到2000埃。沉積之厚度可被調整，以使任何突出現象 (overhang phenomenon)之發生減少並且減小溝渠之高寬 比(aspect ratio)。部分形成於溝渠側壁39的第一氧化層 45可被以較溝渠下端（bottom)更快沉積於溝渠洞口邊緣 (lip)。這樣的現象會導致如再進入（reentrance)的問題，其 中溝渠之頂部將變得較下端窄。 然後，施行一選擇性蝕刻法（selective etch 13 1302013 97-03-31 09665twf2.doc/d process)，其中係以較從溝渠底部41去除大的速率或是程 度(extent)從溝渠側壁39去除部分第一氧化層45。因此， 可獲得一較寬的窗口，以利後續第二氧化層55(請參照後 續之第7a圖）之沉積。依照本發明之一觀點，被設計之第 一氧化層45的最初沉積厚度是與產生有助於無裂縫 (void-free)塡充（filling)之第二氧化層55的—溝渠輪廓 (profile)的選擇性蝕刻製程相結合。 於本實施例中，如非等向性之選擇性蝕刻製程包括一 濕式旋飩刻(wet spin etch)，其中晶圓被浸入—化學溶液 中，而較佳者係濃度在10:1到500:1之間的一緩衝氧化物 鈾刻（buffered oxide etch，簡稱BOE)劑與稀氫氟酸 (diluted hydrofluoric acid，簡稱 DHF)的混合物 (mixture)，並且於蝕刻施行時同時旋轉晶圓。晶圓可被水 平放置與水平旋轉’或是被垂直放置與垂直旋轉。於本實 施例中，濕式旋蝕刻會去除在約100埃到約300埃之間的 氧化物。當濕式飩刻施行時去旋轉晶圓，會因爲譬如化學 藥品流動中之旋轉移動（spinning motion)與變動(variance) 的離心力（centrifugal force)，而導致較多的蝕刻劑 (etchant)與溝渠側壁39相互反應，而與溝渠底部41互相 反應的蝕刻劑較少。 調整或改變旋轉速率有助於使蝕刻溝渠側壁39與溝 渠底部41之間有較佳的選擇性，藉以調整相對於地心引力 的離心力。離心力與地心引力之間的調整可被用以調節作 選擇性飩刻之化學藥品流動情形，以便在較高速率下從溝 14 1302013 97-03-31 09665twf2.doc/d 渠側壁39縮減第一氧化層45厚度，或是用較溝渠底部41 大之程度去除。舉例來說，在旋蝕刻期間在溝渠底部41 可能會有比在溝渠側壁39少的化學藥品浸泡情形 (soaking)，以及/或者會因離心力而增加的化學藥品流動而 在溝渠側壁39發生較大的蝕刻。 當晶圓被水平放置與水平旋轉時，藉由增加旋轉速率 能使相對引力（gravity)之離心力增加，以及因此使相對垂 直蝕刻率之橫向蝕刻率增加，因而減少結果的高寬比。藉 由增加旋轉速率，在溝渠側壁39頂部之第一氧化層45的 厚度可被以較溝渠側壁39下端快速以及/或是大程度地縮 減。藉由減低旋轉速率則可使關於引力之離心力降低，而 使相對於垂直蝕刻率之橫向蝕刻率降低，因而相對增加結 果的高寬比。 濕式旋蝕刻配方（recipe)是依照一個或更多預定的幾 何特徵(geometrical characteristic)所產生，譬如高寬比、 第一氧化層深度(depth)或是第一氧化層厚度。而濕式旋飩 刻配方之基本參數可以是旋轉速率。舉例來說，如果相關 的幾何特徵是高寬比，則較高高寬比的溝渠可用較大之旋 轉速率，而相對小的高寬比溝渠可選擇較小之旋轉速率。 第6a圖所示係依照本發明施行濕式旋蝕刻之後的第 一氧化層45的剖面圖，而第6b圖所示係習知完成一標準 濕式浸泡蝕刻(wet dip etch)之後的第一氧化層45結構。 本發明之濕式旋蝕刻可施行於配置在晶圓上從中心到邊緣 的任何部位上之溝渠。於一實施例中，即使改變晶圓上溝 15 1302013 09665twf2.doc/d 97-03-31 渠的位置去採用不同的離心力也可獲致類似的結果。依照 本發明之一觀點，一非常大的轉速（rotating speed)可增進 相對地心引力之離心力（如驅動力）。依照本發明之另一觀 點，化學藥品具驅動力之黏度(viscosity)特性也可降低相對 之引力。因此，濕式旋蝕刻的功效可藉改變如旋轉速率、 化學組成以及/或是黏度其中之一或更多來作調整。濕式旋 蝕刻的功效於其他實施例中也可藉改變晶圓上溝渠的位置 來調整。雖然於本實施例中以水平放置爲例，但是晶圓在 修改的實施例中也可被垂直放置。所以，濕式旋蝕刻功效 同時可藉改變晶圓之旋轉軸（spin-axis)或軸心來作調整。 在一垂直型式晶圓方位(orientation)中，相對於一水平的旋 轉軸，可在施給化學藥品時建立一預轉（pre-rotation)或慢 轉模式（slow-rotation mode)的配方，藉以降低相對的地心 引力。舉例來說在上述任一實施例中，可於預定之濕式旋 蝕刻製程中及時實施各種不同的旋轉速率、黏度以及/或是 旋轉軸於不同點上。 技術上標準的實施方法是在形成第一氧化層45之後 施行一濕式浸泡蝕刻。標準的濕式浸泡蝕刻包括將晶圓浸 入一化學槽(chemical bath) —段時間，以等向性蝕刻第一 氧化層45。蝕刻之目的主要是去拓寬溝渠側壁39間的距 離，如距離A 48與距離B 50，並伴隨溝渠深度之小幅改 變或增加，如距離C 52，因而提供一較小的高寬比(深度/ 寬度）。而溝渠側壁39最好被蝕刻成距離A 48大於距離B 5〇 ’以抵抗再進入（reentrance)的問題。 16 1302013 97-03-31 09665twf2.doc/d 比較過第6a圖與第6b圖可知本發明之濕式旋蝕刻的 優點。使用濕式旋蝕刻(第6a圖）代替傳統濕式浸泡蝕刻(第 6a圖）能夠藉由選擇性地增加距離A 48或將其增至最大’ 同時降低距離C 52或將其減至最少，以減少或消除高寬比 之問題。濕式旋飩刻還可減少或消除窄溝渠之再進入 (reentrance)的問題。 藉由降低或將高寬比減至最少，可避免與具高高寬比 之溝渠相關聯的問題。因爲除了溝渠基底41上垂直的沉積 速率外，還需考慮到溝渠側壁39上橫向的沉積速率’而發 生上述問題。沿溝渠側壁39上部分的沉積速率係高於溝渠 側壁39或底部41之較低部分。因此溝渠也許會被堵塞或 是堵住溝渠側壁39的上部，而在完全塡充溝渠前使反應物 無法到達溝渠較低部分。所以會形成裂縫或空隙’致使鄰 近被影響的溝渠之元件中產生電性失誤（electrical faHure) 〇 第7a圖與第7b圖分別顯示先前於第6a圖與第6b 圖中所示的隔離溝渠在施行一第二氧化物沉積後形成一第 二氧化層55的剖面圖。施行第二氧化沉積可使用低壓化學 氣相沉積製程(丨〇w pressure CVD，簡稱LPCVD)、咼密度 電漿化學氣相沉積製程或是電漿化學氣相沉積製程 (plasma enhanced CVD，簡稱PECVD)，而較佳者係用砂 烷與氧混合物之高密度電漿化學氣相沉積製程。於一實施 例中，第二氧化沉積包括兩步驟。於第一步驟中，流入80 到140 SCCM之矽烷與130到200 SCCM的氧，之後於第 17 1302013Stop). Before the deposition of the nitride layer 34, the pad oxide layer 32 grown or deposited on the wafer can serve as a buffer (buffer) to alleviate the difference between the semiconductor substrate 3 and the nitride layer 34 due to different expansion coefficients (c〇 Stress caused by factors of efficient of expansion. Next, a photoresist layer 37 may be provided on the nitride layer 34, and the photoresist layer 37 is patterned in accordance with the known known lithography principle. The patterned photoresist layer 37 may have an opening from about 1 micron to about 1 micron wide, and is preferably in a range from about 0.20 micron to about 0.24 micron to meet the dimensions required for the isolation trench. Referring to FIG. 2, the conventional method is used for isotropic etching and/or anisotropic etching of the nitride layer 34 and the pad oxide layer 32, such as dry or wet etching, to remove portions not covered by the photoresist layer 37. And in Figure 3, 'sustained isotropic and/or anisotropically etched into the semiconductor substrate 30 to help form trenches having a depth of about 0.2 microns to 0.3 microns. Each trench may include two trench sidewalls ( Trench sidewall)39 and extension A trench bottom 41 between the side walls 39 of the trench. The trench sidewall 39 in this embodiment is inclined to the trench bottom 41, and the trench bottom 41 includes a substantially flat surface extending completely between the trench sidewalls 39. The resulting trench sidewall 39 can be at an angle of, for example, about 60 degrees to about 90 degrees to the trench bottom 41. In a modified embodiment, the corners connecting the trench sidewall 39 to the trench bottom 41 are round. The photoresist can then be removed by known standard strip and ash steps. Subsequently, as shown in the cross-sectional view of FIG. 4, a thermal oxidation process is performed to the trench sidewalls 39 and The bottom of the trench 41 grows an oxide liner (oxide line 〇 43. When this layer of oxide liner is used to round the 12 1302013 09665twf2.doc/d 97-03-31, the thickness can grow to 400 angstroms. Between 600 and angstroms, the oxide liner 43 provides three basic functions: rounding of the trench profile, reducing stress caused by etching in the semiconductor substrate 30, and protecting oxide recesses. Layer 43 can enhance the 矽The interface quality of yttrium oxide. Fig. 5 is a schematic view showing the formation of a first oxide layer 45 after the deposition of a first oxide in the structure of Fig. 4. The boundary between two adjacent oxide layers is The first oxide layer 45 can be subjected to a chemical vapor deposition process including: high density plasma chemical vapor deposition (HDPCVD), atmospheric pressure chemical vapor deposition (APCVD). And sub-atmospheric CVD (SACVD) for deposition, and preferably silane (SiH4) and oxygen (02) in decane flow from 50 to [J 100 SCCM (standard cubic centimeters per minute), oxygen flow from 80 to 150 SCCM, deposition time from 10 seconds to 30 seconds of high-density plasma chemical vapor deposition process for deposition. The thickness of the finally formed first oxide layer 45 at the bottom 41 of the trench is 1000 to 2000 angstroms. The thickness of the deposit can be adjusted to reduce the occurrence of any overhang phenomenon and reduce the aspect ratio of the trench. The first oxide layer 45 partially formed on the trench sidewalls 39 can be deposited on the trench edge of the trench faster than the bottom of the trench. Such a phenomenon can lead to problems such as reentrance, in which the top of the trench will become narrower than the lower end. Then, a selective etching method (selective etch 13 1302013 97-03-31 09665 twf2.doc/d process) is performed in which a portion is removed from the trench sidewall 39 at a greater rate or extent than the trench bottom portion 41 is removed. The first oxide layer 45. Therefore, a wider window can be obtained to facilitate the deposition of the subsequent second oxide layer 55 (see the subsequent Fig. 7a). In accordance with one aspect of the present invention, the initial deposited thickness of the first oxide layer 45 is designed to create a trench profile that facilitates void-free filling of the second oxide layer 55. The selective etching process is combined. In this embodiment, the non-isotropic selective etching process includes a wet spin etch in which the wafer is immersed in a chemical solution, and preferably the concentration is 10:1. A buffered oxide etch (BOE) agent and a diluted hydrofluoric acid (DHF) mixture between 500:1, and simultaneously rotate the wafer during etching. The wafer can be placed horizontally and horizontally rotated or placed vertically and vertically. In this embodiment, wet spin etching removes oxide between about 100 angstroms and about 300 angstroms. When the wet engraving is performed to rotate the wafer, more etchants and ditches are caused by, for example, the spinning motion and the centrifugal force in the flow of the chemical. The side walls 39 react with each other, and the etchant that reacts with the bottom portion 41 of the trench is less. Adjusting or changing the rate of rotation helps to provide better selectivity between the etched trench sidewalls 39 and the trench bottom 41 to adjust the centrifugal force relative to the gravity. The adjustment between centrifugal force and gravity can be used to adjust the chemical flow for selective engraving to reduce the groove from the groove 14 1302013 97-03-31 09665twf2.doc/d The thickness of the oxide layer 45 is either removed to a greater extent than the bottom 41 of the trench. For example, there may be less chemical soaking at the bottom 41 of the trench during spin-etching than at the sidewalls 39 of the trench, and/or a greater flow of chemicals due to centrifugal forces may occur at the sidewalls 39 of the trench. Etching. When the wafer is horizontally placed and horizontally rotated, the centrifugal force of the relative gravity is increased by increasing the rate of rotation, and thus the lateral etch rate of the relative vertical etch rate is increased, thereby reducing the aspect ratio of the result. By increasing the rate of rotation, the thickness of the first oxide layer 45 at the top of the trench sidewalls 39 can be reduced rapidly and/or to a greater extent than the lower end of the trench sidewalls 39. By reducing the rate of rotation, the centrifugal force with respect to the gravitational force is lowered, and the lateral etching rate with respect to the vertical etching rate is lowered, thereby increasing the aspect ratio of the result relatively. The wet etch recipe is produced in accordance with one or more predetermined geometrical characteristics, such as aspect ratio, first oxide depth, or first oxide thickness. The basic parameter of a wet rotary recipe can be the rate of rotation. For example, if the associated geometric feature is an aspect ratio, a higher aspect ratio trench can use a larger rotation rate, while a relatively small aspect ratio trench can select a smaller rotation rate. Figure 6a is a cross-sectional view of the first oxide layer 45 after wet spin etching in accordance with the present invention, and Figure 6b is the first shown after completion of a standard wet dip etch. Oxide layer 45 structure. The wet spin etch of the present invention can be applied to a trench disposed anywhere on the wafer from the center to the edge. In one embodiment, similar results can be obtained even if the position of the trench on the wafer is changed to use different centrifugal forces. According to one aspect of the invention, a very large rotating speed enhances the centrifugal force (e.g., driving force) relative to gravity. According to another aspect of the present invention, the viscosity characteristic of the driving force of the chemical can also reduce the relative gravity. Therefore, the effectiveness of wet spin etching can be adjusted by changing one or more of the rotation rate, chemical composition, and/or viscosity. The effectiveness of the wet spin etch can also be adjusted in other embodiments by changing the position of the trench on the wafer. Although horizontal placement is exemplified in the present embodiment, the wafer may be placed vertically in the modified embodiment. Therefore, the wet spin-etching effect can be adjusted by changing the spin-axis or axis of the wafer. In a vertical type wafer orientation, a pre-rotation or slow-rotation mode recipe can be established when a chemical is applied, relative to a horizontal axis of rotation. Reduce relative gravity. For example, in any of the above embodiments, various rotational rates, viscosities, and/or axes of rotation may be applied at different points in a predetermined wet etch process. A technically standard implementation method is to perform a wet soak etch after forming the first oxide layer 45. The standard wet immersion etch involves dipping the wafer into a chemical bath for an isotropic etch of the first oxide layer 45. The purpose of the etching is mainly to widen the distance between the side walls 39 of the trench, such as the distance A 48 and the distance B 50, and with a small change or increase in the depth of the trench, such as the distance C 52 , thus providing a small aspect ratio (depth / width). Preferably, the trench sidewall 39 is etched to a distance A 48 greater than the distance B 5 〇 ' to resist reentrance. 16 1302013 97-03-31 09665twf2.doc/d The advantages of the wet spin etching of the present invention can be seen by comparing Figures 6a and 6b. The use of wet spin etching (Fig. 6a) instead of conventional wet soak etching (Fig. 6a) can be achieved by selectively increasing the distance A 48 or increasing it to the maximum ' while reducing the distance C 52 or minimizing it, To reduce or eliminate the aspect ratio problem. Wet rotary engraving also reduces or eliminates the problem of reentrance of narrow trenches. By reducing or minimizing the aspect ratio, problems associated with trenches with high aspect ratios can be avoided. This is due to the fact that in addition to the vertical deposition rate on the trench substrate 41, the lateral deposition rate on the trench sidewalls 39 is taken into consideration. The deposition rate along the upper portion of the trench sidewall 39 is higher than the lower portion of the trench sidewall 39 or bottom portion 41. Therefore, the ditch may be blocked or block the upper portion of the side wall 39 of the ditch, and the reactants may not reach the lower portion of the ditch before completely filling the ditch. Therefore, cracks or voids are formed, causing electrical faHure in the components adjacent to the affected trench. Figures 7a and 7b show the isolated trenches previously shown in Figures 6a and 6b, respectively. A cross-sectional view of a second oxide layer 55 is formed after a second oxide deposition is performed. The second oxidation deposition may be performed by a low pressure chemical vapor deposition process (LPCVD), a tantalum density plasma chemical vapor deposition process, or a plasma enhanced CVD (PECVD) process. Preferably, a high density plasma chemical vapor deposition process using a mixture of sand and oxygen is used. In one embodiment, the second oxidative deposition comprises two steps. In the first step, 80 to 140 SCCM of decane is flowed with 130 to 200 SCCM of oxygen, followed by the 171302013
09665twe.doc/d 97-03-31 二步驟流入110到180 SCCM之矽烷與180到250 SCCM 的氧。在第7a圖中溝渠已被完全塡充，而形成具良好的電 性特徵的隔離溝渠。而在習知的第7b圖中顯示接近溝渠底 部41有空隙或裂縫57形成，這將在之後導致鄰近的電晶 體、電容器等之元件失誤。在一修改的實施例中，第二氧 化層55可用其他介電材質取代，如氮氧化矽（silicon oxynitride) ° 隨著第二氧化層55的沉積後，施行一化學機械硏磨 製程（chemical mechanical planarization，簡稱 CMP)去平 坦化表面。而氮化層34在化學機械硏磨製程期間可作爲硏 磨終止層，以防止氧化物、氮化物、矽等從晶圓被進一步 去除。第8圖所示係第7a圖在施行一化學機械硏磨製程後 的剖面圖。繼第二氧化層55沉積後，而在化學機械硏磨製 程之前可施行一非必要的回火（anneal)，以增加氧化物的 緻密度(densification)，因而在後續製造步驟期間將其蝕刻 率降至最小。 在第9圖中，於化學機械硏磨製程後可用一濕式鈾刻 如用磷酸（H3P〇4)處理晶圓，以氮化層34與墊氧化層32。 最終的晶圓幾乎是平的，且具有數個被無裂縫隔離溝渠62 分隔開的主動區60。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 18 1302013 09665twG.doc/d 97-03-31 【圖式簡單說明】 第1圖是在中間製程階段的一種積體電路之剖面示意圖； 第2圖是第1圖中之結構在一蝕刻步驟後的剖面示意圖； 第3圖是第2圖中之結構在形成溝渠以及去除光阻層之後的剖面 示意圖； 第4圖是第3圖中之結構在一氧化襯層之運用後的剖面示意圖； 第5圖是第4圖中之結構在沉積一第一氧化層之後的剖面示意圖； 第6a圖是第5圖中之結構在一旋蝕刻步驟後的剖面示意圖； 第6b圖是習知一種類似第6a圖之剖面示意圖，係施行一標準的 蝕刻步驟； 第7a圖是第6a圖中之結構在一第二氧化物的沉積後的咅_示意 圖； 第7b圖是習知一種類似第6b圖之結構在一第二氧化物的沉積後 的剖面示意圖； 第8圖是類似第7a圖之結構在施行一化學機械硏磨製程後的剖面 示意圖；以及 第9圖是類似第8圖之結構在一後續蝕刻步驟後的剖面示意圖。 【主要元件符號說明】 30 半導體基底 32 墊氧化層 34 氮化層 37 光阻層 39 溝渠側壁 19 1302013 97-03-31 09665twf2.doc/d 41 :溝渠底部 43 :氧化襯層 45，55 :氧化層 48，50，52 ··距離 57 :空隙或裂縫 60 :主動區 62 :隔離溝渠 2009665twe.doc/d 97-03-31 Two steps into 110 to 180 SCCM of decane and 180 to 250 SCCM of oxygen. In Figure 7a, the trench has been fully filled to form an isolated trench with good electrical characteristics. In the conventional Fig. 7b, it is shown that there is a gap or crack 57 near the bottom of the trench, which will later cause component errors of adjacent electro-crystals, capacitors and the like. In a modified embodiment, the second oxide layer 55 may be replaced by other dielectric materials, such as silicon oxynitride. With the deposition of the second oxide layer 55, a chemical mechanical honing process is performed. Planarization, referred to as CMP), flattens the surface. The nitride layer 34 can serve as a ruthenium termination layer during the chemical mechanical honing process to prevent further removal of oxides, nitrides, germanium, etc. from the wafer. Figure 8 is a cross-sectional view of Figure 7a after a chemical mechanical honing process. After the deposition of the second oxide layer 55, an optional anneal may be performed prior to the chemical mechanical honing process to increase the densification of the oxide, thereby etching the etch rate during subsequent fabrication steps. Minimized. In Fig. 9, the wafer may be treated with a wet uranium engraving such as phosphoric acid (H3P〇4) after the chemical mechanical honing process to nitride layer 34 and pad oxide layer 32. The resulting wafer is almost flat and has a plurality of active regions 60 separated by a crack-free isolation trench 62. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 18 1302013 09665twG.doc/d 97-03-31 [Simple description of the diagram] Figure 1 is a schematic cross-sectional view of an integrated circuit in the intermediate process stage; Figure 2 is the structure in Figure 1 after an etching step FIG. 3 is a schematic cross-sectional view of the structure of FIG. 2 after forming a trench and removing the photoresist layer; FIG. 4 is a schematic cross-sectional view of the structure of FIG. 3 after application of an oxide liner; 5 is a schematic cross-sectional view of the structure of FIG. 4 after depositing a first oxide layer; FIG. 6a is a schematic cross-sectional view of the structure of FIG. 5 after a spin-etching step; FIG. 6b is a conventional similar 6a is a schematic cross-sectional view of a standard etching process; Figure 7a is a schematic diagram of the structure of Figure 6a after deposition of a second oxide; Figure 7b is a conventional analogous to Figure 6b. A schematic cross-sectional view of a structure after deposition of a second oxide; FIG. 8 is a schematic cross-sectional view of a structure similar to that of FIG. 7a after performing a chemical mechanical honing process; and FIG. 9 is a structure similar to FIG. Sectional representation after subsequent etching steps . [Main component symbol description] 30 semiconductor substrate 32 pad oxide layer 34 nitride layer 37 photoresist layer 39 trench sidewall 19 1302013 97-03-31 09665twf2.doc/d 41 : trench bottom 43: oxide liner 45, 55: oxidation Layers 48, 50, 52 · Distance 57: voids or cracks 60: active zone 62: isolation trenches 20