TWI301975B - Memory device with built-in error-correction capabilities - Google Patents

Description

130 1975 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ And a method of operating a memory component to provide built-in error correction capabilities. Prior Art For the design of semiconductor memory devices, redundant memory cells are typically fabricated with memory arrays along the rows (c ο 1 u m n s ) or columns (r 〇 w s ) of the memory array. Redundant circuitry is used to control the replacement of one or more failed memory cells of the memory array with one or more redundant memory cells. The redundant memory unit described above allows the memory element to function normally even when the memory array has a fault memory unit. In general, the redundant circuit is connected to the redundant memory unit and one row or column of the redundant memory unit is selected to replace the corresponding row or column of one of the memory cells having one or more fault cells. In particular, the redundant circuit responds to an address signaj corresponding to the failed cell of the memory array by accessing the redundant memory cell in place of the failed cell. The conventional redundant circuit design uses a fusible link that permanently replaces the failed unit. In particular, the redundant circuit described above relies on logic to generate a signal to replace the failed unit. The logic circuit described above may consist of a logic gate array with a fusible link between its logic gates. The fusible link design allows the electrical connection between the logic gates to be programmed by providing a large current to the one or more connections to cut the fusible link. The above logic circuit, programmed with a particular remaining connection between the logic gates, operates the redundant circuit described above to permanently replace the failed unit with the redundant unit.

11287twfl.ptc Page 6 1301975 _ Case No. 92117234_ Year Month Day Correction _ V. Invention Description (2) However, if the replaced redundant memory unit becomes faulty later, the permanentity of the above redundant circuit will hinder The replaced redundant unit is replaced again, thus limiting the reliability and resiliency of the memory component. As a result, only the conventional redundant circuit can be used to replace the failed memory cell generated by the manufacturing process, and it is not possible to replace the memory cell which later becomes faulty after the memory element starts operating. SUMMARY OF THE INVENTION In accordance with the present invention, a memory component including a main array, 'a redundant array, and a switching circuit is provided herein. The main array includes a plurality of memory cells including a first fault unit and a second fault unit. The redundant array described above includes at least one replacement memory unit for replacing at least one failed unit of the primary array. The switch circuit coupled to the main array and the redundant array receives a first control signal to switch a unit signal of the first fault unit to the replacement unit, and receives a second control signal to receive the second fault unit The meta signal is switched to the above replacement unit. In one embodiment, the first and λ-control signals respectively identify the first and second faulty units, wherein the first and second control signals are changed according to fault states of the first and second faulty units at different times. . Also in accordance with the present invention, a memory component having built-in error correction capabilities is provided herein. The memory device includes a main array, a redundant array, and a switching circuit. The main array described above includes a plurality of memory cells. The redundant array described above includes at least one replacement unit for replacing at least one failed unit of the primary array. A control signal identifies the above ticket

11287twfl.ptc Page 7 1301975 修正 Amendment iJI 92117m V. Inventive Note (3) and the control signal is changed according to the above faulty unit at different times: change. The above switching circuit includes a main array and the above-mentioned main array. According to the present invention, an additional operation is provided here; Provides a way to build error correction capabilities. The above method comprises a main array comprising a plurality of memory cells; a fault state is provided to change the control signal; and a switching circuit is provided for receiving the unit signal of the control signal to be replaced by the replacing unit. The above description of the above-mentioned faults and the following detailed description are only exemplary embodiments, and are not intended to limit the present invention. Therefore, the scope of m: m should be determined by the scope of the patent application. The above and other objects of the invention are "explained, and the preferred embodiments thereof are described below, and are matched; = can be described as follows: q 圃 圃 , 作 , , , , , , , , , , , , , , , , And: a more complete explanation. +Same type Number chart: Door order. 1 Double Table Different Type The present invention provides a memory element and an operation method. In particular, the present invention provides a hidden object that allows replacement of one or more. Page 8 11287twfl.ptc 1301975 Case No. 92117234 5. Invention Description (4) Memory elements of the memory unit and The memory element will first be described as a symbol f 1 according to an embodiment of the invention. And using this memory element as a mortal memory cell "$$$$ section" Next, a memory element and a method thereof in a system for making a T-processor according to an embodiment of the present invention will be described Figure 1 is a block diagram of a memory cell block according to an embodiment of the present invention. Referring to Figure 1, the memory component 10 includes a square array of cattle 12/redundant array 14, and a switching circuit. 16m 忆 体 阵 忆 1 1 1 可能 可能 可能 可能 可能 可能 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Other, ',, memory unit. The above memory unit is processed from a processor, a computer, or a special application that uses two pieces of data. (If the signal is described later, it may be read, overwritten, Or erasing the data and storing a plurality of δ hexamme units. The main array = material. The redundant array η is also the same as the body unit. To illustrate the memory unit of the above-mentioned series 12 of the array 4 of the present invention. Because of the manufacturing aspect, I assume a partial main array or Permanently affecting one or more of the main arrays 12 and/or others may be temporary. When one or more of the memory unit operations are identified as the remaining elements of the array lj to replace the above elements, it may be redundant. The number of redundant soap elements is usually less than the main ^7L. The size of the array 1j of the redundant array 可能4 may depend on the number of units a. The number of redundant trouble sheets 70, and the cost ^ b as the main array 1 2 size, in order to replace the trouble ticket with a redundant unit. Early, so at the same time with the main array 12

1301975 _ Case No. 92117234_年月日日 Revision _ V. Invention Description (5) and Redundant Array 1 4 coupled switch circuit 16 receives the data to be stored in the faulty unit and transmits the data to be stored Go to the above redundant unit and process other signals or data. In particular, switching circuit 16 receives a control signal to switch the cell signals of the failed cells of main array 12 to the replacement cells of redundant array 14. The above unit signals may include information required to access the memory unit as the address signal, as well as other information such as input and output data. In one embodiment, the control signal received by the switching circuit 16 may change over time according to the fault condition of the faulty unit. In other words, the above control signal may change when the available unit becomes faulty or when the faulty unit becomes available. The above varying control signals allow the switching circuit 16 to choose to abort the original memory replacement or create a new memory replacement. In one embodiment, the switch and circuit 16 may be a logic array, such as a reprogrammable logic array (RPLA). In particular, the above-described reprogrammable logic array (RPLA) may be coupled to a multiprocessor, The multiprocessor is capable of accessing the memory elements 10, such as by panning the processor to receive the unit signals and transmitting the unit signals to the processors, and, in addition to replacing the single failed memory unit, the switching circuit 16 may The faulty unit is replaced by a memory unit of a particular block, group, or group to which a faulty unit belongs. Thus, it is possible to replace a particular block, group, or group of memory cells having one of the primary arrays of one or more faulty cells with one of the redundant arrays of blocks, groups, or groups of replacement units. The choice of replacing a faulty unit individually or replacing a faulty unit in a group is based on many factors, such as the design and type of the memory component, the application of the memory component, the type of system that accesses the memory component, and even the replacement.

11287twfl.ptc Page 10 1301975 Case No. 92117234 修正 Amendment V. Description of invention (6) Type of fault or error in the body component. In general, memory components have two types of errors: permanent and temporary. A permanent error (also known as a hard error (h a r d e r r 〇 r )) means that the error is irreversible. A typical permanent error occurs during the manufacturing process of the memory component. A temporary error (also known as a soft error) means that the memory unit is only a temporary failure and the failure may change over time. In other words, a memory unit with a temporary error may only be used for a period of time and thus only need to be replaced during this particular failure. > In order to replace the temporary faulty unit, the control signal for controlling the switching circuit 16 may change with time according to the fault state of the temporary faulty unit described above. The above varying control signals allow the memory components to use the redundant array more efficiently. As a result, more redundant units can be used to replace the additional faulty units. 2A and 2B respectively provide a block diagram and an alternative diagram to illustrate the two-way error of the memory unit and the replacement of the memory unit according to an embodiment of the present invention. Referring to the replacement of the hard-wound memory unit in FIG. 2A, the memory cells C1 to C6 are memory cells of a memory array and the redundant cells R 1 1 to R 16 are replaced by a redundant array. unit. The functions of memory cells C2, C4, and C5 are within specifications, while memory cells C1, C3, and C6 are permanent faults. The control signal instructs the switch circuit to replace the faulty cells ci, C3, and C6 with replacement cells R11, R12, and R13, respectively, for example, by switching the cell signals of cells C1, C3, and C6 into cells R1, R1, respectively. And the unit signal of R13. Referring to the replacement map with soft error in Figure 2B, the memory unit a j

11287twfl.ptc Page 11 1301975

A redundant array ί.iti I Ϊ early ^ and replace the memory * yuan ruler 1 to R3 is the function of the body unit A1:; Period:: to the period T4 during the memory period memory unit Α 2 is fault: body: 乂 5fT, barrier. In the period T1, the memory list (4) is (4) to the period T3, and the record 4 is faulty. Therefore, the fault state of the memory cell during the period up to the period Τ4 is in these; when the operation is performed according to these temporary trouble sheets, the circuit is replaced with the redundant unit R1 during the period Τ1, and the single-change unit A3 is replaced, and During the period T3 with the redundancy unit R3, since the unit A2 is no longer reversed, the replacement R1 for the unit A2 is now available, so the above control replaces the unit A3, and replaces the unit A5 with the redundant unit R2, R3. . In the period T4, the above control signal is changed to the command. And, because the redundant unit signals the redundant unit R 1 to replace the unit A5. As a result, redundant single units. Therefore, in an embodiment, the fault state of the different time is used to replace a main array at different times. As described above, the control signal element is changed to a fault state at different times, and the control signal refers to the open element. A2, and replaces the unit A5 with the redundant unit R2. In the period T2 and the cycle, the above control signal command is changed. And, since the redundant unit system signal indicates that the unit A4 is replaced with the redundant unit r1, and in the redundant single period, since the single |tA3 is no longer reversed, the replacement for the single turn A3 is now available, so the above Control unit A4 and replace the unit with a redundant unit [^2 element R3 now available to replace one of its switching circuits may replace the unit with a different fault unit according to one of the redundant arrays. May vary depending on one or more tickets. In order to detect the memory unit

1301975.Article __Case No. 92117234_Yearly ^^-Repair-- V. Invention Description (8) Fault state, so the memory component 10 of Figure 1 includes the main array 12 and the redundant array 14 The coupled error detecting component 18' is configured to periodically or/or detect the function of the main array 1 2, the redundant array H, or both of the memory units according to a specific command. In one embodiment, the error detection 70 is a single tester, such as an external tester or a built-in self tester (^ 1 1 1 - 1 n self - tester, BIST). When a built-in self-tester (BIST) is used, it may become part of the memory component 1 or a portion of the system chip containing the memory component 10 0. Furthermore, as an embodiment of the present invention The memory component 1 of the system described may include a central processing unit (CPU) 20 for providing a control signal to the switching circuit 16. Referring to Fig. 1, a central processing unit (CPU) 20 may be coupled to the switching circuit 16. In order to obtain the fault condition of the memory unit, the central processing unit (CPU) 20 may also be coupled to the error detection component 18 to receive information identifying the faulty unit, such as by identifying the faulty unit's data by its address. When the data from the error detecting component 18 is changed as a result of a failure state change of the memory component of the main array, the central processing unit (C has U) 20 changes the above control signal. The updated control signal described above will then instruct the switch circuit 16 to properly replace the recently failed unit and/or replace the unit that now restores the function. In one embodiment, the control signal may identify the unit by an address or any other unit identification information. The memory component 10 may also be an embedded memory component to which a system (also referred to as a system on chip (SOC)) fabricated on a single semiconductor wafer belongs. Figure 3 illustrates an example of an arrangement of a single wafer system (SOC) wafer 30 as described in one embodiment of the present invention. Single chip system

11287twfl.ptc Page 13 1301975 Case No. 92117234

B. V. DESCRIPTION OF THE INVENTION (9) The system (S0C) chip 30 includes a system circuit area 32 such as a digital logic circuit and a memory module 34. In one embodiment, the memory module 34 may be a flash memory module, and may include a main array 34 A, a redundant array 34 B, and a control circuit 3 4 C for achieving the operation of the above memory. . In one embodiment, control circuit 34C may include one or more components, such as a switching circuit, a built-in self tester (B I ST ), processing for generating control signals, or other convenient components capable of receiving and providing the necessary signals. Many modern semiconductor components are designed using a single-chip system (S0C). However, because the memory unit is more sensitive to errors, whether hard or soft, the single-chip system (S〇c) wafer may be susceptible to failure simply because one of the memory modules is wrong. As a result, memory module errors can significantly reduce yields and increase the cost of producing single-chip system (S0C) chips due to the high failure rate associated with memory modules. As described above, the embodiment of the present invention can correct the memory error of the above components, thereby providing a memory element or a memory module with built-in error-correction (BEC) force. group. In a real case, adding redundant arrays and their accompanying circuits, only slightly increasing the single-wafer system (s〇c) wafer area, but improving the production of wafer system (S0C) chips due to built-in error correction (BEC) capabilities. Yield. In particular, in one embodiment, the redundant array may only increase the single wafer system (S0C) wafer area by approximately 1.25%. As described in one embodiment of the present invention, the memory module 34 of FIG. 3 occupies approximately one quarter of the entire area of the single wafer system (s〇c). Within the memory module 34, the main array 34A occupies approximately half of the memory module 34, or a single wafer system (s〇c) wafer 3

Page 14 1301975 _ Case No. 92117234_Year __s__ Amendment ___ V. About one-eighth of the description of the invention (10). If a redundant array of approximately one-tenth the size of the main array 34A is added, such as the redundant array 34B, the added single-wafer system (S0C) wafer area is approximately 1.25% (10°/ 〇, 1/8), plus an additional tiny area occupied by the control circuitry of the redundant array 3 4 B. Figure 4 is a block diagram of the switching circuit (e.g., Reprogrammable Logic Array (RPLA) 40) associated with three central processing units (CPUs) 42, 44, and 46. A Reprogrammable Logic Array (RPLA) 40 is also coupled to the memory component 1 to allow data to be read and written by the central processing units (0-11) 42, 44, and 46. As shown, the reprogrammable logic array (RPLA) 40 includes a clock terminal CK for receiving clock signals and three control memory elements by central processing units (CPUs) 42, 44, and 46. 1〇 access control terminals a, B, and c. The clock signal of the reprogrammable logic array (RPLA) 40 may be the same or synchronized with the clock signals operating the central processing units (CPU) 42, 44, and 46. In addition, the Reprogrammable Logic Array (RPLA) 40 may have a companion processor similar to the central processing unit (CPU) 20 of Figure 1 for generating control signals for the replacement of the failed memory unit. In order to manage memory accesses with multiple processors, a reprogrammable logic array (RPLA) 40, as described in one embodiment of the invention, may include a sample and hold circuit. The above sampling and holding circuits may work with different types of system architectures, such as synchronous systems or streamlined processing systems. Figure 5 illustrates an example of a sample and hold circuit 50 that provides a set of transistors and capacitors to the memory busbar 10B and central processing unit (CPU) busbars 42B, 44B, and 46B. In particular, transistor 1 〇 T and capacitor 1 〇 c and

11287twfl.ptc Page 15 1301975

Recall that the body bus 8B fits together. The transistor 42T and the capacitor 42 c are coupled to the bus (24) bus bar 42B. The transistor 44T and the central processing unit (CPU) bus bar 44B are coupled. Transistor 46T and Ray ☆ 毋〇 Zhongxing Eight Electric Valley! §46Γ47 This processor (CPU) bus is 4 6B. Typically, t, such as IOC, 42C, 44C, and 46C, act as a data storage unit, with the transistors 10T, 42T, 44T, and 46T controlling storage and/or reading. In the operation, when the Beading blade is operated, when the gate 10G of the transistor 10 is at the logic high level and the gates 42G of the transistors 42Τ, 44Τ, and 46Τ, When 44G and 46G are at a logic low level, the memory element 10 will transfer data via the memory bus 10 Β. Capacitor ^: (Therefore, the above information is stored. Thereafter, when one of the gate terminals 42G, 44G, and 46G becomes a logic high level and the gate terminal 5 2G is at a logic low level, the CPU (CPU) is selected. One of the bus bars 42B, 44B, and 46B to read the stored data. For example, if the voltage at the gate terminal 4 2 G becomes high, the stored data will be transferred to the capacitor 42C and possibly via the medium processor. The (CPU) bus bar 42B is accessed by a central processing unit (CPU) 42. Similarly, the sample and hold circuit 50 may operate in the reverse order of the selected gate stage 'eg by providing a logic high level to the gate The stage 42G and later to the gate stage 10G, the data is transferred from the central processing unit (CPU) 42 via the central processing unit (CPU) bus 42B and stored in the memory element 10 via the memory bus 10B. The signal that controls the memory access since the gate terminal 42G, 44G, or 46G is used may be generated by a signal generator. FIG. 6 illustrates the present invention.

11287twfl.ptc Page 16 1301975 Amendment 曰 I No. 92117234 V. INSTRUCTION DESCRIPTION (12) The signal generator μ described in the first implementation. G and fVB, c may provide a wheeled signal generator 60. Signal Production = According to the above, the memory cell terminals 42G, 44G, and 46G are controlled. %子] Wang Bie to Gate Level & t ί 2 provides: a kind of operation memory component to provide built-in error to correct the above faulty unit at different times; barrier unit; root: 丄, for; In order to receive the above-mentioned "letter", the message is replaced by the replaced unit. Now, in the above, in one embodiment, a processing control signal may be used. It is also possible to provide an error detection. The component is also provided with the memory unit, the redundant array redundancy, and the array light combining device (BIST) for detecting the main array as the above-mentioned error detecting component. In addition, the built-in self-testing circuit may include a More than one example, 'the above-mentioned open memory component reads the data, writes the record and manages the re-programmable logic array. As the invention = one or two materials, or many of the applications and methods of the two As a matter of course, the memory cell described in the implementation of I may be a memory component memory device fabricated on a single semiconductor wafer. The embedding of the system of poly k Although the present invention has been compared with < fk π tk The preferred embodiment discloses the above However, it is not

130 1975 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Therefore, the scope of the invention is defined by the scope of the appended claims.

11287twfl.ptc Page 18 1301975 _ Case No. 92117234_Yearly Date Correction_ BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a memory element according to an embodiment of the present invention. Figure 2A is a block diagram of a replacement of a memory cell in accordance with an embodiment of the present invention. Figure 2B is an alternate diagram of a replacement of a memory cell in accordance with an embodiment of the present invention. Figure 3 is a diagram showing an example of a semiconductor wafer arrangement as described in an embodiment of the present invention. Figure 4 is a block diagram of a switching circuit in accordance with an embodiment of the present invention. Figure 5 illustrates a sample and hold circuit as described in one embodiment of the invention. Figure 6 is a diagram showing a signal generator for controlling memory access as described in an embodiment of the present invention. Schematic description 10 Memory component 10B Memory bus 10C Capacitor 10G Transistor 1 0 T gate terminal 1 0T transistor 12 Main array 14 Redundant array 16 Switch circuit 18 Error detection component

11287twfl.ptc Page 19 1301975 _ Case No. 92117234_Yearly and Monthly Correction Schematic Description 20 Central Processing Unit (CPU) 30 Single Chip System (SOC) Chip 3 2 System Circuit Area 34 Memory Module 34A Main Array 34B Redundancy Rema Array 34C Control Circuit 40 Reprogrammable Logic Array (RPLA) 42 Central Processing Unit (CPU) 42B Central Processing Unit (CPU) Bus Bar 42C Capacitor 42G Transistor 4 2T Gate Stage 42T Transistor 44 Central Processing Unit (CPU 44B central processing unit (CPU) bus bar 44C capacitor 44G transistor 44T gate terminal 44T transistor 46 central processing unit (CPU) 46B central processing unit (CPU) bus bar 46C capacitor 46G transistor 46T gate terminal 46T Transistor 50 sample and hold circuit

11287twfl.ptc Page 20 1301975 _ Case No. 92117234_Year Month Day_Revision Diagram Simple Explanation 5 2 G Interstage End 60 Signal Generator A Bu A 5 Memory Unit C Bu C 6 Memory Unit R1-R3 Redundancy Unit (replacement unit) R11 to R16 Redundant unit (replacement unit) T Bu T 4 cycle

11287twfl.ptc Page 21

Claims (1)

1301975 Case No. 92117234 JE_L· VI. Application Patent Range 1 · A semi-primary array fault unit and a redundant array are replaced by one of the main array switching power and the redundant array fault unit one of the two control unit signals, Wherein the second fault is single and the second is 2. further includes the signal 3. Further includes components. 4. Where when replacing a single 5. where the 6. If applying for a treatment with a power such as applying a replacement with the application as the replacement element will be as applicable to the switch electrical as applied for conductor memory, including the second fault column, containing at least one way, Including combining, the second first and second elements are used by the unit signal, and the barrier unit is in the patent range. The switching circuit 0 patent range is replaced by the main array patent range unit to replace the patent range road and the plurality of patent range body components. The component includes: a plurality of memory cells including a first cell; at least one replacement memory cell for replacing the faulty cell; and a reprogrammable logic array with the primary array to receive a first control signal Switching the first switch to the replacement unit, and switching one of the unit signals of the first faulty unit to the second control signal to identify the first and the first and the second control signals respectively according to the first difference One of the times changes in the fault state. The semiconductor memory device of the first aspect, wherein the first and the second control and the second semiconductor device are coupled to detect an error detection of the fault state. The semiconductor memory component of the item, wherein the first faulty unit is no longer faulty. The semiconductor memory device of item 1 is coupled by a processor. The semiconductor memory device of item 1, 11287twf1.ptc Page 22 1301975 _ Case No. 92117234_Yearly Month Date Amendment _ VI. Patent Application Scope The fault status is a hard error. 7. The semiconductor memory device of claim 1, wherein the fault condition is a soft error. 8. The semiconductor memory device of claim 1, wherein the semiconductor memory component is an embedded memory component. 9. A semiconductor memory component having built-in error correction capability, the component comprising: a main array comprising a plurality of memory cells; 4 a redundant array comprising at least one replacement unit for replacing at least one of the main arrays Two fault units, wherein a control signal identifies the fault unit, and the control signal changes according to one fault state of the fault unit at different times; and a switch circuit including a coupling with the main array and the redundant array And a reprogrammable logic array for receiving the control signal and switching one of the unit signals of the faulty unit to the replacement unit. > 1 0. The semiconductor device of claim 9, wherein the hidden component further comprises a processing circuit for providing the control signal. 11. The semiconductor memory device of claim 9, further comprising an error detecting component coupled to the main array to detect the fault condition of the memory cells of the main array. The semiconductor memory device of claim 9, wherein the replacement unit replaces the different fault cells of the main array at different times according to the fault states of the faulty units at different times. 1 3. The semiconductor memory component according to claim 9 of the patent application, 11287twfl.ptc Page 23 1301975 _ Case No. 92117234_Yearly revision _ 6. Patent application scope wherein the switching circuit is coupled with more than one processor and manages reading data from the semiconductor memory component and writing the semiconductor One of the data of the memory component. 1 4. The semiconductor memory device of claim 9, wherein the fault condition is a hard error. The semiconductor memory device of claim 9, wherein the fault condition is a soft error. 1 6. A method of operating a memory component to provide built-in error correction capability, the method comprising: providing a primary array comprising a plurality of memory cells; providing a redundant array comprising a plurality of redundant cells Replacing at least one faulty unit of the primary array; providing a control signal to identify the faulty unit; changing the control signal according to the faulty state at one of different time states; and/or providing a reprogrammable logic array And a switching circuit for receiving the control signal to switch a unit signal of the faulty unit to the replacement unit. 17. The method of claim 16, further comprising providing a processing circuit to provide the control signal. 18. The method of claim 16, further comprising providing an error detecting component coupled to the primary array to detect the fault condition of the memory cells of the primary array. 11287twf1.ptc Page 24 1301975 _ Case No. 92117234_年月日日_Amendment_ IV. Summary of Chinese Invention (Invention Name: Memory Element with Built-in Error Correction Capability) A built-in error correction (built-in error - A semiconductor memory component of capability, comprising: a primary array comprising a plurality of memory cells; a redundancy array comprising at least one replacement cell, And replacing at least one defective cell of the foregoing main array, wherein the faulty unit is identified by a control signal and the control signal is changed according to the fault state of the faulty unit at different times; and one includes a switching circuit of a reprogrammable logic array coupled to the main array and the redundant array to receive the control signal, and switching the unit signal (cel 1 signal ) of the fault unit into the above Replace the unit. Wu, (1), the representative of the case is: -_ Figure (2), the representative symbol of the representative figure of the case is a simple description: V. English invention summary (invention name: MEMORY DEVICE WITH BUILT-IN ERROR-CORRECTION CAPABILITIES) A Semiconductor memory device having built-in error-correction capabilities, which compri ses a primary array containing a plurality of memory cells; a redundancy array containing at least one replacement cell for replacing at least one defective cell in the primary array, Is identified by a control signal and the control signal varies according to a 11287twfl.ptc Page 2 1301975 _ Case No. 92117234_年月日日正四, Chinese invention summary (invention name: memory component with built-in error correction capability) 10 Memory component 12: main array 14 redundant array 16 · Switching circuit 18 error detecting component 20: central processing unit (CPU) 5. English invention summary (invention name: MEMORY DEVICE WITH BUILT-IN ERROR-CORRECTION CAPABILITIES) defective state of the defective cell over time; and a conversion circuit a reprogrammable logic array that is coupled to the primary array and the redundancy array for receiving the control signal to switch a cell signal of the defective cell to the replacement cell. 11287twfl.ptc Page 3 1301975 _ Case No. 92117234_ Year Month Day Amendment VI. Designation of Representative Figures Page 4 11287twfl.ptc