Ί301019 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種除頻器電路， 一 號以分別打開或關閉二電晶體開關：=差動信 頻’並產生正交信號，適用於頻率合成器、正交 ^ 虎產生器等裝置之低功率高速除頻器電路者。 乂 • 【先前技術】 j速除頻器在各式寬頻及無線的應用上扮演 的角色。麵作在27GHz及33GHz的靜態⑽ 如^的製程上。未來桃bps的寬頻網路收發已 =現 60GHz的射頻系統需要更高速的除頻哭。 成=第5、5A圖所示，其為將;型正反器 ==器電路及該電路之輸入及輸出波形，可用以Ί301019 IX. Description of the Invention: [Technical Field] The present invention relates to a frequency divider circuit, the first to open or close a two-transistor switch: = differential frequency signal and generate a quadrature signal, suitable for frequency Low-power high-speed divider circuit for synthesizers, quadrature devices, and other devices.乂 • [Prior Art] The role of the j-speed divider in various broadband and wireless applications. The surface is fabricated on a static (10) process such as 27 GHz and 33 GHz. Broadband network transmission and reception of future peach bps has been = now 60GHz RF system needs higher speed de-frequency crying. Cheng = 5, 5A, which is a type of positive and negative == circuit and the input and output waveforms of the circuit can be used
型正、反/ίΐ號’其核心電路可等效為―負緣觸發的D ^二 輸入端(IN)為咖，而另-輸入端請 m弟—級門問（Latchl)電路aim二級⑽ =電路a2鎖住訊號；而當二輸人端反向而分別為 L⑽及Hlgh時，第一級門問電路鎖住訊 路a2打開。 木、及門閂包 口月参閱弟6、8圖所示，公只丨丨么$、士二、人 刀別為互補式除頻電路（CMOS im)及源_合邏輯除頻電路（SCL，s〇urce_c卿y L〇=)。該兩種電路常用來實現上述除頻器電路之功能。 W圖係為互補式除頻電路之電路圖，其互補式反相間 .1301019 . 接成正回授，用以鎖住信號。優點是門閂（Latch)電路鎖 住信號時，靜態耗電流極低。缺點是要轉態時，正回授迴 路仍存在，輸入訊號強度需克服此正回授，才能使“忱乜轉 態。其速度較慢，無法處理高速輸入信號。 如第7圖所示，尤其當輸入為High，在0UT1的電壓沒被 拉下來之前，0UT1B缺乏上推（PULL_UP)的路徑，將使得 輸出（0UT1B)由Low轉High的轉態速度慢。 • 帛8圖係為SCL除頻電路’該電路被廣泛應用於高速 ，頻’其中’該MP卜MP2、MP3、MP4係為偽N型金氧半電 日日體（PSeudo-_S)貞載，此負載亦可換成電阻或間極、 汲極短路的M0S。 备要轉態時，下方的NMOS (MN1、MN2)會 / ，……啊、miNi、MN以| ρ 失效°由High時’輸出端經由 較前ϋ·) 有 u—ϋρ路徑。因此，其工作速度 靜態電流消耗大。 仁缺，，以1疋1时ch鎖住信號時， 有鑑於此，為了改盖 能將高速差動信號物上電路不僅 速度、降低靜態電流，發 夕：“虎，且可加快工作 改進，遂有本發明之產生。貝夕的經驗及不斷的研發 f發明内容J 本發明之主要Η > ι 一 王要目的在提供一種除拖的干a 弟一、二級門閂電路連接 。心、^态弘路，其所設的 關分別連接在二門閂 回彳又迴路，且二個電晶體開 路之二差動輪出端之間，俾能兼具 6 1301019 低靜態電流及高轉態速度者。The type of positive and negative / ΐ ' '''''''''''''''''''''''''''''''''''''''''''''''''''''''''' (10) = circuit a2 locks the signal; and when the two input terminals are reversed and respectively L(10) and Hlgh, the first level gate circuit locks the signal a2 to open. Wood, and the door latch mouth month, see the brothers 6, 8 picture, the public only 丨丨 $, 士二, human knife is a complementary frequency-dividing circuit (CMOS im) and source _ logic de-frequency circuit (SCL , s〇urce_c卿y L〇=). These two circuits are commonly used to implement the functions of the above-described frequency divider circuit. The W picture is a circuit diagram of a complementary frequency-dividing circuit, and its complementary inverting phase .1301019 is connected to a positive feedback to lock the signal. The advantage is that the static current consumption is extremely low when the Latch circuit locks the signal. The disadvantage is that when the state is changed, the positive feedback loop still exists, and the input signal strength needs to overcome this positive feedback to make the "turn" state. The speed is slow, and the high-speed input signal cannot be processed. As shown in Fig. 7, Especially when the input is High, 0UT1B lacks the path of push-up (PULL_UP) before the voltage of 0UT1 is pulled down, which will make the output (0UT1B) transition from Low to High slow. • 帛8 is SCL Frequency circuit 'This circuit is widely used in high speed, frequency 'where 'MP MP2, MP3, MP4 is a pseudo N-type gold-oxygen semi-electric day (PSeudo-_S) load, this load can also be replaced by resistance Or the M0S of the interpole and the bungee short circuit. When the switch is ready, the lower NMOS (MN1, MN2) will /, ..., ah, miNi, MN with | ρ failure ° from High time 'output terminal through the front ϋ · There is a u-ϋρ path. Therefore, its working speed quiescent current consumption is large. Insufficient, when the signal is locked at 1疋1, in view of this, in order to change the cover, the high-speed differential signal can be used on the circuit not only the speed. , reduce the quiescent current, eve: "Tiger, and can speed up work improvement, without the invention Students. Bei Xi's experience and continuous research and development f invention content J The main flaw of the invention > ι 一 王 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要 要The heart and the state state Hong Road are connected to the second door latch and the circuit, and the two transistor open circuit between the two differential wheel ends, the 俾 can have 6 1301019 low quiescent current and high transition state. Speed.
本發明之次要目的在提供一種除頻器電路，其所設的 =個電晶體開關分別由差動信號控制，俾能將高速差=信 號源除頻，並產生正交（相位差90。）信號者。 D 路，包為括達Γ之發明之目的’本發明所設之—種除頻器電 兮第 二級㈣（LatCh)電路及二個電晶體開關。 二級叩⑽⑻電路係連接成正回 :二閃電路分別包括-輸人端及二差動輸 : 晶體開關係分別連接在第一、二級門 差 0 “ 一黾日日體開關分別由輸入除 號控制。 u路之差動信 藉此，當差動輸入信號分別打開第一 晶體開關及關閉第二級門閂電 “的電 門嶋轉態，可提供兩差動輸出= 徑，以加快峨路之工作-=阻抗等化路A secondary object of the present invention is to provide a frequency divider circuit in which the set of transistors is controlled by a differential signal, and the high speed difference = signal source can be divided and orthogonal (phase difference 90). ) Signaler. The D-channel is intended for the purpose of the invention of the invention. The present invention provides a classifier (secondary (four) (LatCh) circuit and two transistor switches. The secondary 叩(10)(8) circuit is connected to the positive return: the second flash circuit includes the -input terminal and the second differential input: the crystal open relationship is respectively connected to the first and second level gate difference 0 "one day of the body switch is divided by the input No. Control. The differential signal of the u road is used to provide two differential outputs = diameter to open the first crystal switch and turn off the second stage latch Work-=impedance equalization
_ ^ , 、民 而第二級門問雷敌/蚀A 電氣信號’可使該間電路形成—個理想的 具有低靜態電流的優點。 式兒路， 級門第一級峨路的電晶體開關及打開第-、、及門問弘路的電晶體開關時，則 弟— 電…虎❿弟二級門問電路轉 貞住 速度及降低靜態電流之目的。 粟了相加快工作 為便於對本發明能有更深 【實施方式】 ]瞭％，炫砰逑於後·· 請參閱第1圖所示，其為本發明除頻器電路之較佳實 7 1301019 施例，包括第一、二級門閂（Latch)電路（1、2)以及二 個電晶體開關（Ml、M2 )。 ，該第一、二級門閂（Latch)電路（1、2)係連接成正 回才又迎路’该二門閃電路（1、2)分別包括-輸入端（IN、 ΙΝβ)、二個互補式反相器（CMOS lnverter) (u、12、21、 22)、二個 NM0S 電晶體（M3、M4、M5、M6、M7、M8)及二 個差動輸出端（OUT—卜，—IB、、術—⑻。該正 輸入端（IM)控制第—級門問電路！的時脈，巾負輸入端 (INB )控制第二級門問電路2的時脈。該二門問電路（1、 2)的二個互補式反相器（11、12、21、22)分別連接成正 :授迴路。各門閃電路（卜2)的三個_s電晶體中⑷、 M5 M6 M7、M8)之其中二個_〇S電晶體（M3、M4、 一6 ' M7)連接成差動對的型態。各級門閃電路（卜2)的 3輸出端（OUT」、〇UT」B、qUT』、卿―qb)分別連接 二：個_S電晶體（M3、M4、、M7)的汲極， 咖電晶體⑻、M4、M6、M7)的閘極為資料輸入端；該 第一個NM0S電晶體（M5、M8)的沒極、鱼iiL a +_ ^ , , and the second level of the door to ask the enemy / eclipse A electrical signal ' can make the circuit to form an ideal low quiescent current. The road switch, the transistor switch of the first stage of the gate, and the transistor switch of the first, the, and the door of the Hong Road, the brother-electric...the second-level door of the tiger turns to the speed and Reduce the purpose of quiescent current. The millet phase speeds up the work so that the invention can be deeper [Embodiment]]%, dazzling after the rear ·· Please refer to FIG. 1 , which is the preferred embodiment of the frequency divider circuit of the present invention 7 1301019 Examples include first and second latch circuits (1, 2) and two transistor switches (M1, M2). The first and second latch circuits (1, 2) are connected to form a positive return and then meet the road. The two gate flash circuits (1, 2) respectively include - input terminals (IN, ΙΝβ), and two complementary modes. Inverter (CMOS lnverter) (u, 12, 21, 22), two NM0S transistors (M3, M4, M5, M6, M7, M8) and two differential outputs (OUT-Bu, - IB, , - (8). The positive input terminal (IM) controls the clock of the first-level gate circuit!, the negative input terminal (INB) controls the clock of the second-level gate circuit 2. The two-door circuit (1) 2) The two complementary inverters (11, 12, 21, 22) are respectively connected to positive: the loop. The three _s transistors of each gate flash circuit (Bu 2), (4), M5 M6 M7, M8) Two of the 〇S transistors (M3, M4, and 6' M7) are connected in the form of a differential pair. The three output terminals (OUT", 〇UT"B, qUT", and "qb" of the gate flash circuit (Bu 2) of each level are respectively connected to the drains of two _S transistors (M3, M4, and M7). The gate of the coffee crystal (8), M4, M6, M7) is the data input end; the first NM0S transistor (M5, M8) has the pole, the fish iiL a +
_(M3'M4、M6、M7wm=5_QS 端，源極接地。 Μ極為控制時脈輸入 該二個電晶體開關⑷、Μ2)係為Ν 晶體開關（Ml、M2)的汲極、源極分 篮。电 且該第一級門閂電路1的電晶體開ρ Mi " T-QB)’ 」兒日日間關Mi之閘極 端（IN);而第二級門閃電路2 輸入 日開關M2之閘極連 工301019 接負輸入端（ΙΝβ)，使該二電晶體開關（们、M2)分別 輸入除頻器電路之差動信號控制。 刀 請參閱第卜2圖所示，其為第！圖之互補式電 入端（IN)的時脈由L〇wf _時之等效電路圖。苴中 =-級門的電晶體開關（M1)打開（τ—， 等文成一導通電阻Rm〇s，以提供兩差動輸出端（ου。、 -之間-個低阻抗等化路徑。使暫時減弱正回授強 度’且由於該導通電阻心⑽同時連接兩差動輸出（㈣卜 提一高轉態速度，幫助狀態為^的輸出轉為 之【離由級門問電路2處於鎖住(Latch)電氣信號 心σ *為互補式電路的優勢，使第二級門閂電路2 只消耗極低之靜態電流。 反之，當輸入端（IN)的時脈由High轉為L〇w時， =二:：如第3圖所示。此時’輸入端（INB)打開第二 門心路2的電晶體開關（M2 )，且第-級門閃電路i的 電晶體開關（M"關閉，則可使第二級門問電路2轉能， 第-級門問電路“貞住電氣信號。 “ 藉^上述電路配置’可將高速差動信號源除頻，並產 t正：仏虎’该正交信號頻率為信號源頻率的"2,且可提 南轉態速度，降低靜態電流。 口月 > 閱第4圖所示，其為工作在2.4GHz ISM Band的 :率=器之電路示意圖。其中，本發明可應用為直： 又振nt出^號的高速除頻電路⑼v—^、Div—2)。輸出 的iQ正交信號（uu、L(UB、L〇—Q、L〇—QB)可以提供無 1301019 線接=做為降頻及鏡像拒斥（imager啦tiQn)使用 ▲又仏號由相位多工器做相位切換，則可以組合出 變除數的除頻器。另，並 文 另糟由本發明應用於上述電路系统. 可有效降低電路1作時的耗電流。 ♦射 因此’本發明具有以下之優點： 1、 本發明不但可保有 雪、、古胜阽 補式門閂电路（Latch)的低靜態 “特性，且可使電路的工作速度大幅提昇。 2、 本發明不但能將高速差 办呈πη。、 门、是動“唬源除頻，且可產生正交（相 位差9 0 )信號，以做為山 上大為提高。u為除頻兼正仏號產生器’在功能 综上所述’依上文所揭示之内容 至“ 產生正m Γ ⑽向逮差動信號源除頻， 器電路，極具產業上利用之價值，差悲電流之除頻 請。.之知冑犮依法提出發明專利申 【圖式簡單說明】 第1圖係為本發明之實施例之電路圖。 第2圖係為第1圖之輸入端（IN)的時脈ά τ 之等效電路圖。 了脈由Low變High時 第3圖係為第！圖之輸入端（IN) 之等效電路圖。 由High Low時 第4圖係為本發明應用於頻率合成器之带 一 ^ ^ ^ 兒路方塊示意圖。 弟5圖係為習用除頻器之電路圖。 “ α 弟5Α圖係為苐5圖之輸入及輸出波形一立 义不思圖。 1301019 第6圖係為習用互補式除頻電路之電路圖。 第7圖係為第6圖之門閂電路之轉態分析圖。 第8圖係為習用SCL除頻電路之電路圖。 【主要元件符號說明】 第一、二級門閂電1路1、2 ' 輸入端 . 反相器 電晶體開關 φ 丽0S電晶體 輸出端 第一級門閂電路 第二級門閂電路_(M3'M4, M6, M7wm=5_QS terminal, source is grounded. ΜExtreme control clock input The two transistor switches (4), Μ2) are 汲 Crystal switch (Ml, M2) drain and source basket. And the transistor of the first stage latch circuit 1 is turned on ρ Mi " T-QB)' ” daytime off the gate of the Mi (IN); and the second stage gate flash circuit 2 is input to the gate of the day switch M2 The continuous input 301019 is connected to the negative input terminal (ΙΝβ), so that the two transistor switches (M2, M2) are respectively input to the differential signal control of the frequency divider circuit. Knife See Figure 2, which is the first! The equivalent circuit diagram of the clock of the complementary input terminal (IN) of the figure is L〇wf _. The transistor switch (M1) of the === level gate is turned on (τ—, etc. to form an on-resistance Rm〇s to provide two differential outputs (ου., - between - a low impedance equalization path. Temporarily weakening the positive feedback strength' and because the on-resistance (10) is connected to the two differential outputs at the same time ((4) mentioning a high transition speed, the output of the help state is turned into the [off-level gate circuit 2 is locked (Latch) electrical signal heart σ * is the advantage of a complementary circuit, so that the second stage latch circuit 2 consumes only a very low quiescent current. Conversely, when the input (IN) clock changes from High to L 〇 w, = 2:: as shown in Figure 3. At this time, the 'input terminal (INB) turns on the transistor switch (M2) of the second gate circuit 2, and the transistor switch of the first-level gate flash circuit i (M" is turned off, Then, the second-level gate circuit 2 can be turned on, and the first-level gate circuit "holds the electrical signal. " By the above-mentioned circuit configuration, the high-speed differential signal source can be divided, and the production is positive: 仏虎' The frequency of the quadrature signal is "2 of the signal source frequency, and can increase the south state transition speed and reduce the quiescent current. Moon and Moon> Read Figure 4 As shown in the figure, it is a schematic diagram of the circuit of the 2.4 GHz ISM Band: rate = device. The invention can be applied as a straight line: a high-speed frequency dividing circuit (9) v-^, Div-2). The iQ quadrature signal (uu, L (UB, L〇-Q, L〇-QB) can provide no 1301019 line connection = as down frequency and image rejection (imager tiQn) use ▲ and nickname by phase When the workpiece is phase-switched, the frequency divider of the variable divisor can be combined. In addition, the invention is applied to the above circuit system by the invention. The current consumption of the circuit 1 can be effectively reduced. The following advantages: 1. The invention not only can maintain the low static "characteristics of the snow, the ancient wins and the complementary latch circuit (Latch), and can greatly improve the working speed of the circuit. 2. The invention can not only carry out the high speed difference It is πη., Gate, is moving "唬 source frequency division, and can generate orthogonal (phase difference 9 0) signal, as a mountain to greatly improve. u is the frequency division and positive nickname generator' in the function summary Said 'in accordance with the content disclosed above to "generate positive m Γ (10) to capture the differential signal source The circuit is very valuable for industrial use, and the frequency of the sorrow current is limited. The knowledge of the invention is based on the law. [Simplified description of the drawing] Fig. 1 is a circuit diagram of an embodiment of the present invention. The figure is the equivalent circuit diagram of the clock τ of the input terminal (IN) of Fig. 1. When the pulse is changed from Low to High, the third diagram is the equivalent circuit diagram of the input terminal (IN) of the figure! The fourth picture of Low is the schematic diagram of the band of the invention used in the frequency synthesizer. The figure 5 is the circuit diagram of the conventional frequency divider. “The α Α 5Α diagram is the input of the 苐5 diagram and The output waveform is not justified. 1301019 Figure 6 is a circuit diagram of a conventional complementary frequency dividing circuit. Figure 7 is a transitional analysis diagram of the latch circuit of Figure 6. Figure 8 is a circuit diagram of a conventional SCL frequency dividing circuit. [Main component symbol description] First and second latches 1 and 1, 2' input. Inverter Transistor switch φ 丽 0S transistor Output terminal First stage latch circuit Second stage latch circuit
IN 、 INB 1卜 12、2卜 22 Ml > M2 M3 、 M4 、 M5 、 M6 、 M7 、 M8 OUT—I 、 OUT—IB 、 0UT_Q 、 OUT—QB al a2IN, INB 1 Bu 12, 2 Bu 22 Ml > M2 M3 , M4 , M5 , M6 , M7 , M8 OUT—I , OUT—IB , 0UT_Q , OUT—QB al a2