1300600 Α7 Β7 五、發明説明（） 在目前的覆晶封裝製程中，銲錫凸塊之合金組成主要 有63%錯(Pb)與37%錫（sn)之組合以.及鉛含量大於90%之 咼鉛與錫之組合。其中，高鉛之銲錫凸塊的熔點較63%錯 /37%錫之銲錫凸塊高。由於高鉛之銲錫凸塊能承受較大之 溫度變化，且具有較佳之抗接合疲勞能力，因此相當適合 於對性能要求較為嚴格之產品。 請參照第1圖至第5圖，其係繪示習知回銲覆晶封裝 的製程剖面圖。習知覆晶封裝製程係在積體電/路之晶片1〇〇 製作70成後’才進行晶片1 〇 〇之封裝製程，以進行晶片！ 與其它必要之電路零件的組合。首先，以沉積的方式在晶 片100上形成導電結構.（未繪示），再利用微影與蝕刻製程 對此導電結構進行圖案化步驟，而在晶片100之表面上形 成銲墊（pad)l02。銲墊102形成後，先沉積一層保護展1〇4 覆蓋在銲墊102與晶片100上，再利用微影與蝕封的方式 去除部分之保護層1〇4，藉以在銲墊1〇2上之保護層1〇4 中形成開口 106，而暴露出部分之銲墊1〇2，所形成之結構 如第1圖所示。 經濟部智慧財產局員工消費合作社印製 銲墊102與保護層104之結構形成後，以塗佈的方式 形成一層乾膜光阻層（Dry Film Photoresist Layer)i〇8覆蓋 在開口 106、開口 l〇6所暴露出之銲墊ι〇2、以及保護層 104上。接著，利用微影的方式圖案化乾膜光阻層1〇8，而 去除部分之乾膜光阻層108，藉以在乾膜光阻層1〇8與保 護層104中形成開口：π〇，並暴露出銲墊1〇2原先所暴露 4 本紙張尺度適用中國國家樣準（CNS ) Α4規格（2丨〇'〆297公釐） 1300600 A7 r—___ _ B7 五、發明説明（） 出的部分以及銲墊102周圍之保護層1〇4。開口 11〇形成 後，以印刷（Print)的方式將金羼材料填入開口 li〇中，而 使k些金屬材料覆盍在所暴露之銲塾1〇2與保護層1〇4 上，藉以在開口 110中形成銲錫凸塊112，所形成之結構 如第2圖所示。 然後，剝除乾膜光阻層108,而暴露出保護層1〇4。去 啤乾膜光阻層1〇8後，對銲锡凸塊i 12進行高溫回銲步驟， 藉以使銲錫a塊U2熔化而以表面能最低的球型狀態成 型，所形成之結構如第3圖所示。其中，上遠之回銲步驟 所使用之溫度會隨著銲錫凸塊112之錯含量的增加而提 古 冋 ° 鮮锡凸塊 1 1 2經©错而士、：f七处, u鲜而成球狀後，覆晶機台（未繪示） 吸附與銲錫凸塊112戶斤處之表面相對之晶片100的另一表 面’而將第3圖之結構予以翻轉倒覆。覆晶機台將所吸附 之晶片100上之銲錫凸塊112與助銲劑114接觸，而使助 銲劑114沾附於銲錫凸塊112上。助銲劑114是一種相當 強的活性劑，可將製程期間形成於銲錫…i 2上之氧化 物移除，以利後續銲锡凸塊112之銲接步驟的進行。當辉 錫凸塊u 2上沾附有助銲劑丨丨4時，將倒覆之晶片丨〇〇上 的知錫<〇7 :¾ η 2與封裝基材！ i 6上之輝塾】J 8對準後，再 將銲錫凸塊112麼合於封裝基材116之銲墊118上，如同 第圖所不#中’封裝基材116之材質-般係採用有機 材料。由於助銲劑Π4可侵兹掉鲜踢凸塊1]2上之氧化物， 本纸張尺度適财 (請先閲讀背面之注意事务再壤 .¾.. 頁 、11 經濟部智慧財產局員工消費合作社印製 1300600 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明説明（ 因此可使銲錫凸塊112與銲墊11 8產生直接的接觸。 接著，再次進行銲錫凸塊112之回銲步驟，藉以使銲 錫凸塊1 12產生熔化現象，而使銲錫凸塊丨丨2與封袭基材 116上之銲墊118接合在一起。當銲錫凸塊112與銲墊118 完成接合後，利用助銲劑清洗機台以及清洗助銲劑之溶劑 去除助銲劑H4，即完成晶片100之封裝製程中的覆晶步 驟，而形成如第5圖所示之結構。1300600 Α7 Β7 V. Inventive Note () In the current flip chip packaging process, the alloy composition of solder bumps is mainly composed of 63% (Pb) and 37% tin (sn) combined with lead content greater than 90%. The combination of lead and tin. Among them, the high-lead solder bump has a higher melting point than the 63% wrong /37% tin solder bump. Because high-lead solder bumps can withstand large temperature variations and have better resistance to joint fatigue, they are well suited for products with more stringent performance requirements. Referring to Figures 1 through 5, a cross-sectional view of a conventional reflow flip chip package is shown. The conventional flip-chip packaging process is performed on a wafer of integrated circuits/channels, and after 70% of fabrication, the wafer 1 封装 〇 packaging process is performed to perform wafer processing! Combination with other necessary circuit parts. First, a conductive structure is formed on the wafer 100 by deposition. (not shown), the conductive structure is patterned by a lithography and etching process, and a pad 1022 is formed on the surface of the wafer 100. . After the pad 102 is formed, a protective layer 1 4 is deposited on the pad 102 and the wafer 100, and a portion of the protective layer 1 〇 4 is removed by lithography and etching, thereby being on the pad 1 〇 2 The opening 106 is formed in the protective layer 1〇4, and a part of the pad 1〇2 is exposed, and the structure is formed as shown in FIG. After the structure of the printed pad 102 and the protective layer 104 is formed by the Intellectual Property Office of the Intellectual Property Office of the Ministry of Economic Affairs, a dry film photoresist layer (Dry Film Photoresist Layer) is formed by coating to cover the opening 106 and the opening l. The pad ι 2 exposed on the crucible 6 and the protective layer 104. Then, the dry film photoresist layer 1 〇 8 is patterned by lithography, and part of the dry film photoresist layer 108 is removed, thereby forming an opening in the dry film photoresist layer 1 〇 8 and the protective layer 104: π 〇, And exposed the solder pad 1〇2 originally exposed 4 paper scales applicable to China National Standard (CNS) Α 4 specifications (2丨〇'〆297 mm) 1300600 A7 r-___ _ B7 V. Invention description () The portion and the protective layer 1〇4 around the pad 102. After the opening 11 is formed, the metal material is filled into the opening li by printing, and the metal material is covered on the exposed solder joint 1〇2 and the protective layer 1〇4. A solder bump 112 is formed in the opening 110, and the formed structure is as shown in FIG. Then, the dry film photoresist layer 108 is stripped to expose the protective layer 1〇4. After the dry film photoresist layer 1〇8 is removed, the solder bump i 12 is subjected to a high temperature reflow step, whereby the solder a block U2 is melted and formed into a spherical state having the lowest surface energy, and the formed structure is as shown in the third. The figure shows. Among them, the temperature used in the reflowing step of the far-reaching solder will increase with the increase of the wrong content of the solder bumps 112. The fresh tin bumps 1 1 2 by the wrong, the: f, seven fresh After the ball is formed, the flip-chip machine (not shown) adsorbs the surface of the wafer 100 opposite to the surface of the solder bump 112, and flips the structure of FIG. The flip chip stage contacts the solder bumps 112 on the adsorbed wafer 100 with the flux 114, and the flux 114 is adhered to the solder bumps 112. Flux 114 is a relatively strong active agent that removes oxides formed on the solder i2 during processing to facilitate subsequent soldering steps of solder bumps 112. When the flux 丨丨4 is adhered to the tin bump u 2, the known tin <〇7:3⁄4 η 2 and the package substrate on the inverted wafer !! After the J 8 is aligned, the solder bumps 112 are then bonded to the pads 118 of the package substrate 116, as in the case of the package substrate 116 in the figure. organic material. Since the flux Π4 can invade the oxide on the fresh kicking bump 1]2, this paper scale is suitable for money (please read the attention of the back side of the transaction again. 3⁄4.. Page, 11 Ministry of Economic Affairs Intellectual Property Bureau staff consumption Cooperatives Printed 1300600 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed Β7 Β7 V. Invention Description (Therefore, the solder bumps 112 can be directly contacted with the pads 11 8. Next, the solder bumps 112 are re-welded again. Therefore, the solder bumps 12 are melted, and the solder bumps 2 are bonded to the pads 118 on the sealing substrate 116. When the solder bumps 112 are bonded to the pads 118, the help is utilized. The flux cleaning machine and the solvent cleaning flux flux removing flux H4 complete the flip chip step in the packaging process of the wafer 100 to form the structure as shown in FIG.
然而，由於南鉛銲錫凸塊之熔點較錯含舞低之鮮錫凸 塊的溶點高，因此進行高鉛銲錫凸塊之回銲步驟時，其溫 度較高，而有機材質之封裝基材無法承受此一回銲溫度I 如此一來，經回銲步驟後，封裝基材將產生變形，而嚴重 影響封裝製程的可靠度。 發明目的及概述： 雲於上述習知覆晶封裝製程中，有機之封裝墓材無法 承受高鉛銲錫凸塊之回銲溫度，而產生變形，造成封裝製 程的可靠度下降。其次，受到元件微縮化的影響，銲錫凸 塊經回銲後’相鄰之銲錫凸塊間容易發生橋接現象，而產 生短路，降低元件之電性品質。再者，封裝所使用之助鮮 劑不易清除’而助銲劑之殘留常引發腐蝕問題，嚴重影響 製程可靠度與產品良率。 曰 因此，本發明之主要目的之一就是在提供一種利用超 音波銲接之高鉛銲錫凸塊的封裳製程，不需對銲錫凸塊進 行回銲。如此-來’可使有機封裝基材應用於高錯鲜踢凸 6 家標準(CNS ) A4規格However, since the melting point of the south lead solder bump is higher than that of the low tin solder bump, the high soldering step of the high lead solder bump is higher, and the package material of the organic material is higher. Can not withstand this reflow temperature I As a result, after the reflow step, the package substrate will be deformed, which seriously affects the reliability of the packaging process. OBJECT AND SUMMARY OF THE INVENTION: In the above conventional flip chip packaging process, the organic package material cannot withstand the reflow temperature of the high-lead solder bump, and the deformation occurs, resulting in a decrease in the reliability of the packaging process. Secondly, due to the miniaturization of the components, the solder bumps are prone to bridging between the adjacent solder bumps after reflow, resulting in a short circuit and reducing the electrical quality of the components. Furthermore, the fluxing agent used in the package is not easy to remove, and the residue of the flux often causes corrosion problems, which seriously affects process reliability and product yield.曰 Therefore, one of the main objects of the present invention is to provide a high-lead solder bump using ultrasonic welding, which does not require reflow solder bumps. So - to make organic packaging substrates suitable for high-missing kicks 6 standard (CNS) A4 specifications
I3〇〇6〇〇 A7 ~^_____ ^B7 五、發明説明^ ^ 一 "〜一~~ 一〜-- 塊的封裝製程中。 *發明之另-目的就是因為銲錫凸塊不需經回銲即可 ^封裝基材之銲墊接合，因此可％ 思几 一 雖持鲜錫凸塊之高度，以 J後續填膠(Under-fill)步驟之進行。 本發明之另-目的就是因為銲錫凸塊不需回鐸使得 銲踢凸塊之形狀料柱狀，如此―來可降低銲錫凸塊間產 生橋接而短路的風險。因此，可庫 」應用於具細微間距之銲錫 凸塊的產品，應用性極廣。 本發明之又一目的就是因為利用超音波銲接的方式， 即可有效接合銲錫凸塊與封裝基材之銲塾，不需使用助鮮 劑。因此’除了可提高產品可靠度外，更可省下助銲劑、 助銲劑清洗機台、以及助銲劑清洗溶劑等的購置成本，減 輕成本負擔。另外，又因不使用助銲劑與助銲劑清洗溶劑'， 有利於環境的保護。 ^ 本發明之又一目的就是因為本發明之高鉛銲錫凸塊的 封裝製程不需使用助銲劑，亦不需進行回銲步驟，因此可 簡化製程步驟，進而提高產量。 本發明之再一目的就是利用橡膠吸嘴吸附晶片以進行 覆晶步驟，因此可使晶片上之銲錫凸塊與封裝基材上之銲 塾產生自我平坦化（Self Planarization)接合，進而提高封事 製程的可靠度。 根據以上所述之目的，本發明更提供了 一種利用超音 波銲接之高鉛銲錫凸塊覆晶封裝製程，至少包括下列步 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事見再填頁} 頁. 經濟部智慧財產局員工消費合作社印製 1300600 Λ7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（ 驟:首先’提供-晶片，其中此晶片之-表面上至少包括 複數個弟一銲墊以及一保護層覆蓋於部分之第一銲墊以及 基材上，1此保護層中至少包括複數個第—M 口，而.之此 第一開口暴露出另一部分之第一銲墊。接著，形成一乾ς 光阻層於上述之保護層上'其中此乾膜光阻層至少包、 數個第二開口 ’且這些第二開口暴露出上述之第一開口： 暴露出之第一銲墊以及位於第一開口周圍之保護層1再形 成複數個高錯銲錫凸塊於^述之第二開口與1 一開口中二 並覆蓋在這些第一開口所暴露出之第一銲墊^及第二開口 所暴露出之保護層上。然後，去除殘留之乾膜光阻層：： 暴露出保護層之一部分。接下來，提供一封裝基材，其中 此封裝基材上至少包括複數個第二銲墊，且這些第二鲜墊 之位置對應於上述之高鉛銲錫凸塊的位置。再進行一^音 波銲接步驟，藉以使上述之高鉛銲錫凸塊與相對應之第二 銲墊接合， ^ ^ ^ ^ ^ ^^ ^ ^ ^ — 其中，進行上述之覆晶步驟時，係使用橡膠吸嘴來吸 附Β曰片之另一表面，以在高鉛銲錫凸塊與第二銲塾鋒接 時，藉由軟質的橡膠吸嘴來達到自我平坦化的目的。 藉由超音波，可在高鉛銲錫凸塊與封裝基材上之第二 銲墊銲間產生局部兩溫，而將高鉛銲錫凸塊銲接在第二銲 塾鲜上。因此，熱影響區域（Heat Affect zone ; ΗΑΖ)大幅 縮小除了可防止有機材料所組成之封裝基材產生繆形， 達到提高製程可靠度的目的外，製程更具有相當高的應用 本紙張尺度適用中觸家襟準（CNS )〜規格（21()><297公鳌）I3〇〇6〇〇 A7 ~^_____ ^B7 V. Invention Description ^ ^ One "~1~~ One ~-- Block encapsulation process. *The other part of the invention - the purpose is that the solder bumps can be soldered to the package substrate without reflow soldering. Therefore, the height of the tin bumps can be increased by a few times, and the subsequent glue is filled in (Under- Fill) The step is carried out. Another object of the present invention is that the solder bumps do not need to be returned so that the shape of the solder bumps is columnar, thus reducing the risk of bridging and shorting between the solder bumps. Therefore, the library can be applied to products with fine pitch solder bumps for a wide range of applications. Another object of the present invention is to effectively bond the solder bumps to the solder pads of the package substrate by means of ultrasonic welding without using a freshener. Therefore, in addition to improving product reliability, the cost of purchasing flux, flux cleaning machine, and flux cleaning solvent can be saved, and the cost burden can be reduced. In addition, because it does not use flux and flux to clean the solvent', it is conducive to environmental protection. Another object of the present invention is that the high lead solder bump packaging process of the present invention does not require the use of flux and does not require a reflow step, thereby simplifying the process steps and thereby increasing throughput. A further object of the present invention is to use a rubber nozzle to adsorb a wafer for a flip chip step, thereby enabling self-planarization of the solder bumps on the wafer and the solder bumps on the package substrate, thereby improving the sealing process. Process reliability. According to the above object, the present invention further provides a high-lead solder bump flip chip packaging process using ultrasonic welding, which comprises at least the following steps: the Chinese National Standard (CNS) A4 specification (210×297 mm) ( Please read the note on the back first and then fill in the page} Page. Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 1300600 Λ7 B7 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 5, Invention Description (Step: First of all - provide - wafer, Wherein the surface of the wafer includes at least a plurality of pads and a protective layer covering a portion of the first pad and the substrate, wherein the protective layer includes at least a plurality of M-th ports, and The first opening exposes another portion of the first pad. Then, a dry photoresist layer is formed on the protective layer, wherein the dry film photoresist layer includes at least a plurality of second openings and the second openings are exposed The first opening is: the exposed first pad and the protective layer 1 around the first opening form a plurality of high-error solder bumps in the second opening and the first opening And covering the first soldering pad exposed by the first openings and the protective layer exposed by the second opening. Then, removing the residual dry film photoresist layer:: exposing one part of the protective layer. Next, Providing a package substrate, wherein the package substrate comprises at least a plurality of second pads, and the positions of the second fresh pads correspond to the positions of the high-lead solder bumps described above. The high-lead solder bump is bonded to the corresponding second pad, ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ - wherein, in the above-mentioned flip chip step, the rubber nozzle is used to adsorb the wafer The other surface is used to achieve self-flattening by a soft rubber nozzle when the high-lead solder bumps are connected to the second solder bump. Ultra-sonic, high-lead solder bumps and package bases can be used. The second pad welding on the material produces localized two temperatures, while the high-lead solder bumps are soldered to the second solder bump. Therefore, the heat affected zone (Heat Affect zone; ΗΑΖ) is greatly reduced except for the organic material. The package substrate formed by the formation of a dome shape, To improve the reliability of the process object of the external system, more processes of the present application has a relatively high sheet in contact lapel home registration (CNS) ~ size suitable scale (21 () > < 297 well Ao)
A7 B7 1300600 五、發明説明（） 壓合的區域，而將銲錫凸塊212銲接於第二銲塾22〇上。 ............... (請先閲讀背面之注意事項再填寫00 請參照第11圖，將銲錫凸塊212銲接於封裝基材218 之第二銲墊220上後，覆晶機台214停止抽氣，而使覆晶 機台214之橡膠吸嘴216釋放晶片2〇〇，並移開覆晶機台 214。如此一來，即已藉由銲錫凸塊212以及第二銲墊22〇 順利將晶片200與封裝基材21 8銲接在一起。之後，便可 進行下一道填膠步驟，而將封膠(Encapsulant)填入晶片200 之保護層204與封裝基材218之間的空隙。 本發明之一特徵在於本發明於銲錫凸塊形成後並不進 行咼溫回銲步驟，而使銲錫凸塊之形狀維持柱狀，進而使 銲錫凸塊之高度較習知球狀銲錫凸塊高。因此，不僅可避 免具微細間距之銲錫凸塊產生橋接而引發短路，更有利於 後續填膠步驟之進行。 本發明之另一特徵則在於本發明利用超音波來銲接銲 錫凸塊與封裝基材上之第二銲墊，因此不需使用助銲劑， 亦無需藉助回銲來接合銲錫凸塊與封裝基材上之第二銲 墊。如此一來，可簡化製程步驟，省下使用助銲劑之成本。 綜合上述’本發明之一優點就是因為不需藉助高溫回 銲步驟即可完成銲錫凸塊與封裝基材上之第二銲墊間的接 經濟部智慧財產局員工消費合作社印製 合。因此’有機材料之封裝基材亦可應用於高鉛銲錫凸塊 的封裝製程中。 本發明之另一優點就是因為銲錫凸塊不經回銲，而使 桿錫凸塊之高度可獲得維持。如此一來，除了可防止具微 12 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 1300600 A7 B7 五、發明説明（ 經濟部智慧財產局員工消費合作社印製 細間距之銲錫凸塊產生橋接而影響電性品質 M i 、 文有利於 後續填勝步驟之進行。因此，本發明之封裝製程不僅具有 極佳之應用性，並可達到提高製程可靠度與產品良率的目 的。 本發明之又一優點就是因為本發明之封装製程不需使 用助銲劑。因此，可防止助銲劑造成元件腐蝕，提高產品 可靠度，並可省下助銲劑、助銲劑清洗機台、以及助銲劑 清洗溶劑等成本，達到降低成本的目的。而且，應用本發 明可降低對生態環境的影響。 本發明之又一優點就是因爲本發明毋需對高鉛銲錫凸 塊上助銲劑，亦不需進行回銲步驟。因此，可簡化製程步 驟’達到提高產量的目的。 本發明之再一優點就是因為利用橡膠吸嘴來進行覆晶 步驟時，可利用橡膠吸嘴的軟質特性，使銲錫凸塊與封裝 基材上之第二銲墊產生自我平坦化接合。因此，可達到提 升製程可靠度的目的。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍’·凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 圖式簡單說明： 本發明的較佳實施例已於前述之說明文字中辅以下列 圖形做更詳細的闡述，其中： (請先閱讀背面之注意事項再填寫¥) 13 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公爱) 1300600 A7 B7 五、發明説明（） 第1圖至第5圖係繪示習知回銲覆晶封裝的製程剖面 圖；以及 第6圖至第1 1圖係繪示本發明較佳實施例之高鉛銲錫 凸塊之覆晶封裝的製程剖面圖。 圖號對照說明： 100 晶 片 102 銲 墊 104 保 護 層 106 開 Ώ 108 乾 膜 光 阻層 1 10 開 口 112 銲 錫 凸 塊 114 助 銲 劑 116 封 裝 基 材 118 銲 墊 200 晶 片 202 第 一 銲 墊 204 保 護 層 206 第 一 開 Π 208 光 阻 層 210 第 二 開 口 212 銲 錫 凸 塊 214 覆 晶 機 台 216 橡膠 吸 嘴 218 封 裝 基 材 220 第 銲 墊 ...............^: {請先閲讀背面之注意事項再場寫mk) 訂· 綉 經濟部智慧財產局員工消費合作社印製 14 本紙張尺度適用’中國國家標準(CNS)A4規格(210 X 297公釐)A7 B7 1300600 V. Inventive Description () The pressed area is soldered to the second pad 22 。. ............... (Please read the precautions on the back and fill in the 00. Please refer to Figure 11 to solder the solder bumps 212 to the second pads 220 of the package substrate 218. Thereafter, the flip-chip station 214 stops pumping, and the rubber nozzle 216 of the flip-chip station 214 releases the wafer 2 and removes the flip-chip station 214. Thus, the solder bump 212 has been removed. And the second bonding pad 22 〇 smoothly solders the wafer 200 to the package substrate 218. Thereafter, the next filling step can be performed, and the encapsulant is filled into the protective layer 204 and the package base of the wafer 200. The gap between the materials 218. One of the features of the present invention is that the present invention does not perform the temperature reflow soldering step after the solder bumps are formed, and the shape of the solder bumps is maintained in a columnar shape, so that the height of the solder bumps is higher than that of the conventional balls. The solder bumps are high. Therefore, not only the solder bumps with fine pitches can be bridged to cause short circuit, but also the subsequent glue filling step is facilitated. Another feature of the present invention is that the present invention uses ultrasonic waves to solder solder. The bump and the second pad on the package substrate, so no soldering is required The solder does not need to be soldered to bond the solder bumps to the second pads on the package substrate. This simplifies the process steps and saves the cost of using the flux. The solder joint between the solder bump and the second solder pad on the package substrate can be printed without the need of a high-temperature reflow step. Therefore, the packaging material of the organic material can also be applied. Another advantage of the present invention is that the height of the rod tin bump can be maintained because the solder bump is not reflowed, so that it can prevent the paper from being micro 12 sheets. The scale applies to China National Standard (CNS) A4 specification (210X 297 mm) 1300600 A7 B7 V. Invention Description (The Ministry of Economic Affairs, Intellectual Property Office, Staff Consumer Cooperative, prints fine pitch solder bumps to bridge and affect electrical quality M i , The invention facilitates the subsequent filling step. Therefore, the packaging process of the invention not only has excellent applicability, but also achieves the purpose of improving process reliability and product yield. Another advantage of the invention is that the packaging process of the present invention does not require the use of flux, thereby preventing component corrosion caused by the flux, improving product reliability, and saving flux, flux cleaning machine, and flux cleaning. Solvent and other costs can achieve the purpose of reducing costs. Moreover, the application of the present invention can reduce the impact on the ecological environment. Another advantage of the present invention is that the present invention does not require a flux on the high-lead solder bumps. The welding step. Therefore, the process step can be simplified to achieve the purpose of increasing the yield. Another advantage of the present invention is that the use of the rubber nozzle for the flip chip step can utilize the soft characteristics of the rubber nozzle to make the solder bump and the package The second pad on the substrate creates a self-flattening bond. Therefore, the purpose of improving process reliability can be achieved. The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the invention as defined by the present invention. Equivalent changes or modifications are intended to be included in the scope of the claims below. Brief Description of the Drawings: The preferred embodiment of the present invention has been explained in more detail in the above description with the following figures, wherein: (Please read the notes on the back and then fill in the ¥) 13 The paper size applies to the Chinese country. Standard (CNS) A4 specification (210X 297 public) 1300600 A7 B7 V. Description of invention (1) Figure 5 to Figure 5 shows a process sectional view of a conventional reflow flip chip package; and Fig. 6 to 1 1 is a cross-sectional view showing a process of a flip chip package of a high-lead solder bump according to a preferred embodiment of the present invention. Figure number comparison description: 100 wafer 102 pad 104 protective layer 106 opening 108 dry film photoresist layer 1 10 opening 112 solder bump 114 flux 116 package substrate 118 pad 200 wafer 202 first pad 204 protective layer 206 First opening 208 photoresist layer 210 second opening 212 solder bump 214 flip chip machine 216 rubber nozzle 218 package substrate 220 first pad ...............^: {Please read the notes on the back and write mk again) Order · Embroidery Ministry of Economic Affairs Intellectual Property Bureau Employees Consumption Cooperative Printed 14 Paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm)