TWI300573B - Semiconductor memory and memory system - Google Patents

Description

1300573 IX. Description of the Invention: Field of the Invention 3 Field of the Invention The present invention relates to a semiconductor memory capable of changing the address space size and a memory system in which the semiconductor memory is mounted. I. Prior Art 3 BACKGROUND OF THE INVENTION Generally, the address space size of a semiconductor memory is fixed. In the design of a system in which a semiconductor memory is mounted, the number of semiconductor memories 10 mounted in the system takes into account the address space size of the semiconductor memory. Decide. At this time, once there is an unusable memory area that cannot be accessed in the semiconductor memory of SiS, the cost of the system increases, and unnecessary power is consumed. In order to solve this drawback, a semiconductor memory capable of changing the size of the address space has been proposed (for example, refer to Patent Document 1). 15 [Patent Document 丨] Japanese Patent Laid-Open Publication No. 2002-245780

C Mingzhong J Reveals the problem to be solved by the invention When changing the address space size of the semiconductor memory, it is necessary to change the set value of the temporary storage device or the like. In a typical system, since the size of the address space is fixed, the size of the address space cannot be switched when the system is operating. However, the memory capacity required for the operation of the system varies depending on the mode of operation of the system. At this time, the size of the address space is set in accordance with the operation mode required for the maximum memory capacity. Therefore, in the operation mode 1300573 in which the redundant memory capacity is small, there is an unnecessary memory area that cannot be accessed, and it consumes unnecessary power. On the other hand, in order to minimize the power consumption, the address space size is set in accordance with the operation mode in which the memory capacity is small. At this time, each time you switch to another operation mode with a larger memory capacity, you need to set the size of the address space. In general, since the access operation cannot be performed during the switching of the address space size, the access efficiency is lowered due to the re-setting of the size. In order to improve the access efficiency, when the size of the address space is set large, as described above, unnecessary power is consumed. 10 The object of the present invention is to access a cell array while minimizing power consumption without reducing access efficiency. Solution to Problem In one aspect of the invention, the plurality of cell arrays are assigned different addresses. The access information unit keeps displaying the number of the aforementioned array of cells activated at the same time and takes valid information. The array control unit, in response to a forced access request from outside the semiconductor memory, forcibly activates a single array 70 that does not correspond to the access effective information set in the access information unit. Thereby, the cell array that does not correspond to the access valid information and is passivated can be activated before the access request is provided. Therefore, when the number of simultaneously activated cell arrays is small, it can be performed without interrupting the access operation. Further, since it is not necessary to change the content of the access information unit, it is not necessary to access the access information in order to rewrite the effective information. As a result, power consumption can be minimized without degrading the access efficiency, and the cell array can be accessed. In a preferred embodiment of the present invention, the access detecting unit detects in advance the access of the plurality of the cell arrays by 1300573 5 10 15 20, and detects in advance the access of the cell array corresponding to the access valid information. And performing access to the cell array that does not correspond to the foregoing access valid information. The array control unit, in response to the detection by the access detecting unit, forcibly activates access to the cell array that does not correspond to the access valid information, and performs an access operation. For example, the semiconductor memory includes an address counter that operates in a burst access mode to sequentially generate internal access bits subsequent to an external access address provided from outside the semiconductor memory. site. The access detecting unit performs the detecting operation in accordance with the external access address. By continuous access, in the execution of the unfinished series of pieces, by means of prior information, 2 without interruption of access, continuous execution. The cell array that is not allowed to access is activated and activated. Therefore, the unit array can be accessed by minimizing the power consumption without degrading the access efficiency. A preferred example of the storage state is that when the execution of the unary corresponding access to the complex unit array single-fish τ take-out detecting unit is performed, the second::::::: :广阵(四)取动控哭之(四)# Conductor of semiconductor memory: the situation: return to the signal, judge whether to execute or stop the cell array that does not correspond to the half-access valid information, the right non-correspondence device stops accessing action. Thereby, the access operation of the cell array for controlling the access of the effective information can be stopped if the operation is not performed. (4) The cell array 1300573 that does not correspond to access to the information is activated in response to the detection by the access detection unit. Therefore, the power consumption can be minimized without the access efficiency being lowered, and the cell array can be accessed. Effect of the Invention The power consumption can be minimized without reducing the access efficiency, and the cell array can be accessed. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a semiconductor memory device according to a first embodiment of the present invention. Fig. 2 is a block diagram showing the details of the cell array shown in Fig. 1. Fig. 3 is an explanatory diagram showing the allocation of the address of the setting contents of the access register shown in Fig. 1. Fig. 4 is a block diagram showing a memory system in which the memory shown in Fig. 1 is mounted. 15 Fig. 5 is a timing chart showing the access operation when the valid information setting logic 1 is accessed in the memory shown in Fig. 1. Fig. 6 is a block diagram showing a semiconductor memory device according to a second embodiment of the present invention. Fig. 7 is a view showing 20 pieces of the memory system in which the memory shown in Fig. 6 is mounted. Fig. 8 is a block diagram showing a semiconductor memory device according to a third embodiment of the present invention. Fig. 9 is a block diagram showing a semiconductor memory device according to a fourth embodiment of the present invention. Fig. 10 is a block diagram showing a semiconductor memory device according to a fifth embodiment of the present invention. Fig. 11 is a block diagram showing a semiconductor memory device according to a sixth embodiment of the present invention. [Embodiment] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described using the drawings. In the figure, the apostrophe line indicated by a thick line is composed of a plurality of bars. One of the blocks connecting the thick lines is composed of a plurality of circuits. The signal line that conveys the signal uses the same number as the signal name. The double circles in the figure indicate external terminals. Fig. 1 shows a semiconductor memory device according to a first embodiment of the present invention. The semiconductor brother system reproduces in synchronization with the clock CLK and has an SDRAM of a dynamic memory unit. The memory MEM has a command input unit 1 , a mode register 12 , a clock input unit 14 , an address input unit 16 , 18 , a data input and output , an I5 20 , an address counter 22 , an access detection unit 24 , and an array control Part% and memory core 28. The command input unit 1 receives the command provided by the command terminal (:]^1), and outputs the received command CMD to the array control unit 26. In this implementation, the access command (read command, write command, update command), temporary register setting command, forced access command (forced access request), and forced access release command are used as the command CMD. It is supplied to the command input unit 1〇. When the read command and the write command are executed in the memory cell MC2 access operation (read access operation and write access operation) of the memory cell array ARY, they are provided together with the addresses ra and CA. The update command is provided in the memory unit update action ^300573^. The command input unit is decremented _ access command to receive the forced release command, and the _ access request signal FREQ is activated.

10 The forced access command and the forced access release command are commands that are supplied to the memory MEM only when the access address is temporarily stored in the HACSR_^ access valid account. Strong (four) take command and _ access release material and column address RAILI3- job. At this time, the column 2]32 indicates the sub-cell array SARA which is activated for forced access or the sub-cell array SARY〇_3 which is purified to stop the forced access. By the command input unit 1 〇 receiving strong, the access command ' can activate the passivated sub-reading column SARY age j without setting a special terminal. That is, as will be described later, the sub-cell array which does not correspond to the number of access effective information AINFs can be activated from the lamp. The mode register 12 has a register BUSTR and an access temporary crying ACSR. The mode register 12 has a temporary storage 9 for determining the CAS latency in addition to the drawing. The CAS latency indicates the number of clock cycles from the acceptance of the read command to the round-up read 15 data. The shell burst register BUSTR maintains the length of the burst. The burst length indicates the number of data signals input and output in response to a read command or a write command. For example, the type of burst length has "1", "4,," "8,," "full burst,". The eight bursts provide read commands or write commands until the next command is provided. The mode of output or input of 20 consecutive data. The mode register 12 is set to "B", "8," and "Full Crowd," when the burst is stored in the burst BUSTR. The array control unit 26, which will be described later, operates in the burst access mode when the burst signal BUST^^. The access register ACSR keeps displaying the sub-cell array shown in Fig. 2] 1300573 SARY〇_3 At the same time, the activation or activation-activated access information is used to output the valid information of the access as an effective signal for access. In this example, the access to the effective information F and the access valid signal are When the low level (logic 〇), all the sub-units RYQ 3 are simultaneously activated. When accessing the valid information a trace and accessing the effective signal outline high level (logic 1), the general access In the action, the sub-cell array sary〇_3 is activated, and the other sub-cell array sARY^ is activated. The access temporary storage IsACSR has a function of setting an access information portion for displaying the access effective information of the number of sub-unit arrays SARY0-3 activated at the same time. 1〇 The mode register 12 is provided in accordance with the register setting command MRS. The addresses RA and CA are set to a value of 兀. Therefore, the access effective information AINF indicating the number of simultaneously activated sub-unit arrays SARY can be set without setting a special terminal. Further, the mode mode register 12 can be set according to the bit value of the data, or can be set according to the bit value of the address RA, CA and the data DT. If the 15 terminal is used, the burst register BUSTR and the access register are set. ACSR can minimize the cycle time required for 5 。. As a result, the access efficiency of the read access or write access memory cell array ARY can be prevented from decreasing. The clock input unit 14 is clocked with the signal CKE. When the activation is performed, the external clock CLK is output as the internal time ICLK, and when the passivation of the clock enable signal 20 CKE is performed, the generation of the internal clock ICLK is stopped. The internal clock CLK is the clock input portion 14 of the MEM memory. Except for each circuit block The address input unit 16 receives the column address RA12-13 and the block address CA7-8 provided by the address terminal AD. The address input unit 16 receives the low level access valid letter 11 1300573 AINF The received address (5) is the array selection address SA (M and output, and the received column address RA12_13 is used as the array selection address during the period of receiving the high-level access valid signal a· 1. Output. The array selection address SA0-m is used to select any one of the sub-unit 5 arrays SARY0-3 shown in Fig. 2. The address input unit 18 receives the column address provided by the address terminal AD. After the address CA0-6, the received address R is output to the address counter 22 at 〇_6. The column address RA (M1 is used to select the word line muscle described later. In this case, the column address RA and the block address CA are simultaneously supplied to the dedicated bit address terminals RA, CA. That is, this memory The body mem is in the address non-multiplex mode. When the data input/output unit 20 reads the data, the data output from the memory core 28 is output to the data terminal DT (DT0-7) by the data bus DB. During the write operation, the write data received by the data terminal DT is output to the memory core 28 via the data bus DB DB. The data terminal 〇1 15 is a terminal common to the read data and the write data. The address counter 22 is When the length of the burst register BUSTR is '1'', the received addresses RAO-11, CA〇-6, SA〇-1 are directly output. The address counter 22 is the burst register. When the length of the BUSTR setting is "4,," "8" or "full burst", it will connect to the received address CA〇_6, sAO-丨 (outside 20 access addresses), CA0_6, SA0 -1 (internal access address) is generated by sequentially generating the number of burst lengths. In addition, the address counter 22 can also sequentially increase the column address RA0-11. The access detecting unit 24 operates only when the valid access information AINF of the access register ACSR is held at logic 1. When the access detector 24 is in the burst access mode 12 1300573, the monitoring is output from the address counter 22 After accessing the addresses CAO-6, SA0-1, and detecting the access of the sub-cell array SARY (for example, SARY0) activated in response to the access command, the execution of the other sub-cell array SARY (for example, SARY1) is performed. The detection signal DET is activated. The details of the operation of the access 5 detection will be described later in Fig. 5. The array control unit 26 performs the access operation of the memory core 28 and returns

10 15

20 The control signal CNT output of the memory cell array ARY should be accessed by accessing the command CMD. The control signal CNT is useful for selecting the word line control signal WLZ of the word line WL, the sense amplifier control signal SAZ for activating the sense amplifier SA, and the column control signal CLZ for selecting the column switch for using the bit line Line BL, /BL precharge precharge control signal pREZ, etc.

Further, the array control unit 26 receives the low-level access valid signal AINF and activates all of the activation signals ACT0-3. When receiving the high-level access valid signal 八11>, the array control unit 26 activates only the borrowed array selection address SA (M selected sub-cell array SARY〇_3, and activates the signal ACT0). -3 is activated - the activation of the activation signal act〇-r, respectively, activates the sub-cell array SARY0-3. That is, the array control unit % responds to the access command, transfers the valid NF, and all the sub-units Array SARY0-3 activates 'or activates one of the beans of the sub-cell array sa. The access (4) HACSR is surrounded by the information of the sub-cell array 3 Selecting the address s, the sub-cell array SARY0-3 is activated, and the array control unit 26 can be deleted from the access valid signal 13 1300573 to receive the forced access request signal. When the FREQ is activated, the activation signal ACT of the sub-array array SARY corresponding to the column address address RA12-13 (=array selection address SA(M)) which is provided together with the forced access command is forcibly activated. That is, the array control unit 26 Respond to mandatory access request FREQ, but will not be set to 5 The sub-cell array SARY of the access valid information of the register ACSR is forcibly activated. Therefore, the access operation is not interrupted for rewriting the access valid information AINF. As a result, the access efficiency can be reduced without reducing the access efficiency. When the detection signal DET is activated when the burst signal BUST is activated (when the burst memory 10 is activated), the array control unit 26 performs the access operation. In addition to the active sub-cell array SARY (for example, SARY0), other sub-cell arrays (for example, SARY1) are forcibly activated. Thus, in the burst access mode, two sub-cell arrays SARY are covered. When the access operation is performed, it can be executed without interrupting the access operation. 15 The memory core 28 has a memory cell array ARY, a column decoder RDEC, a sense amplifier SA, a column switch CSW, a column decoder CDEC, and a sense amplifier. RA and write amplifier WA. The memory cell array ARY has a dynamic memory cell MC, a word line WL connected to the dynamic memory cell MC, and bit line pairs BL, /BL. The memory cell MC is formed on the word line WL. Bit 20 is the intersection of BL and /BL. The column decoder RDEC responds to the access command and the update command, and decodes the column address RAD to select any of the word lines WL. The column decoder CDEC responds The access command is used to decode the column address CAD to select 8 sets of bit line pairs BL, /BL corresponding to the number of bits of the data terminal DT. 14 1300573 The sense amplifier SA will be bit line pair BL, /BL The difference between the semaphores of the read data signals is amplified. The column switch CSW connects the bit lines BL and /BL to the data bus line DB according to the column address CAD. The sense amplifier RA amplifies the complementary read data output by the column switch CSW during the read operation. When the write-in amplifier WA is in the write operation, it is supplied to the bit line pair BL, /BL by the complementary write data supplied from the data bus DB. Fig. 2 shows the detailed contents of the memory cell array ary shown in Fig. 1. In the figure, the memory cell array ARY corresponding to the data terminal DT0 is displayed. Actually, the bit line pair BL, /BL corresponds to the data terminal DT 〇 -7 and is divided into 10 wires. The memory cell array ARY has four sub cell arrays SARY0-3. The sub-cell array SARY0-3 has the same memory capacity and is selected according to the array selection address SA0_1. That is, the sub-cell array SARY〇-3 is assigned a different address. The array selection address SA0-1 is provided by the column address CA7-8 when the access register 8 (:; 511 is set to the lower 15 access valid information AINF as described above, and when the access is temporarily stored as the ACSR. When the high-level access valid information AINF is set, it is provided by the column address RA12-13. 存取 When the access temporary memory is set to the ACSR setting low-level access valid information AINF, the access command is responded to, and all the sub-units are responded to. The array SARY〇_3 2〇 is simultaneously activated. For example, when the array selection address SA0-1 shows "11", when the sub-cell array SARY3 is accessed (for example, the word line WL2), the other sub-cell array SARY 1 -2 The word line WL2 is also activated in synchronization with the activation of the sub-cell array sARY3. On the other hand, when the access register ACSR is set to a high level access, there is a 15 1300573 effect information AINF, and the access command is responded only to Any one of the sub-cell arrays SARY0_3 corresponding to the array selection address SA0-1 is activated. For example, when the array selection address SA0-1 displays "〇〇", the sub-cell array SARY0 (for example, the word line WL1) is accessed. , other sub-cell arrays · γι_3 word line 5 WL1 is not activated. Figure 3 shows the root According to the allocation of the address valley of the access register ACSR shown in Figure 1, when the access valid information AINF is set to logic 〇 (low level), the keeper will use the column address CA7-8 as the array selection. The address SA is supplied to the memory core 28. At this time, the sub-cell array Sary〇_3 is selected according to the column address CA7-8 ίο. Therefore, in the access operation, all the sub-cell arrays saryo-3 are selected. When the access valid information AINF is set to logic ι (high level), the column address R A12 _ 13 is supplied to the memory core 28 as the array selection address s A 0 - 1. At this time, the secondary unit array SARY〇-3 is selected according to the address RA12-13. In this case, during the access operation, any one of the sub-cell arrays SARY0-3 of the column address RA12-13 is activated. The memory system of the memory mem shown in Fig. 1. The memory system is formed as a system package SIP (System In Package) stacked on a substrate. The SIP has a memory controller 20 MCNT1 for accessing the memory MEM. Flash memory FLASH, memory controller MCNT2 for accessing flash memory FLASti and control system The CPU and the memory controller MCNT1-2 are connected by the system bus SBUS. The CPU is the access memory MEM, and the output access command CMD, the external address AD and the write data DT are controlled by the memory. The device MCNT1 receives the read 16 1300573 data DT from the memory MEM. Fig. 5 shows the access operation when the access valid information AINF is set to logic 1 in the memory] VIEM shown in Fig. 1. In this example, after the burst access operation of the sub-element array SARY0 is performed, the access operation of the sub-cell array SARY1 5 is performed. When the column address RA12-13 is "0," the sub cell array SARY is selected. In this example, the burst register BUSTR is set to "full plex,". Therefore, each time the block address CA0-6 is accessed, the carry increment is incremented from "〇," to "63". When the address of the address CA0-6 is rounded, the column address is still maintained. In the case of raO-11 (in this case, 10 204), the sub-cell array SARY0 is passivated, and the sub-cell array SARY1 is activated. Thus, the sub-cell array SARY can be sequentially accessed without increasing the activation domain. 15 20 The access detecting unit 24 shown in Fig. 1 synchronizes with the fourth access (CA〇_6=6〇) from the last of the sub-cell array SARY〇, and demodulates the detection signal det. 26 is activated with the detection signal, and activates the activation signal VIII(3) in order to activate the sub-single array SARY1. The sub-cell array sARYm should activate the signal ACT1, and perform the last three tree actions in the sub-cell array sar. (4) The power generation circuit (10) that generates power supply (four) rdec power generation circuit (10), such as boost voltage generation, negative voltage generation circuit) or the power generation circuit of the power supply for sensing amplification (for example, boost voltage generation circuit, negative power generation, electric activation) Finally, after the completion of the access operation of sary〇, the subunit will be started from the next one. In the operation of reading the phantom, that is, in order to reduce the returning power, in the operation of only one sub-cell array SARY, the surface operation is not stopped during the switching period of the sub-cell array 17 1300573 SARY0-1. After the activation of the sub-cell array SARY1, the sub-cell array SARY0 that has completed the access operation is purified (ACT0=low level). Therefore, the power consumption can be reduced without reducing the access efficiency. In the first embodiment, the sub-cell array SARY that does not correspond to the number of access valid information AINF is forcibly activated before the access command is provided. When the number of sub-cell arrays SARY is small, the access operation can be performed without interrupting the access operation. Further, since the access valid information AINF is not required to be set, the access operation is not interrupted for rewriting the access valid information AINF. By not reducing the access efficiency, the power consumption can be minimized, and the cell array can be accessed. Further, by the continuous access of the burst access operation, the sub-cell array for the unallowed access is executed. When the SARY access operation is performed, the pre-borrowing access detecting unit 24 detects the information, and has the margin to activate the sub-cell array for the next access. 15 Therefore, the access can be continuously performed without interrupting the access. When the continuous access is automatically performed inside the memory MEM, the controller for accessing the memory can be easily controlled by activating the sub-cell array SARY of the next access in advance to prevent interruption of the access. The semiconductor memory of the second embodiment of the present invention is the same as the one described in the first embodiment, and the same reference numerals are given to the same components, and the detailed description thereof will be omitted. The semiconductor memory MEM of this embodiment has a detection terminal DET for outputting the detection signal DET outputted from the access detecting unit 24 to the outside of the memory MEM. The other structure is the same as that of the first embodiment. That is, the semiconductor memory MEM forms an SDRAM. 1300573 Fig. 7 shows a memory system equipped with the memory MEM shown in Fig. 6. The difference from the first embodiment is that the detection signal DET is transmitted from the memory MEM to the memory controller MCNT1. The memory controller MCNT1 includes a control unit CNT1 that determines activation of the detection signal DET for performing an access operation of the sub-cell array SARY that does not correspond to the memory information AINF, and determines to stop or continue the memory MEM. access. The other structure is the same as in Fig. 4. For example, as shown in FIG. 5 above, in the burst access mode, after the access operation to the sub-cell array SARY that allows access, 10 pairs of sub-cell arrays SARY that are not allowed to access are executed. During the access operation, the memory controller MCNT1 accessing the memory MEM cannot recognize the sub-cell array SARY to be activated for switching. At this time, by transmitting the detection signal DET to the memory controller MCNT1, the control unit CNT1 of the memory controller MCNT1 can respond to the detection signal DET, and judge whether to execute or stop the access of the sub-cell array 15 SARY which is not allowed to access. action. For example, if the access operation of the sub-cell array SARY corresponding to the access valid information AINF is an erroneous operation, the memory controller MCNT1 stops the access operation. In this way, stop unnecessary access. If the access operation of the sub-cell array SARY that does not correspond to the access valid information AINF is normal operation, the memory controller MCNT1 continues to access the operation. As described above, in the second embodiment, the same effects as those of the above-described third embodiment can be obtained. Furthermore, in this embodiment, by transmitting the detection signal det to the memory controller MCNT1, the memory controller MCNT1 can judge to continue or stop the access. As a result, since the access operation of the stomach due to the erroneous operation can be prevented, the power consumption can be minimized and the cell array can be accessed without reducing the access efficiency. Fig. 8 shows a + conductor memory according to a third embodiment of the present invention. The same elements as those of the first and second sacred elements are attached with the same reference numerals, and the same is omitted (4). The semiconductor memory MEM of this embodiment has a command input circuit 10B and an array control unit 26β in place of the command input circuit ίο and the array control unit 26 of the first embodiment. Further, the semiconductor memory MEM has a dedicated forced access *FREq for receiving a forced access request FREQ. The other structure is the same as that of the i-th embodiment. That is, the semiconductor memory forms 10 SDRAM. The array control unit 26B responds to the forced access request FREQ received by the forced access request terminal FREq, and forcibly activates all the sub-unit arrays sary〇_3 "activation 彳 唬 唬 〇 10-3. Namely, the array control unit 26B responds to the forced access request FREQ, and forcibly activates the sub-unit array sARY which is not associated with the access 15 active AINF of the access register ACSR. In this embodiment, since the activated sub-cell array SARY and the forced access request FREQ are not required to be specified, the memory controller MCNT1 (not shown) is not based on the input specification of the command, but may be any Time provides mandatory access to FREQ. Since the command terminal 20 CMD, the address terminals RA0-13, CA0-8, and the data terminal DT〇_7 are not used, the forced access request FREQ can be provided, so the next execution can be performed without interrupting the access operation. The sub-cell array SARY of the access action is activated. In addition, although not shown in the figure, the memory controller]^(:]^1[1 has the output forced access request FREQ forced access request terminal FREq instead of the detection terminal of the detection signal DET shown in the seventh 1300573 The other structure of the memory system is the same as that of Fig. 7. In the third embodiment, the same effects as those of the above-described third embodiment can be obtained. Further, in this embodiment, the general storage is not used. The sub-cell array SARY that does not correspond to the access valid information AINF can be forcibly activated by taking the terminal used for the 5 action. As a result, the sub-cell array SARY can be accessed without lowering the access efficiency. FIG. 9 shows the present invention. The semiconductor memory of the fourth embodiment is denoted by the same reference numerals as those of the first embodiment, and the detailed description is omitted. The semiconductor memory MEM of this embodiment has a mode temporary storage. 12C replaces the mode register I] of the first embodiment. Further, the semiconductor memory MEM has a fuse circuit 30C. The other configuration is the same as that of the first embodiment. That is, the semiconductor memory forms sdram. The mode temporary storage 12C is configured by deleting the I5 access temporary storage IsACSR from the mode register 12 of the first embodiment. The access valid signal is output from the fuse circuit 30C. The fuse circuit 3〇c has execution memory. The fuse of the effective information ainf is obtained. That is, the fuse circuit 30C has the function of setting the access information unit for accessing the effective information ainf. The fourth embodiment can also be obtained in the same manner as the second embodiment and the second embodiment 20 described above. Further, when the fuse circuit 30C performs access to the valid information A chat, the FREQ can also be accessed by the forced access request to access the sub-unit array SARY which is not allowed to access. FIG. 10 shows the fifth embodiment of the present invention. The semiconductor memory is the same as the first embodiment and the requirements described in the fourth embodiment, and the same reference numerals are attached to the same reference numeral 21 1300573, and the detailed description thereof will be omitted. The semiconductor recording k and the body MEM of this embodiment have The mode register 12C of the fourth embodiment mode (5) replaces the mode temporary memory II12 of the first embodiment. Further, the semiconductor memory mem has a wiring connection circuit gamma. The other structure is the same as the jth embodiment. 5. The semiconductor memory is formed into a SDRAM. The wiring connection circuit 32D is formed of a conductive pattern CD formed on the memory MEMEM substrate in a pattern shape corresponding to the mask used in the memory process. The wiring connection circuit 32D is based on the voltage value of the connection end of the conductive pattern, and the memory 10 displays the active information AINF of the memory array of the auxiliary unit array SRAYi. In this example, the conductive pattern CD is connected to the power line VDD or the setting line. VSS. That is, the configuration connection circuit 32D has a function of setting an access information unit for accessing the effective information AINF. In the fifth embodiment, the same effects as those of the first and second embodiments described above can be obtained. Furthermore, depending on the reticle used, the access is performed with a 15-way information ,, and the FREQ can be accessed by a forced access to access the sub-cell array SARY that is not allowed to access. Fig. 11 is a view showing a semiconductor memory device according to a sixth embodiment of the present invention. The same elements as those described in the first embodiment are denoted by the same reference numerals, and the detailed description thereof will be omitted. The semiconductor memory MEM of this embodiment has 4 20 memories BK1-4 each having a memory core 28. Further, the corresponding memory bank BK1-4 is formed with four address control units 丨4, four address counters 22, four access detecting units 24, and four array control units 26. The mode register 12E has a temporary register BUSTR and an access register ACSR corresponding to four memories BK1-4, respectively. The address input unit 18E has a function of receiving the memory address BA0-1 for identifying the memory bank BK1-4 in addition to the function of the address input unit 18 of the first real form. The memory address BA0-1 is supplied to the array control unit 26, and each array control unit 26 is activated in accordance with the memory address ΒΑ0-1 to access the corresponding memory bank BK1-4. 5 Other structures except the corresponding memory bank BK1-4 generate burst signal BUST1-4, access valid signal AINF1-4, address counter 22 address RAO-11, CA0-6, SA0-1, detection signal The rest of the DET1-4 is the same as that of the first embodiment. The burst signal BUST1-4, the access valid signal AINF1-4, and the number at the end of the detection signal DET1-4 correspond to the number at the end of the memory bank BK1-410. That is, the semiconductor memory forms an SDRAM having four memories BK1-4. In this embodiment, the operation described in the first embodiment is executed for each of the memory banks BK1-4. The access valid information AINF 1-4 is set for each memory BK1-4 or uniformly for all 15 BK1-4 depending on the register setting command supplied from the command input unit 10E. Therefore, the command input unit 1A receives, in addition to the function of the command input unit 10 of the second embodiment, receives information including setting the access valid information AINF1_4 for each bank BK1-4 or uniformly setting all memory banks bki_4. Register setting command (access valid information setting command). Thereby, the access valid information AINF1-4 can be set according to the specification of the memory controller (memory 20 system) of the access memory MEM. Each array control unit 26 responds to the forced access request RFEQ1·4 provided for each memory bank BK1-4, and sets the access valid information A set to the unregistered access register ACSR (access information unit). The sub-cell array SARY of _4 is forcibly activated. 23 1300573 or more, in the sixth embodiment, the same effects as those of the above-described second and second embodiments can be obtained. Further, in the memory MEM having the complex memory bank BK1-4, the sub-unit array SARY of each of the memory banks BK1-4 can be accessed by minimizing the power consumption without lowering the access efficiency. Further, in the above embodiment, an example in which the memory system is formed as a SIP has been described. The invention is not limited to this embodiment. For example, the memory system may be formed as a system LSI (Systenl On Chip) laminated on a germanium substrate, and a memory mem, a flash memory FLASH, and a memory controller may be mounted on the printed substrate. MCNT! _2 and the formation of a memory system is also available. In the above embodiment, an example in which the present invention is applied to an SRAM has been described. The invention is not limited thereto. For example, the present invention is also applicable to DRAM, virtual SRAM, SRAM or flash memory. The virtual SRAM is a memory having a DRAM and having the same input/output interface as the SRAM to automatically perform an internal memory memory update operation. The semiconductor memory to which the present invention is applied may be a clock asynchronous type or a clock synchronous type. The above-described embodiment can also be applied to the semiconductor 20 memory MEM having the sub-cell array SARY of n, 16 or 32, etc., n-th power (n: 3 or more integers). At this time, the number of bits for identifying the array selection address SA of the sub-cell array SARY requires n. Further, the second to fifth embodiments may be applied to a semiconductor memory MEM having a plurality of memory banks. The present invention has been described in detail above, and the above-described embodiments and their modifications are merely examples of the invention, and the invention is not limited thereto. It will be appreciated that modifications can be made without departing from the scope of the invention. The present invention is applicable to a semiconductor memory in which the address space size can be changed. [Brief Description of the Drawings] 5 Fig. 1 is a block diagram showing a semiconductor memory according to a first embodiment of the present invention. Fig. 2 is a block diagram showing the details of the cell array shown in Fig. 1. Fig. 3 is an explanatory diagram showing the allocation of the bit 10 address of the setting contents of the access register shown in Fig. 1. Fig. 4 is a block diagram showing a memory system in which the memory shown in Fig. 1 is mounted. Fig. 5 is a timing chart showing the access operation when the valid information setting logic 1 is accessed in the memory shown in Fig. 1. Fig. 6 is a block diagram showing a semiconductor memory device according to a second embodiment of the present invention. Fig. 7 is a block diagram showing a memory system in which the memory shown in Fig. 6 is mounted. Fig. 8 is a block diagram showing a semiconductor memory device according to a third embodiment of the present invention. Fig. 9 is a block diagram showing a semiconductor memory device according to a fourth embodiment of the present invention. Fig. 10 is a block diagram showing a semiconductor memory device according to a fifth embodiment of the present invention. 25 1300573 Fig. 11 is a block diagram showing a semiconductor memory device according to a sixth embodiment of the present invention. [Main component symbol description]

10...Command input unit 10B...Command input circuit 12: Mode register 12C... Mode register 14... Clock input unit 16... Address input unit 18... Address input unit 20·.·Information Input/output unit 22···Address counter 24: Access detection unit 26. Array control unit 26B... Array control unit 28. Memory core 30C...Fuse circuit 32D...Wiring Connection circuit MEM···Semiconductor memory CMD···Command terminal BUSTR...Cluster register ACSR...Access register SARY(0-3)···Sub-cell array AD...Address terminal RA...address terminal CA...address terminal WL...word line BL...bit line/BL...bit line DB...data bus DT...data terminal ARY... Memory cell array RDEC...column decoder SA...sense amplifier CSW...column switch CDEC...column decoder RA...sense amplifier WA...write amplifier MC....dynamic memory unit MCNT1...memory controller FLASH...flash memory MCNT2...memory controller SBUS...system bus bar DET...detection terminal FREQ...forced access request terminal CD... Conductive pattern VDD... Power line VSS... Configuration line BK1-4. · .3⁄4 Storehouse

26

Claims (1)

L3〇〇573 X. Patent application scope: L-type semiconductor memory, including: bit = cell array, with memory unit, and assigned different access information parts, used to set the number of display arrays Take the effective information; _ activation description unit requires the array, in response to the access from the outside of the semiconductor memory ... 1 mosquito in the aforementioned access information department of the above-mentioned access effective 10 15 strong: In response to the external memory request from the semiconductor memory, the cell array that is not validly set before the access information unit is forced to activate. 2. The semiconductor memory of claim i, further comprising: the access detecting unit is configured to perform a pre-detection of the cell array corresponding to the access effective information when the plurality of sub-cell arrays are continuously executed. After the fetching, the accessor of the above-mentioned access control unit is activated to activate the access of the cell array that does not correspond to the access valid information. And perform an access action. 3. The semiconductor memory of claim 2, further comprising: the address count n ' is used to continuously access the memory unit of the memory unit, and sequentially generates a connection (4) accessing the address from the external access address provided outside the semiconductor memory, and when the access detecting unit is in the burst mode, performing the check according to the external 27 1300573 access and the internal access address Measuring action. 4. If the semiconductor memory of the second application of the patent scope is included, the detection terminal 'will display the detection in response to the aforementioned access check: section 3, so as to execute the cell array that does not correspond to the access effective information. The detection signal of the action is output to the outside of the semiconductor memory. 5. The material memory of the application scope of the patent item includes: a command input unit that receives an access command for accessing the memory unit and receives the mandatory access request as a commander, and the foregoing The array control unit forcibly activates the cell array that does not correspond to the access valid information in response to the mandatory access request received by the command rounding unit. 6. The semiconductor memory of claim 3, further comprising a mandatory access request terminal for receiving the mandatory access request, and wherein the array control unit responds to the mandatory access request received by the mandatory access request terminal. And the cell array that does not correspond to the aforementioned access valid information is forcibly activated. 7. The semiconductor memory of claim 1, further comprising: a command input unit that receives an access command for accessing the memory unit and receives the access valid information as a register setting commander. And the access information unit is set according to the temporary register setting command. 8. The semiconductor memory of claim 7, wherein the access poor portion is set by at least one of an address and a data provided by an external terminal in response to the register setting command. 9. The semiconductor memory of claim 1 of the patent scope, wherein the aforementioned access to the "TUP" is a fuse circuit for performing and accessing effective information. The semiconductor memory of claim 1 of the patent application, wherein the access port is a conductive pattern formed on a substrate of a semiconductor memory corresponding to a pattern of a photomask used in a semiconductor process. The gate 5 is closed, and the switch is connected to the electrical memory of the connection end of the conductive pattern to display the number of accesses of the array of cells simultaneously activated. For example, the semiconductor memory of claim 1 of the patent scope includes: 10 plural number of cells, each having a plurality of the foregoing arrays of cells, and the independent interoperators, Relative to the foregoing access valid information of each of the memory cell arrays, and the array control unit sets 'and the respective memory banks' and provides responses to the foregoing memory banks: 15 the mandatory access request is The cell array corresponding to the access effective information set in the access information unit is forcibly activated. , ... 12. The semiconductor memory of the U of the patent application scope, including: 叩·? The input unit receives the access command to access the memory unit and receives the access valid information as a register setting command, and the buffer setting command includes displaying the foregoing for each memory bank. Access valid information or uniformly set the aforementioned information for accessing valid information for all of the aforementioned memory banks. 13·—a memory system having a semiconductor memory and a controller for accessing the semiconductor memory, the semiconductor memory comprising: 29 1300573 a complex cell array, having the address of the address; Hidden unit, and assigned differently The access information department is used to set the access valid information of the number of display arrays; Access _ part, listen to the 彳 彳 彳 舰 料 = = = = = = 贱 贱 贱 贱 翁 翁 翁 翁 翁 翁 翁 翁 翁 翁 翁 翁 翁 翁 翁 子 子 子 10 10 10 10 10 10 10 15 15 2, the array control unit 'responds to the access request from the outside of the semiconductor memory' and activates the cell array corresponding to the access: the aforementioned access effective information of the Wei part, and at the same time, the response comes from the semiconductor memory ^ The mandatory access request is to set the unemployed unit to the above-mentioned access information to access the valid information unit __activator; and, ... the sub-system will display the response to the detection of the access detection unit, and the execution does not correspond to the foregoing The detection of the access operation of the effective unit (4) (4) is performed to the outside of the semiconductor memory. The controller includes: a control unit that responds to the detection signal and determines whether to execute or stop the semiconductor memory that is not corresponding. The access actor of the cell array that accesses the effective information. 30