1300255 九、發明說明： % 【發明所屬之技術領域】 本發明關於半導體製程中用於阻擋銅擴散之障j 料及其製法，特別地，該障礙層材料同時具有阻擋: 能力強、電阻係數低、與介電質及銅之附著性良好 晶粒傾向（1 1 1 )方向及高溫穩定性佳等性質。 【先前技術】 自從IBM於1 99 7年發表了銅導線技術之後， • 便成爲全球高階積體電路多層導線技術的主流。然 對矽晶材料以及大多數之介電質材料而言，都是影 的污染物，例如矽晶片一旦受到銅原子之滲入，將 載子生命週期縮短及元件漏電流增加，再者，若銅 入介電質，將使崩潰電場降低及漏電流增加，因此 用適當的擴散障礙層以包覆銅導線。 關於包覆銅導線之障礙層，一般必須符合數項 求’包括··（ 1 )阻擋銅擴散能力強；（2 )電阻係數低 ® 介電質及銅之附著性良好；（4)使銅晶粒傾向（n n方 (5 )局溫穩定性佳。 習知銅導線上方的介電質障礙層以S i 3 N 4或是 合物最爲常見，至於下方以及側面的金屬性障礙層 Ta/TaN堆疊形成障礙層爲主流；關於採取Ta/TaN 理由爲：TaN具有極佳的熱穩定性、不易結晶及良 擋銅擴散能力，卻存在一些缺點，包括··與銅之附著 無傾向於使位其上方的銅形成（1 1 1 )晶向及電阻係 礙層材 銅擴散 、使銅 銅製程 而，銅 響性質 使少數 原子進 必須使 基本要 ;(3)與 向；及 SiC化 ，則以 堆疊之 好之阻 :力差， 數也偏 1300255 高等，因此利用Ta，其和TaN相反性質之特性，可藉以彼 此截長補短。 然而隨著奈米製程的進一步發展，導線線寬更趨微小 化，因而障礙層的厚度亦必須相對降低，上述Ta/TaN堆疊 形成障礙層之厚度遂難符要求。因此，新近之發展出更多 具有更低電阻係數之障礙層材料便成爲硏究的重點，例如 S. C· Sun et al·發表之 Ti、Ta及 W等之碳化物系列 ( Refractory Metal Carbide-Based Diffusion Barrier for i Copper Metallization”，Proc. of IITC，p.397，2 00 1 ) ，J.1300255 IX. Description of the invention: % TECHNICAL FIELD The present invention relates to a barrier material for blocking copper diffusion in a semiconductor process and a method for fabricating the same, and in particular, the barrier layer material has a barrier at the same time: high capability, low resistivity, Good adhesion to dielectric and copper, grain tendency (1 1 1 ) direction and high temperature stability. [Prior Art] Since IBM published copper wire technology in 1997, it has become the mainstream of high-order integrated circuit multilayer wire technology. However, for the twinned materials and most of the dielectric materials, they are shadow contaminants. For example, once the germanium wafer is infiltrated by copper atoms, the carrier life cycle is shortened and the component leakage current is increased. Entry into the dielectric will reduce the collapse electric field and increase the leakage current, so the appropriate diffusion barrier layer is used to coat the copper conductor. Regarding the barrier layer covering the copper wire, it is generally necessary to meet several requirements for 'including · (1) blocking copper diffusion ability; (2) low resistivity ® dielectric and copper adhesion; (4) copper Grain tendency (nn square (5) is stable in temperature. The dielectric barrier layer above the conventional copper wire is most common with S i 3 N 4 or the compound, as for the metal barrier layer below and side. /TaN stacking barrier layer is the mainstream; the reason for adopting Ta/TaN is: TaN has excellent thermal stability, is not easy to crystallize, and has good copper diffusion ability, but has some shortcomings, including no adhesion to copper. The copper is formed above (1 1 1 ) crystal orientation and the resistance hinders the diffusion of copper from the layer, and the copper and copper processes are performed. The copper ringing property makes a few atoms necessary to make the basics; (3) and the direction; and SiC , the resistance of the stack is good: the force difference, the number is also higher than 1300255, so the use of Ta, the characteristics of the opposite nature of TaN, can be used to complement each other. However, with the further development of the nano-process, the wire The width is more miniaturized, so the thickness of the barrier layer is also The thickness of the barrier layer formed by the above Ta/TaN stack is relatively low. Therefore, the recent development of more barrier layer materials with lower resistivity has become the focus of research, such as S. C. Sun et. Al. Refractory Metal Carbide-Based Diffusion Barrier for i Copper Metallization, Proc. of IITC, p. 397, 2 00 1 ), J.
Schuhmacher et al.發表之 Ti、Ta及 W等之氮化物系列 ( TiN，TaN，and WxN as diffusion barrier for Cu on Si02” ，in Proc. A d v. Metal Conf.，ρ·759，2002)，以及其 他系歹IJ 之 TaSiN、TiSiN、 、MoN、WCN、ZrTi、ZrTiN、A series of nitrides of Ti, Ta and W, published by Schuhmacher et al. (TiN, TaN, and WxN as diffusion barrier for Cu on Si02), in Proc. A d v. Metal Conf., ρ·759, 2002), And other systems IJ of TaSiN, TiSiN, MoN, WCN, ZrTi, ZrTiN,
TaNi等等，然而很遺憾地，該等已知或硏發中之材料仍未 發現其中任何一種可以同時兼顧上述指稱之完整的基本要 求。 > 【發明內容】 本發明之主要目的在於提供一種可同時符合前述銅擴 散障礙層之材料，特別是適用於奈米製程下之導線線幅要 求。 本發明之銅擴散障礙層之材料，除了阻擋導線之銅原 子擴散外，更包括半導體元件之閘極裝置’或薄膜電晶體 (TFT)金屬電極等運用。 如上述之本發明銅擴散障礙層材料，係至少一 TaPt薄 1300255 ， 膜’其特徵在於該材料係由Ta與Pt所組成，可於高溫下， 例如5 0 0 °c以上仍維持非結晶之特性而可以阻擋銅原子擴 散，並具有低的電阻係數。 其中該材料中Pt之摻雜量約在35原子數（at.) %以 下，較佳爲15原子數（at·) %。 其中該TaPt薄膜之厚度可低於5nm，其與銅導線厚度 之比値較佳在1:1〇〜1:20之間，例如，在一簡單金屬氧化 物半導體（MOS)電容裝置之閘極中，TaPt(約5至20奈 I 米厚）/Cu(約200奈米厚）/TaPt(約5至20奈米厚）。 其中該T a P t薄膜，經過8 0 0 °C / 3 0 m i η退火/仍然維持 非晶狀態；再者，該TaPt薄膜之阻擋銅擴散的能力達700 °C / 3 0 m i η ;如經過6 5 0 °C / 3 0 m i η之退火，該T a P t薄膜仍可 承受測試條件200 °C、60min、2MV/cm之偏壓溫度測試。 本發明之另一目的在於提供一種如上述之銅擴散障礙 層材料之製法，包括TaPt合金材料之選取步驟，其中Ta 之含量不低於65原子數（at.)% ;及進行該障礙層之沉積步 I 驟，使該合金材料於一蒸鍍系統中，形成於Cu導電層與預 定之隔離物之間。 然而TaPt薄膜之形成方法並不限定於上述或實施例中 所使用的方法，尙包括雙電子槍蒸鍍、濺鍍或Ta/Pt/Ta/Pt 之多層堆疊等，均可適用。 如上述利用雙電子槍蒸鍍以製作本發明之銅擴散障礙 層材料，包括在一具有Ta爲第一標靶與具有Pt爲第二標 靶之雙電子鎗蒸鍍機中，以高的第一功率與低的第二功 1300255 . 率，分別控制該第一標靶與該第二標靶之沉積速率，使其 形成於Cu導電層與預定之隔離物之間。 如上述利用濺鍍，包括TaPt合金材料之選取步驟，其 中Ta之含量不低於65原子數（at.)% ;及進行該障礙層之 沉積步驟，使該合金材料於一濺鍍系統中，形成於Cu導電 層與預定之隔離物之間。 如上述利用共濺鍍以製作本發明之銅擴散障礙層材 料，包括在一具有Ta爲第一標靶與具有Pt爲第二標靶之 ® 雙濺鍍機中，以高的第一功率與低的第二功率，分別控制 該第一標靶與該第二標靶之沉積速率，使其形成於Cu導電 層與預定之隔離物之間。 如上述利用Ta/Pt/Ta/Pt之多層堆疊以製作本發明之銅 擴散障礙層材料，包括Ta與Pt堆疊結構之沉積步驟，其 中Ta在該堆疊層中之含量不低於65原子數（at·)% ;及進 行該障礙層之沉積步驟，使該堆疊結構於一雙濺鍍系統 中，形成於C u導電層與預定之隔離物之間。 ® 其中，上述之該預定之隔離物，可爲一矽基板，或半 導體裝置之閘極，或多重導線之電極等裝置之一。本發明 該銅擴散障礙層之應用亦不限於積體電路之銅導線以及平 面顯示器之銅閘極，任何使用銅的場合，若需要擴散障礙 層或提高與其它材質之附著力，均適用本發明。 【實施方式】 有關本發明之技術內容及實施手段槪以下列之具體實 施例描述之。 1300255 【實施例一】T a P t薄膜之製作與其特性 於一矽晶基板上，製作一簡單金屬氧化物半導體 (MOS)的電容裝置，其構造爲主要含TaPt(約5至20奈 米厚）/Cu(約200奈米厚）/TaPt(約5至20奈米厚）之閘電極 裝置，該閘電極氧化物爲厚約60 nm之熱氧化物。 接著將一 TaPt置於一共濺鍍系統中，其中該Ta及pt 標靶之濺鍍功率分別地設定爲直流3 0瓦及射頻3 0瓦。另 外一 Cu導電層係由濺鍍方式沉積。此合金閘極藉由發射製 程（lift-off process)加以圖案化。一 TaPt(50nm)/SiO2/Si 覆 蓋物之樣本亦被製備，以供TaPt薄膜之特性比較。 藉由魯氏後散射圖譜 （Rutherford back- scattering spectroscope，RBS)測得之Ta/Pt原子比例約85/15。如第 1圖所示在不同退火溫度之後的TaPt薄膜XRD頻譜圖， 其中較寬廣且弱的訊號代表該薄膜即使經過8 0 0 °C退火處 理3 0分鐘後仍會殘留的非經晶部份。該根據先前技術所示 之相圖【T. B. Massalski，Binary Alloy Phase Diagrams 2nd ed.，American Society for Metals，1990，p.3133·】該主要之 相假定係一 σ相。第2圖顯示50 nm後之TaPt薄膜經過 8 0 0 °C退火之後的TEM顯微剖面圖’僅可發現有少數之奈 米級結晶存在。該繞射圖案亦確認了處於近乎完全非晶狀 態。第3圖顯示在不同退火溫度之後的T a P t薄膜電阻率， 在此圖中亦同時並列Ta薄膜及TaN薄膜之電阻率。關於 加入了 P t之後並未增加電阻率且其在高達8 0 0 °C之下仍顯 示相當之穩定性。 1300255 • 經過進行一炭拉附著力試驗（Stud-pull adhesion test)，其顯示TaPt附著至Si02之強度超過50 MPa，而 且與單獨之Ta附著至Si02之強度不相上下。因爲Ta顯示 對多孔性碳摻雜氧化物（C D 0)具有好之附著力，所以相信 TaPt合金應當具有類似之效果，例如在k. L. Fang et al.， J· Appl. Phys.，vol.93，No.9，p.5546，2003·之論文中已展 現C u / T a P t堆疊之良好附著力。 【實施例二】銅擴散障礙層之性質測試 _ 第4圖顯示退火之前與以6 0 0 °C退火經3 0分鐘後之TaNi et al., however, unfortunately, none of these known or bursting materials have found any of the basic requirements for the above-mentioned allegations. SUMMARY OF THE INVENTION The main object of the present invention is to provide a material which can simultaneously conform to the aforementioned copper diffusion barrier layer, and in particular to a wire width requirement for a nanometer process. The material of the copper diffusion barrier layer of the present invention, in addition to blocking the diffusion of copper atoms of the wires, further includes the use of a gate device or a thin film transistor (TFT) metal electrode of a semiconductor device. The copper diffusion barrier layer material of the present invention is at least one TaPt thin 1300255, and the film is characterized in that the material is composed of Ta and Pt, and can maintain non-crystalline at a high temperature, for example, above 500 ° C. It can block the diffusion of copper atoms and has a low resistivity. The doping amount of Pt in the material is about 35 atomic % (at.) % or less, preferably 15 atomic number (at · %). Wherein the thickness of the TaPt film may be less than 5 nm, and the ratio of the thickness of the copper wire to the thickness of the copper wire is preferably between 1:1 〇 and 1:20, for example, the gate of a simple metal oxide semiconductor (MOS) capacitor device. Medium, TaPt (about 5 to 20 nm I m thick) / Cu (about 200 nm thick) / TaPt (about 5 to 20 nm thick). The T a P t film is annealed at 80 ° C / 30 μ η / still maintains an amorphous state; further, the TaPt film has a barrier copper diffusion ability of 700 ° C / 30 μ η ; After annealing at 65 ° C / 30 μm, the T a P t film can still withstand the test conditions of 200 ° C, 60 min, 2 MV / cm bias temperature test. Another object of the present invention is to provide a method for preparing a copper diffusion barrier layer material as described above, comprising the step of selecting a TaPt alloy material, wherein the content of Ta is not less than 65 atomic number (at.)%; and performing the barrier layer In the deposition step, the alloy material is formed in an evaporation system between the Cu conductive layer and the predetermined spacer. However, the method of forming the TaPt film is not limited to the method used in the above or the examples, and includes double electron gun evaporation, sputtering, or a multilayer stack of Ta/Pt/Ta/Pt, and the like. Using the dual electron gun evaporation as described above to fabricate the copper diffusion barrier layer material of the present invention, including a dual electron gun evaporation machine having Ta as the first target and Pt as the second target, with a high first power And a low second work 1300255. Rate, respectively controlling the deposition rate of the first target and the second target to be formed between the Cu conductive layer and the predetermined spacer. As described above, using sputtering, including a step of selecting a TaPt alloy material, wherein the content of Ta is not less than 65 atomic number (at.)%; and performing a deposition step of the barrier layer, the alloy material is in a sputtering system, Formed between the Cu conductive layer and the predetermined spacer. Co-sputtering as described above to fabricate the copper diffusion barrier layer material of the present invention, including in a double sputtering machine having Ta as the first target and Pt as the second target, with a high first power and The second low power controls the deposition rate of the first target and the second target to be formed between the Cu conductive layer and the predetermined spacer. As described above, a multilayer stack of Ta/Pt/Ta/Pt is used to fabricate the copper diffusion barrier layer material of the present invention, including a deposition step of a Ta and Pt stacked structure, wherein the content of Ta in the stacked layer is not less than 65 atomic number ( And a) the deposition step of the barrier layer is formed in a double sputtering system between the Cu conductive layer and the predetermined spacer. ® wherein the predetermined spacer is one of a substrate, or a gate of a semiconductor device, or an electrode of a plurality of wires. The application of the copper diffusion barrier layer of the present invention is not limited to the copper wire of the integrated circuit and the copper gate of the flat display. In the case of using copper, if the diffusion barrier layer is required or the adhesion to other materials is required, the present invention is applicable. . [Embodiment] The technical contents and the means for carrying out the invention are described in the following specific embodiments. 1300255 [Embodiment 1] The fabrication of a T a P t film and its characteristics on a twin crystal substrate, a simple metal oxide semiconductor (MOS) capacitor device is constructed, which is mainly composed of TaPt (about 5 to 20 nm thick). a gate electrode device of /Cu (about 200 nm thick) / TaPt (about 5 to 20 nm thick), the gate electrode oxide is a thermal oxide having a thickness of about 60 nm. Next, a TaPt is placed in a common sputtering system, wherein the sputtering power of the Ta and pt targets is set to 30 watts DC and 30 watts of RF, respectively. Another Cu conductive layer is deposited by sputtering. This alloy gate is patterned by a lift-off process. A sample of TaPt (50 nm) / SiO2 / Si coating was also prepared for comparison of the characteristics of the TaPt film. The ratio of Ta/Pt atoms was about 85/15 as measured by Rutherford back-scattering spectroscope (RBS). As shown in Figure 1, the XRD spectrogram of the TaPt film after different annealing temperatures, wherein the broad and weak signal represents the non-crystallized portion of the film that remains after 30 minutes of annealing at 80 °C. . The phase diagram according to the prior art [T. B. Massalski, Binary Alloy Phase Diagrams 2nd ed., American Society for Metals, 1990, p. 3133.] is mainly assumed to be a sigma phase. Figure 2 shows a TEM micrograph of a TaPt film after annealing at 80 nm after annealing at 80 °C. Only a few nanocrystals were found. The diffraction pattern also confirmed that it was in a nearly completely amorphous state. Figure 3 shows the resistivity of the T a P t film after different annealing temperatures. In this figure, the resistivity of the Ta film and the TaN film are also juxtaposed. There is no increase in resistivity after the addition of P t and it still shows considerable stability up to 800 °C. 1300255 • After performing a Stud-pull adhesion test, it shows that the strength of TaPt attached to SiO2 exceeds 50 MPa, and is comparable to the strength of Ta attached to SiO2 alone. Since Ta shows good adhesion to porous carbon doped oxide (CD 0), it is believed that TaPt alloys should have similar effects, for example, in k. L. Fang et al., J. Appl. Phys., vol Good adhesion of the C u / T a P t stack has been demonstrated in papers .93, No. 9, p. 5546, 2003. [Embodiment 2] Test of the properties of the copper diffusion barrier layer _ Figure 4 shows the annealing after annealing at 60 ° C for 30 minutes.
TaPt(20nm)/Cu(200nm)/TaPt(20nm)結構之 AES 深度圖形， 可以發現並未有銅擴散至TaPt障礙層內之現象。第5圖顯 不經過不同退火溫度後之TaPt(5nm)/Cu/TaPt(5nm)金屬氧 化物半導體，其電容之高頻下C_V特徵。當高於400°C以 上退火時有些損痕，乃因應力誘發介面狀態所致。經過 5 0 0、6 0 0、6 5 0及700°C之退火步驟，幾乎C-V曲線之重疊 顯示該銅原子可以被5 nm後之TaPt障礙層有效地阻擋 B 住。第6圖顯示其平帶電壓（Vfb)係爲退火溫度之函數。 其緊密之分佈與微小之差異確認該TaPt障礙層之效能。 第 7 圖顯示 65(TC退火樣本之崩潰電壓（breakdown voltage )係與在400°C退火樣本相同的，而700°C退火樣本 之崩潰電壓卻相對較低。在矽基板中之最小載子生命週期 可用停留時間量測法（r e t e n t i ο n t i m e m e a s u r e m e η t )加以 推估之，然而第8圖中顯示幾乎呈現相同之停留時間，亦 即到了 6 5 (TC以上，該矽基板仍未被銅所污染。 -10-The AES depth pattern of the TaPt (20 nm)/Cu (200 nm)/TaPt (20 nm) structure shows that there is no copper diffusion into the TaPt barrier layer. Figure 5 shows the TaPt (5 nm) / Cu / TaPt (5 nm) metal oxide semiconductor after different annealing temperatures, the C_V characteristics of the capacitor at high frequencies. Some of the damages when annealing above 400 °C are due to the stress-induced interface state. After an annealing step of 500, 600, 650, and 700 °C, the overlap of almost C-V curves shows that the copper atoms can be effectively blocked by the TaPt barrier layer after 5 nm. Figure 6 shows that the flat band voltage (Vfb) is a function of the annealing temperature. Its tight distribution and small differences confirm the effectiveness of the TaPt barrier layer. Figure 7 shows that 65 (the breakdown voltage of the TC annealed sample is the same as that of the annealed sample at 400 ° C, while the breakdown voltage of the annealed sample at 700 ° C is relatively low. The minimum carrier life in the tantalum substrate The period can be estimated by the residence time measurement method (retenti ο ntimemeasureme η t ), however, the figure 8 shows almost the same residence time, that is, up to 6 5 (TC or more, the germanium substrate is still not contaminated by copper. -10-
1300255 最後，在2 Μ V / c m及2 0 〇 °C條件下進 、測吾式(strong bias-temperature stress 1 〇及1 1圖分別地顯示6 0 〇 °C，6 5 0 °c及 C-V特徵。對600 °C及65CTC退火樣本 厚之TaPt，其進行30與60分鐘之BTS 帶電壓（Vfb)漂移，但對700°C退火樣坤 之TaPt，並無法通過該強偏壓溫度應力 第 1 2圖中比較經過 5 0 0。(：退 TaPt/Cu/TaPt 與 Ta/Cu/Ta 三明治構廷 TaPt 樣本中之該 Cu(lll)/Cu(200)強 ratios)是非常接近於Ta樣本中之該 度比値，此一結果暗示具有TaPt障礙 度相似於具有目前之 Ta/TaN堆疊障 度，亦即TaPt合金具有作爲銅擴散障 能。經7 0 0 °C 爐膛退火所具之優良的鍊 顯示在8 0 0 °C 退火之後的殘留非結晶牛( 樣本可以維持2 Μ V / c m 與2 0 0 °C，6 0 而仍保有低的電阻率、良好的附著力、ΐ 向（texture preference)等 ° 因此對下一世代銅導線製程而言， 爲最佳之金屬障礙材料。 雖然本發明已以較佳實施例揭露如 限定本發明，任何熟悉本技藝之人士， 精神與範圍內，當可做些許之更動與潤 行強偏壓溫度應力 ist5 BTS )。第 9、 7 00 °C 退火樣本之 而言，具有著5 nm 測試將不會導致平 :，具有著20n m厚 測試（BTS)。 火 30 分鐘後之 |之XRD頻譜。在 度比値（intensity Cu(lll)/Cu(200)強 層之該銅導線可靠 礙層之銅導線可靠 礙層所需之優異功 3障礙能力，其證據 勿；而該6 5 0 t退火 m i η .之B T S測試， 高的C u ( 1 1 1 )理路趨 T a P t合金將被建議 丨上，然其並非用以 在不脫離本發明之 I飾，因此本發明之 -11- 1300255 保護範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 第1圖 表示在不同退火溫度之後的TaPt薄膜XRD頻 譜圖。 第2圖 表示50 nm之TaPt薄膜，經過8 0 0 °C退火之後 的TEM顯微剖面圖。 第3圖 表示在不同退火溫度之後的TaPt薄膜、Ta薄 膜及TaN薄膜之電阻率。 第4圖 表示退火之前與以6 0 0 °C退火經3 0分鐘後之 TaPt(20nm)/Cu(200nm)/TaPt(20nm)結構之 AES 深度圖形。 第5圖 顯示經過不同退火溫度後之 TaPt (5 n m)/C：u/ TaPt(5nm)金屬氧化物半導體，其電容之高頻 下C-V特徵。 第6圖 顯示其平帶電壓（vfb)係爲退火溫度之函數。 第7圖 顯示6 5 0 °C退火樣本之崩潰電壓（breakdown voltage)係與在400 °C退火樣本相同。 第8圖 顯示幾乎呈現相同之停留時間，亦即到了 65 0°C 以上，該矽基板仍未被銅所污染。 第9圖 顯示60 0 °C退火樣本之C-V特徵。 第10圖 顯示6 5 0 °C退火樣本之C-V特徵。 第11圖 顯示700 °C退火樣本之c~v特徵。 第12圖 係比較經過5 00°C退火30分鐘後之TaPt/Cu/TaPt 與Ta/Cu/Ta三明治構造之XRD頻譜。1300255 Finally, under the conditions of 2 Μ V / cm and 20 ° ° C (strong bias-temperature stress 1 〇 and 1 1 map respectively show 60 ° ° C, 6 50 ° C and CV Characteristics: For TaPt with 600 °C and 65CTC annealed samples, the BTS band voltage (Vfb) drifts for 30 and 60 minutes, but the 700 °C annealed the TaPt, which cannot pass the strong bias temperature stress. 1 2 is compared with 5000. (: The TaPt/Cu/TaPt and the Ta/Cu/Ta sandwich TPt sample in the Cu(lll)/Cu(200) strong ratios) are very close to the Ta sample. In this case, the result implies that the TaPt barrier is similar to the current Ta/TaN stacking barrier, that is, the TaPt alloy has the function as a copper diffusion barrier. The furnace annealing at 700 °C is excellent. The chain shows residual amorphous cattle after annealing at 80 °C (the sample can maintain 2 Μ V / cm and 200 ° C, 60 while still retaining low resistivity, good adhesion, ΐ ( Texture preference) etc. Therefore, it is the best metal barrier material for the next generation of copper wire process. Although the invention has been better DETAILED DESCRIPTION OF THE INVENTION As defined by the present invention, anyone skilled in the art, within the spirit and scope, can make some changes and run a strong bias temperature stress ist5 BTS). In the case of annealed samples at 9,00 ° C , with a 5 nm test will not result in a flat:, with a 20n m thick test (BTS). The XRD spectrum of the fire after 30 minutes. In the intensity of 値 (intensity Cu (lll) / Cu (200) strong layer The copper wire is reliable to block the copper wire to reliably block the required excellent work 3 barrier capability, the evidence is not; and the 60 50 t annealed mi η BTS test, high C u (1 1 1) The T a P t alloy will be suggested, and it is not intended to be used without departing from the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Simple diagram of the diagram] Figure 1 shows the XRD spectrum of the TaPt film after different annealing temperatures. Figure 2 shows the TEM micrograph of the 50 nm TaPt film after annealing at 80 °C. Indicates the electrical properties of TaPt film, Ta film and TaN film after different annealing temperatures Rate. FIG. 4 represents AES depth before annealing pattern and to anneal 6 0 0 ° C over 30 minutes TaPt of (20nm) / Cu (200nm) / TaPt (20nm) structures. Figure 5 shows the C-V characteristics of the TaPt (5 n m)/C:u/ TaPt (5 nm) metal oxide semiconductor after different annealing temperatures. Figure 6 shows that the flat band voltage (vfb) is a function of the annealing temperature. Figure 7 shows that the breakdown voltage of the 65 °C annealed sample is the same as the annealing sample at 400 °C. Figure 8 shows that the same residence time is almost the same, that is, above 65 °C, the germanium substrate is still not contaminated by copper. Figure 9 shows the C-V characteristics of the annealed samples at 60 °C. Figure 10 shows the C-V characteristics of the annealed samples at 65 °C. Figure 11 shows the c~v characteristics of annealed samples at 700 °C. Figure 12 compares the XRD spectra of TaPt/Cu/TaPt and Ta/Cu/Ta sandwich structures after annealing at 500 °C for 30 minutes.