‘1299215 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種整合於半導體積體電路之變壓器 之製作方法，尤指一種與銅製程結合之變壓器之製作方法。 【先前技術】 隨著半導體技術的突飛猛進與無線通訊晶片需求的日 益殷切下，傳統的電感性元件，例如電感或變壓器等，皆 已被整合至單一晶片上，即，與積體電路結構整合，以符 合無線通訊晶片之小體積及低成本之要求。 請參閱第1圖至第5圖，第1圖至第5圖係為美國專利第 6,727，138號之變壓器製作方法之示意圖。一般變壓器與積體電路 結構之整合’係於半導體晶片後段製程(back-end_of_the-line， BEOL)中進行’例如於最上層之連接墊(contactpacj)製作完 成後，始進行變壓器之製作。如第1圖所示，一積體電路 結構100具有一基底102、一藉由銅製程形成於基底1〇2 内之最高金屬層（top interconnection metal layer) 104，而最 高金屬層之表面則覆蓋有一層保護層106及一金屬墊 (metal pad) 108。 清參閱弟2圖與第3圖。隨後於基底1〇2上形成一介電 層110’於介電層110上對應於金屬墊1〇8之位置利用微影 •1299215 暨蝕刻方法形成一孔洞（via)112，以暴露出金屬墊1〇8。並 於介電層110與孔洞112之底部與侧邊形成一銅擴散防止 層（copper-diffusion barrier layer) 114。 請參閱第4圖與第5圖。接著於銅擴散防止層Η*上贫 序形成一主繞組層（primary winding layer) 116、一絕緣声 (passivation layer)l 18、與一填滿孔洞112之副繞組層 (secondary winding layer) 120。最後，如第 5 圖所示，餘列 部分主繞組層120、絕緣層118、副繞組層116、與銅擴散 防止層114，以形成一具有線圈圖案且與金屬墊1〇8電連 接之變壓器。 由此可知，習知之變壓器係於半導體後段製程，尤其是 金屬墊製程完成之後，方可進行變壓器之製作。故此掣作 過程不但較為複雜，並使得積體電路結構製作成本大為增 加。另外，如第5圖所示，由於變壓器之主繞阻層與副^ 阻層係暴露於外界，因此該等金屬層易受微粒或外界水氣 影響其電性表現。而習知解決該問題之方法只能在完成^ 壓器之製作後，再於基底上形成一保護層，覆蓋主$阻層 與副繞阻層，並需再進行一微影暨蝕刻製程，以暴露出各 金屬墊，或直接將此載有變壓器之晶粒進行封裴掣程等。 【發明内容】 J299215 因此，本發明之主要目的係提供一種整合於半導體積體 電路之變壓器之製作方法，以解決習知半導體製程中變壓 器製程與半導體後段製程，需分別進行之問題，並可簡化 半導體製程以增進產業之利用性。 - 為達上述目的，本發明係於此提供一種整合於半導體積 體電路之變壓器之製作方法，首先提供一基底，並於該基 底上同時形成一最局金屬内連線層與一主繞組層（primary winding layer)。隨後於該基底上形成一絕緣層，且該絕緣 層係暴露出部分該最高金屬内連線層。接下來，於該絕緣 層上同時形成一副繞組層（secondary winding layer)與至少 一個金屬焊墊(bonding pads)，且該金屬焊墊係藉由該等開 口與該最高金内連線層電性連結。 根據本發明之申請專利範圍，本發明係另提供一整合於 • 半導體積體電路之變壓器，其包含有一基底、一設置於該 基底上之主繞阻層與一最高金屬内連線層、一設置於該主 繞阻層與該最高金屬内連線層上之絕緣層，且該絕緣層係 具有複數個開口設置於該最高金屬内連線層上、一設置於 該絕緣層上之副繞阻層與至少一個金屬焊墊，且該金屬焊 塾係藉由該等開口電性連接至該最高金屬内連線層。其 中’該主繞阻層與該副繞阻層係構成該變壓器。 8 ，1299215 • 根據本發明所提供之方法，係藉由同時製作變壓器之主 繞阻層與最高金屬内連線層，以及同時製作變壓器之副繞 阻層與金屬焊塾，提供一整合於半導體積體電路之變壓 • 器，並達到簡化半導體製程之目的。 【實施方式】 明參閱第6圖至第1〇圖，第6圖至第1〇圖係為本發明 φ 所提供整合於半導體積體電路之變壓器之製作方法之一較 佳實施例之示意圖。如第6圖所示，首先提供一基底2〇〇， 例如半導體晶圓或矽覆絕緣(S0I)等基底，且其包含有一主 動電路（圖未示）與至少一層金屬内連線層（圖未示）。接著再 對基底200實施一銅製程，以於基底2〇〇内同時形成一變 壓裔之主繞阻層210與一最高金屬内連線層212。 請參閱第7圖。接下來於基底200表面形成一厚度係為 Φ 1〇0〜500埃（angstr〇m)之絕緣層220，覆蓋住主繞阻層210 與最高金屬内連線層212，且絕緣層220具有複數個開口 222，分別暴露出部分最高金屬内連線層212。 請參閱第8圖與第9圖。隨後於基底200上形成一金屬 層230，且金屬層230係填滿各個開口 222。金屬層230之 材質係包含鈦、氧化鈦、鋁，或上述金屬之合金。隨後對 . 金屬層230實施一顯影暨蝕刻製程，使金屬層230於主繞 1299215 阻層210上方形成一副繞阻層232，並同時於最高金屬内 連線層212上方形成一金屬焊塾234。其中主繞阻層210 與副繞阻層232即構成本發明所提供之整合於半導體積體 • 電路之變壓器240。另外，由於主繞阻層21〇與最高金屬 •内連線層212係利用同一製程形成於基底2〇〇内；而副繞 阻層232與金屬焊墊234係利用同一製程形成形成於絕緣 層220上，因此如第9圖所示，主繞阻層21〇與最高金屬 ❿ 内連線層212係整合於約略同一水平面；而副繞阻層232 與金屬焊墊234係整合於約略同一水平面。 值得注意的是，金屬焊墊234係藉由開口 222内之金屬 層230與最高金屬連線層212電性連接；另外，為降低變 壓器240之電阻以提昇其品質因素，副繞阻層之寬度 係大於主繞阻層之寬度21〇。 籲 請參閱第10圖。最後於基底2〇〇上再形成-保護層 250，覆蓋住副繞阻層232與絕緣層22〇，並暴露出金屬焊 墊234以供對外電性連接，至此亦完成金屬焊墊234之製 作。且保護層25G之材料係包含氮化料可有效遮蔽水氣 之絕緣物質。換句話說，本發明所提供之整合於半導體積 體電路之變壓器之製作方法係於完成金屬焊墊234的同、 時’便能使副繞阻層232完全為保護層25〇所覆蓋而不致 *暴露於外界’因此更可避免副繞阻層232受到微粒或外界 1299215 水氣之影響。 請參閱第11圖。第11圖為本發明所提供之整合於半導 體積體電路之變壓器之上示圖，為方便說明，第11圖係僅 繪示本發明所提供之變壓器之主繞阻層與副繞阻層，而省 略其他部分。如第11圖所示，變壓器300之主繞阻層310 係藉由一銅製程於基底内形成最高金屬連線層（圖未示） 時，同時形成於基底内；而變壓器300之副繞阻層320係 於基底表面形成金屬焊墊（圖未示）時同時形成於基底表面 上。另外，變壓器300更包含一絕緣層（圖未示）設於主繞 阻層310與副繞阻層320之間。 值得注意的是，主繞阻層310與副繞阻層320係分別具 有一線圈圖案，由於副繞阻層320之感應電流係為電流流 過主繞阻層310之線圈時因磁感應所產生的，因此當主繞 阻層310之線圈於通電時所產生之磁力線亦通過副繞阻層 320之線圈圖案即可產生副繞阻層320之感應電流，故主 繞阻層310與副繞阻層320之線圈圖案係可為完全重合或 如本實施例所示之部分重疊等之佈局設計；較佳者，主繞 阻層310與副繞阻層320之線圈圖案係為共軸。另外，為 降低電阻提高品質因子，主繞阻層310之線寬係小於副繞 阻層320之線寬。第11圖係揭示本發明所提供之整合於半 導體積體電路之變壓器之主繞阻層與副繞組層之線圈圈數 11 •1299215 &其線_數與兩線圈圖 與其線圈圖案的一種重疊方式 案重疊方式係不限於此。 之倾供之整合於體電路 &壓„之&作方法’ #'错由同時s作髮器之主 2高金屬内連線層，以及同時製作變:： 金屬焊墊的方式’進而提供—整合於半導體層與 壓器的簡化餘。因此，根據本發明所提供之方法，^ 去多個曝錢影步驟，達到簡化製程與降低成本之目的 另外’本㈣所提供之整合於半導體額電路之變壓 於完成金屬焊墊的同時提供副繞阻層一保護層因此更可 有效避免魏阻層受科界水氣之影響，提高可靠度/ 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 ’Μ#’％與修飾’皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第5圖係為習知之變壓器之製作方法之示意圖。 第6圖至第10圖係為本發明所提供整合於半導體積體電路 之4壓器之製作方法之一較佳實施例之示意圖。 第11圖為本發明所提供之整合於半導體積體電路之變壓 器上示圖。 12„1299215 IX. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a transformer integrated in a semiconductor integrated circuit, and more particularly to a method of fabricating a transformer combined with a copper process. [Prior Art] With the rapid advancement of semiconductor technology and the increasing demand for wireless communication chips, conventional inductive components, such as inductors or transformers, have been integrated onto a single wafer, that is, integrated with the integrated circuit structure. In order to meet the requirements of small size and low cost of wireless communication chips. Please refer to FIG. 1 to FIG. 5 . FIG. 1 to FIG. 5 are schematic diagrams showing a method of manufacturing a transformer of US Pat. No. 6,727,138. In general, the integration of the transformer and the integrated circuit structure is performed in the back-end_of_the-line (BEOL) of the semiconductor wafer. For example, after the fabrication of the uppermost contact pad is completed, the transformer is fabricated. As shown in FIG. 1, an integrated circuit structure 100 has a substrate 102, a top interconnection metal layer 104 formed by a copper process in the substrate 1〇2, and the surface of the highest metal layer is covered. There is a protective layer 106 and a metal pad 108. See the 2nd and 3rd drawings. Then, a dielectric layer 110' is formed on the substrate 1'2, and a via 112 is formed on the dielectric layer 110 corresponding to the metal pad 1〇8 by using a lithography•1299215 etch method to expose the metal pad. 1〇8. A copper-diffusion barrier layer 114 is formed on the bottom and sides of the dielectric layer 110 and the holes 112. Please refer to Figures 4 and 5. A primary winding layer 116, a passivation layer 18, and a secondary winding layer 120 filled with the holes 112 are then formed on the copper diffusion preventing layer 贫*. Finally, as shown in FIG. 5, the remaining portion of the main winding layer 120, the insulating layer 118, the sub-winding layer 116, and the copper diffusion preventing layer 114 form a transformer having a coil pattern and electrically connected to the metal pad 1〇8. . It can be seen that the conventional transformer is manufactured in the semiconductor back-end process, especially after the metal pad process is completed. Therefore, the manufacturing process is not only complicated, but also greatly increases the manufacturing cost of the integrated circuit structure. In addition, as shown in Fig. 5, since the main winding layer and the secondary resist layer of the transformer are exposed to the outside, the metal layers are susceptible to the electrical performance of the particles or the external moisture. However, the conventional method for solving this problem can only form a protective layer on the substrate after the fabrication of the stamper, covering the main resist layer and the sub-winding layer, and further performing a lithography and etching process. In order to expose the metal pads, or directly seal the crystals carrying the transformers. SUMMARY OF THE INVENTION J299215 Therefore, the main object of the present invention is to provide a method for fabricating a transformer integrated in a semiconductor integrated circuit to solve the problems of the transformer process and the semiconductor back-end process in the conventional semiconductor process, which need to be separately performed and simplified. Semiconductor manufacturing to enhance the utilization of the industry. In order to achieve the above object, the present invention provides a method for fabricating a transformer integrated in a semiconductor integrated circuit. First, a substrate is provided, and a contiguous metal interconnect layer and a main winding layer are simultaneously formed on the substrate. (primary winding layer). An insulating layer is then formed over the substrate, and the insulating layer exposes a portion of the highest metal interconnect layer. Next, a secondary winding layer and at least one bonding pad are simultaneously formed on the insulating layer, and the metal pad is electrically connected to the highest gold interconnect by the openings Sexual links. According to the patent application scope of the present invention, the present invention further provides a transformer integrated in a semiconductor integrated circuit, comprising a substrate, a main winding layer disposed on the substrate and a highest metal interconnect layer, An insulating layer disposed on the main winding layer and the highest metal interconnect layer, and the insulating layer has a plurality of openings disposed on the highest metal interconnect layer and a secondary winding disposed on the insulating layer The resist layer and the at least one metal pad are electrically connected to the highest metal interconnect layer by the openings. The main winding layer and the sub-winding layer constitute the transformer. 8 , 1299215 • According to the method of the present invention, an integrated semiconductor is provided by simultaneously fabricating a main winding layer of a transformer and a highest metal interconnect layer, and simultaneously fabricating a secondary winding layer and a metal soldering of the transformer The transformer of the integrated circuit and the purpose of simplifying the semiconductor process. [Embodiment] Referring to Fig. 6 to Fig. 1 and Fig. 1 to Fig. 1 is a schematic view showing a preferred embodiment of a method for manufacturing a transformer integrated in a semiconductor integrated circuit provided by φ of the present invention. As shown in FIG. 6, first, a substrate, such as a semiconductor wafer or a germanium-insulated insulating (S0I) substrate, is provided, and includes an active circuit (not shown) and at least one metal interconnect layer (FIG. Not shown). Then, a copper process is performed on the substrate 200 to simultaneously form a main winding layer 210 and a highest metal interconnect layer 212 in the substrate 2 . Please refer to Figure 7. Next, an insulating layer 220 having a thickness of Φ 1 〇 0 〜500 Å is formed on the surface of the substrate 200 to cover the main winding layer 210 and the highest metal interconnect layer 212, and the insulating layer 220 has a plurality Openings 222 expose a portion of the highest metal interconnect layer 212, respectively. Please refer to Figure 8 and Figure 9. A metal layer 230 is then formed over the substrate 200, and the metal layer 230 fills each opening 222. The material of the metal layer 230 is titanium, titanium oxide, aluminum, or an alloy of the above metals. Then, a developing and etching process is performed on the metal layer 230, so that the metal layer 230 forms a pair of winding layers 232 over the main winding 1299215 resistive layer 210, and simultaneously forms a metal soldering pad 234 over the highest metal interconnect layer 212. . The main winding layer 210 and the sub-winding layer 232 constitute a transformer 240 integrated with the semiconductor integrated circuit provided by the present invention. In addition, since the main winding layer 21 and the highest metal/interconnect layer 212 are formed in the substrate 2 by the same process, the sub-winding layer 232 and the metal pad 234 are formed in the insulating layer by the same process. 220, so as shown in FIG. 9, the main winding layer 21〇 and the highest metal ❿ interconnect layer 212 are integrated on approximately the same horizontal plane; and the secondary winding layer 232 and the metal pad 234 are integrated on approximately the same horizontal plane. . It should be noted that the metal pad 234 is electrically connected to the highest metal wiring layer 212 by the metal layer 230 in the opening 222; in addition, to reduce the resistance of the transformer 240 to improve the quality factor, the width of the secondary winding layer It is greater than the width of the main winding layer by 21〇. Please refer to Figure 10. Finally, a protective layer 250 is formed on the substrate 2, covering the sub-winding layer 232 and the insulating layer 22, and exposing the metal pad 234 for external electrical connection, thereby completing the fabrication of the metal pad 234. . And the material of the protective layer 25G is an insulating material containing a nitride material to effectively shield moisture. In other words, the method for fabricating the transformer integrated in the semiconductor integrated circuit provided by the present invention is such that when the metal pad 234 is completed, the secondary winding layer 232 can be completely covered by the protective layer 25〇. *Exposed to the outside world' Therefore, it is more avoided that the secondary winding layer 232 is affected by particles or external 1299215 water vapor. Please refer to Figure 11. 11 is a diagram of a transformer integrated in a semiconductor integrated circuit provided by the present invention. For convenience of description, FIG. 11 only shows a main winding layer and a secondary winding layer of the transformer provided by the present invention. And omit other parts. As shown in FIG. 11, the main winding layer 310 of the transformer 300 is formed in the substrate by a copper process to form the highest metal wiring layer (not shown) in the substrate; and the secondary winding of the transformer 300 The layer 320 is simultaneously formed on the surface of the substrate while forming a metal pad (not shown) on the surface of the substrate. In addition, the transformer 300 further includes an insulating layer (not shown) disposed between the main winding layer 310 and the sub-winding layer 320. It should be noted that the main winding layer 310 and the sub-winding layer 320 respectively have a coil pattern, and the induced current of the secondary winding layer 320 is generated by magnetic induction when current flows through the coil of the main winding layer 310. Therefore, when the magnetic lines of force generated when the coil of the main winding layer 310 is energized also passes through the coil pattern of the secondary winding layer 320, the induced current of the secondary winding layer 320 is generated, so the main winding layer 310 and the secondary winding layer The coil pattern of 320 may be completely overlapped or partially overlapped as shown in this embodiment; preferably, the coil patterns of the main winding layer 310 and the secondary winding layer 320 are coaxial. In addition, in order to reduce the resistance and improve the quality factor, the line width of the main winding layer 310 is smaller than the line width of the sub-winding layer 320. Figure 11 is a diagram showing the number of turns of the main winding layer and the secondary winding layer of the transformer integrated in the semiconductor integrated circuit provided by the present invention. 11 • 1299215 & the line _ number and the overlap of the two coil patterns and their coil patterns The manner in which the method is overlapped is not limited to this. The integration of the circuit into the body circuit & press & _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Providing a simplification of the integration of the semiconductor layer and the press. Therefore, according to the method provided by the present invention, a plurality of exposure steps are performed to simplify the process and reduce the cost, and the integration provided by the semiconductor (the fourth) is integrated into the semiconductor. The voltage transformation of the frontal circuit provides a secondary winding layer and a protective layer while completing the metal pad, thereby effectively preventing the Wei resist layer from being affected by the water vapor of the scientific boundary, and improving the reliability. The above is only the preferred embodiment of the present invention. The embodiments of the present invention are intended to be within the scope of the present invention. [Fig. 1 to Fig. 5 is a schematic diagram of a conventional transformer manufacturing method. 6 to 10 are schematic views of a preferred embodiment of a method for fabricating a 4-integrator integrated with a semiconductor integrated circuit according to the present invention. FIG. 11 is an integrated semiconductor integrated body provided by the present invention. Circuit transformer Fig. 12
Cs) 1299215 【主要元件符號說明】 100 積體電路結構 102 基底 104 最高金屬層 106 保護層 108 金屬墊 110 介電層 112 孔洞 114 銅擴散防止層 116 主繞阻層 118 絕緣層 120 副繞阻層 200 基底 210 主繞阻層 212 最高金屬内連線層 220 絕緣層 222 開口 230 金屬層 232 副繞阻層 234 金屬焊墊 240 變壓器 250 保護層 300 變壓器 310 主繞阻層 320 副繞阻層 (§)Cs) 1299215 [Main component symbol description] 100 integrated circuit structure 102 substrate 104 highest metal layer 106 protective layer 108 metal pad 110 dielectric layer 112 hole 114 copper diffusion preventing layer 116 main winding layer 118 insulating layer 120 secondary winding layer 200 substrate 210 main winding layer 212 highest metal interconnect layer 220 insulating layer 222 opening 230 metal layer 232 secondary winding layer 234 metal pad 240 transformer 250 protective layer 300 transformer 310 main winding layer 320 secondary winding layer (§ )