1299244 19644twf.doc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種薄膜電晶體(thin fUm transist〇r， TFT)及其製造方法，且特別是有關於一種非晶矽薄膜電晶 體及其製造方法。 、 【先前技術】 近2來隨著數位時代的來臨，平面顯示器市場蓬勃發 展下，帶動主動式的平面液晶顯示器的需求急劇的成長， 用電視、攜帶式資訊產品、筆記型電腦、數位相機等 终夕的應用出現帶給人們更便利的生活。因此 的製作技術與薄膜電晶體的相關研究備受矚目。^ 、 為了因應大尺寸高解析度的液晶電視的要求， =非::夕】，曰曰體㈣i TFT)較符合大面積化生產 突破:舉:二二有部分缺陷有待 體Γ較高的二動;== 升會影響元件開關的操作特作下’光漏電流的上 然而，在上述問題之現有解決之道 問題，卻無法兼顧其他元件特 1解決個別 ，。因此，如何能約同時提升驅動缺 是目前產業界所急需克服的_。叫料漏電流， 【發明内容】 本發明的目的就是在提供一種薄膜電晶體及其製造 I2992U 19644twf.doc/e 造出可以同時提升驅動電流並抑制光漏電流的 +本發明提出-種薄膜電晶體，包括基板、閘極、閉介 ^、通道複合層、歐姆接觸層、源極區與汲極區，盆中 非晶石夕薄膜與非晶矽鍺薄膜所構成。閘介 ^配置於基板上並覆蓋配置於基板上的閘極。通道 層配置於部分間介電層上。歐姆接觸層配置於通道複入層 i相出閘極上之部分通道複合層。源極區與汲極區 相刀舰配置於較電層上，並覆蓋_接觸層。 =本發明之—實闕所狀薄職晶體/通道複 ===於閘介電層上之非晶石夕薄膜以及位於非晶石夕薄 膜上之非晶石夕鍺薄膜。 入展！ΐ本發明之—實施例所述之_電晶體中，通道複 括位於閘介電層上之非晶石夕鍺薄膜以及位於非晶石夕 鍺溥膜上之非晶石夕薄膜。 發明之—實施例所述之薄膜電晶體中，非㈣ 材質實施例所述之_電晶體中，閘極的 t例如疋摻雜多㈣、钽、鉻、鉬、鈦、㈣其他導體 依照本發明之—實施例所述之薄膜電晶體中 層的材質例如是氧切、氣化碎或氮氧 : 是在3000埃〜4000埃之間。 /、厗度例如 12992^ 19644twf.doc/e 依照本發明之-實施例所述之薄膜電晶體中，歐 觸層的材質例如是摻雜非晶石夕或摻雜非晶石 如是在400埃〜500埃之間。 #八尽度例 依照本發明之-實施例所述之薄膜電晶體中， 與>及極區的材質例如是摻雜多晶石夕、知、 ’、品 或其他導體材料。 ，-路、錮、鈦、銘 依照本發明之一實施例所述之薄膜電晶 如是透明玻璃基板或透明塑膠基板。 土板例 本發明另提出一種薄膜電晶體的製造方法， 供一基板。然後，於基板上形成閘極。接著， 成覆蓋閘極的閘介電層。之後，於閘介 =’ 石夕薄膜以及非晶石夕錯薄膜所構成的通道複:非； 形ΐ歐姆接觸層。而後，圖案化_接_ 覆蓋歐2= ΐ ’於閘介電層上形成導體材料層，並 人姆接觸層。然後，定義導體材料 區。隨後，贿^ 法中，實施例所述之薄膜電晶體的製造方 氣相沈層的步驟例如是進行電漿增強型化學 忐非日積私或低壓化學氣相沈積製程，於閘介帝Μ μ# 著再於非晶賴膜上形成非晶二 、、本發明之另一實施例所述之薄 成非晶心=化學氣相沈積製程’於問介電層上形 膜。者_ ’接著再於非晶賴_上形成非晶石夕薄 7 1299214 95014 19644twf.doc/e 依照本發明之另一實施例所述之薄獏電晶體的掣、告 法中，形成閘極之步驟例如是先於基板上形成閘= 層。接著再進行微影蝕刻製程，以定義出閘極。 可科 依照本發明之另一實施例所述之薄膜電晶體的制、生 方法中，形成歐姆接觸層的步驟例如是以電漿增強型衣j 氣相沈積法或低壓化學氣相沈積法形成摻雜石夕^學 非晶矽鍺。 日日攻^乡雜 、依照本發明之另-實施例所述之_電晶體的制生 方法中，形成閘介電層的方法例如是電漿增強型化風 沈積法或低壓化學氣相沈積法。 予氣相 依照本發明之另―實施例所述之相電晶體的制& ^法中’形成閘介電層、通道複合層與歐姆接觸層是= 場方式進行。 品 依照本發明之另-實施綱述之薄膜電晶體的制i 方法中’形成閘介電層、通道複合層與歐姆接觸 = 臨場方式進行。 非 本發，之非晶石/鍺薄膜具有較低阻值的優點，故 引入做為薄膜電晶體的通道層，可以大幅 阳” 以提升驅動電流與林特性。另外，非轉= 漿增強型化學氣相沈積法或低壓化學氣相沈積;】 本身具有足夠的缺陷數目。因此當元件照光時$ ς 溥膜中的缺陷可以作為細錢絲發㈣ ^捉 心。：且，非晶石夕鍺薄膜的缺陷密度與非晶石夕鍺 鍺含篁有關，可藉由調整形成非晶石夕鍺薄膜時的鍺烧流量 12992¾ 〇H 19644twf.doc/e 控制缺陷密度。 μ為讓本發明之上述和其他目的、特徵和優點能更明顯 易廑下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖1Α至圖1D為依照本發明之一實施例所繪示之 膜電晶體的製造流程剖面圖。 e ^參照圖1A，提供4板100，基板100例如 板或透明塑膠基板。然後，於基板100上形 戶(二-广、方法例如是先於基板_上形成閘極材料 ί (未:t而閉極材料層的材質例如是摻雜多晶㈣、 心麵、鈦、銘或其他導體材料 例如是以濺鍍或基梦的古切々r金屬閘極材枓層 i 式形成。而捧雜多晶石夕例如是直 未摻雜多㈣，接著再進行離子A: 極：雜〜一，進行微影_製程，以定義出閘 之後，於基板100上形成覆蓋 刚。閘介電層刚的材質例如是氧化石^02的閘介電層 矽，其厚度例如是在3_埃〜_ 夕、亂化石夕或氮氧化 的方法例如是電聚增強型化學、拉f成閘介電層104 沈積法。以氮化彻，其;;==學氣相 爹數包括使用的功率例如是在2〇 % 予矹相沈積製程 行沈積之環境溫度例如是在100它至 W之間。進 υ c之間。且工作壓 1299¾^ 19644twf· doc/e 力例如是在300 mtorr (毫托)至400 mtorr之間。其所使用 的反應氣體例如是矽烷(SiH4)、氨(NH3)與氮氣(N2')，其中 石夕烧的流量例如是在10 sccm(立方公分/每分鐘)至 之間，氨氣的流量例如是在120sccm之間，而 氮氣的流量例如是400 sccm至600 sccm之間。所沈積的 薄膜厚度例如是在3〇〇〇埃至4〇〇〇埃之間。 貝、 接著，請參照圖1B，於閘介電層1〇4上形成非晶矽薄 膜觸。接著，再於非晶石夕薄膜106上形成非晶石夕^薄膜 108,且非晶矽薄膜1〇6以及非晶矽鍺薄膜1〇8構成通道複 合層110。通道複合層110的形成方法例如是進行電嘴辦 強型化，氣相沈積製程或低壓化學氣相沈積製程，在^ 真空的環境下連續沈積非晶石夕薄膜1〇6以及非晶石夕錯薄膜 應。以此種臨場(In_situ)方法形成兩膜層的方法可以降 低兩層之間的介面問題。其中，以形成換雜氣之非晶石夕薄 膜106為例時，電漿增強型化學氣相沈積製程參數包括使 是在1G w至2G w之間。進行沈積之環境溫 度例如疋在KKTC至放。(：之間。^作壓力例如是在· 4GG mto之間。其所使用的反應氣體例如是石夕 ^ 1例如是在50 sccm幻5〇 sccm之間。而所沈積 的厚度例如是在200埃〜1000埃之間。 膜料強型化學氣相沈積法形成非晶石夕鍺薄 Μ 108日守的參數例如是與形成非晶石夕薄们〇6時大致相 處在於其反絲體·是魏與舰(GeH4)，石夕 烷的_如是在！ _至2〇sccm之間，鍺烷的流量例 I2992M 19644twf.doc/e 如是在 1 seem 至 l〇 scrm 夕 ^ _埃至膽埃之Π #由間所積的厚度例如是在 ^至1·埃之間。其中，形成 程參數，可以使分子的平均自由徑鼓，的製 :固製程反應室中，因此非晶侧 以=二 非晶矽薄膜106上。 从吟勾成長於 例如步驟還可以 之形成條件皆與上述_，故於此不再_。 重要的是，非晶矽鍺薄膜108且有 的通道區’可以大幅道 電阻’以提升驅動電流與元件特 錯 法开彡赤^化予乳相沈積法或低壓化學氣相沈積 7成、杉具有足_缺陷數目、 2::=::中的缺陷可以作為光心= 108 t db B 筇3里有關，因此可藉由調整形成 非曰曰石夕鍺薄膜108時的鍺燒流量控制缺陷密度。 觸/Til參關1C’於通道複合層11G上形成歐姆接 θ 12。_接觸層112的材質例如是播雜非晶石夕或換 =曰曰石夕錯，其形成方法例如是電漿增強型化學氣相沈積1299244 19644twf.doc/e IX. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor (TFT) and a method for fabricating the same, and in particular to an amorphous germanium Thin film transistor and method of manufacturing the same. [Previous technology] With the advent of the digital era, the flat panel display market is booming, and the demand for active flat-panel liquid crystal displays has grown dramatically. TVs, portable information products, notebook computers, digital cameras, etc. The application of the end of the day has brought people a more convenient life. Therefore, the related research techniques and related research on thin film transistors have attracted attention. ^, In order to meet the requirements of large-size and high-resolution LCD TVs, =N:: 夕], 曰曰 (4) i TFT) is more in line with the large-area production breakthrough: Lift: 22 has some defects to be higher Movement; == liter will affect the operation of the component switch under the special 'light leakage current' However, the existing solution to the above problems, but can not take into account the other components to solve the individual. Therefore, how to improve the driver shortage at the same time is an urgent need for the industry to overcome. The invention aims to provide a thin film transistor and a manufacturing method thereof, I2992U 19644twf.doc/e, which can simultaneously increase the driving current and suppress the light leakage current. The crystal comprises a substrate, a gate, a closed dielectric layer, a channel composite layer, an ohmic contact layer, a source region and a drain region, and an amorphous quartz film and an amorphous germanium film in the basin. The gate is disposed on the substrate and covers the gate disposed on the substrate. The channel layer is disposed on a portion of the dielectric layer. The ohmic contact layer is disposed on a portion of the channel composite layer on the gate of the channel re-entry layer. The source region and the bungee region are arranged on the electric layer and cover the _ contact layer. = The thin film crystal/channel complex of the present invention is a === amorphous Aussie film on the gate dielectric layer and an amorphous stone film on the amorphous film. Entering the exhibition! In the transistor according to the embodiment of the present invention, the channel includes an amorphous austenite film on the gate dielectric layer and an amorphous austenite film on the amorphous stone. In the thin film transistor according to the embodiment, in the non-fourth material embodiment, in the transistor, the gate t is, for example, erbium-doped (tetra), germanium, chromium, molybdenum, titanium, or (iv) other conductors according to the present invention. The material of the layer in the thin film transistor according to the embodiment is, for example, oxygen cut, gasification or nitrogen oxide: between 3000 Å and 4000 Å. /, 厗度, for example, 12992^19644twf.doc/e In the thin film transistor according to the embodiment of the present invention, the material of the European contact layer is, for example, doped amorphous or doped amorphous stone, such as at 400 angstroms. Between ~500 angstroms. #八尽度例 In the thin film transistor according to the embodiment of the present invention, the material of the > and the polar region is, for example, doped polycrystalline stone, known, 'product, or other conductive material. The film electro-crystal according to an embodiment of the present invention is a transparent glass substrate or a transparent plastic substrate. Soil plate example The present invention further provides a method of manufacturing a film transistor for a substrate. Then, a gate is formed on the substrate. Next, a gate dielectric layer covering the gate is formed. Thereafter, the channel formed by the gate dielectric = 'Shi Xi film and the amorphous stone film is complex; non-shaped; ΐ ohmic contact layer. Then, the patterned _ _ _ covering ohm 2 = ’ ′ forms a layer of the conductor material on the gate dielectric layer, and contacts the layer. Then, define the area of the conductor material. Subsequently, in the bribe method, the step of fabricating the vapor phase layer of the thin film transistor described in the embodiment is, for example, performing a plasma enhanced chemical non-daily product or a low pressure chemical vapor deposition process, in the case of the dynasty μ# is formed on the amorphous film to form an amorphous film, and the thin amorphous metal according to another embodiment of the present invention=chemical vapor deposition process is formed on the dielectric layer. _ 'Subsequently forming an amorphous slab on the amorphous ray _ 7 1299214 95014 19644 twf. doc / e according to another embodiment of the present invention, the thin 貘 transistor, in the method of forming a gate The step is, for example, to form a gate = layer on the substrate. A lithography process is then performed to define the gate. In the method for fabricating and producing a thin film transistor according to another embodiment of the present invention, the step of forming an ohmic contact layer is formed, for example, by plasma enhanced coating vapor deposition or low pressure chemical vapor deposition. Doped stone Xi ^ learning amorphous enamel. In the method for producing a transistor according to another embodiment of the present invention, the method of forming the gate dielectric layer is, for example, plasma enhanced wind deposition or low pressure chemical vapor deposition. law. The gas phase is formed in accordance with another embodiment of the present invention, in which the gate dielectric layer, the channel composite layer and the ohmic contact layer are formed in the field mode. The method for forming a thin film transistor according to another embodiment of the present invention is to form a gate dielectric layer, a channel composite layer, and an ohmic contact = on-site manner. Non-essential, the amorphous stone/ruthenium film has the advantage of lower resistance, so it is introduced as a channel layer of the thin film transistor, which can greatly increase the driving current and the forest characteristics. In addition, the non-rotation = slurry enhanced type Chemical vapor deposition or low-pressure chemical vapor deposition;] itself has a sufficient number of defects. Therefore, when the component is illuminated, the defect in the film can be used as a fine wire (4) ^Catch the heart. The defect density of the ruthenium film is related to the yttrium-containing yttrium, and the defect density can be controlled by adjusting the smear flow rate 129923⁄4 〇H 19644 twf.doc/e when forming the amorphous 锗 锗 film. The above and other objects, features, and advantages will be more apparent from the following description of the preferred embodiments illustrated in the accompanying claims. A cross-sectional view showing the manufacturing process of the film transistor. e ^ Referring to Fig. 1A, a four-plate 100, a substrate 100 such as a plate or a transparent plastic substrate is provided. Then, the substrate is formed on the substrate 100 (two-wide method, for example, first Forming a gate on the substrate_ Material ί (not: t and the material of the material of the closed-pole material is, for example, doped polycrystalline (four), nucleus, titanium, indium or other conductor material such as a sputter or a base of the ancient cut 金属r metal gate 枓 layer i Formed by the formula, and the doped polycrystalline stone is, for example, straight undoped (four), and then ion A: pole: hetero~ one, lithography_process, to define the gate, form a cover on the substrate 100 The material of the gate dielectric layer is, for example, a gate dielectric layer of oxidized oxide 02, and the thickness thereof is, for example, 3 Å to _ 夕, or a method of oxidizing nitrogen, such as electropolymerization enhanced chemistry, pulling f is a gate dielectric layer 104 deposition method. To nitride, its; == learning gas phase number includes the power used, for example, at 2%% to the 矹 phase deposition process, the deposition temperature is, for example, at 100 Between W and C. The working pressure is 12993⁄4^19644twf·doc/e force is, for example, between 300 mtorr (mTorr) and 400 mtorr. The reaction gas used is, for example, decane (SiH4). Ammonia (NH3) and nitrogen (N2'), wherein the flow rate of Shixia is, for example, between 10 sccm (cubic centimeters per minute), ammonia gas The flow rate is, for example, between 120 sccm, and the flow rate of nitrogen is, for example, between 400 sccm and 600 sccm. The thickness of the deposited film is, for example, between 3 〇〇〇 and 4 〇〇〇. Next, please refer to 1B, an amorphous germanium film contact is formed on the gate dielectric layer 1? 4. Then, an amorphous thin film 108 is formed on the amorphous thin film 106, and the amorphous germanium film is 1 and 6 and amorphous. The ruthenium film 1 〇 8 constitutes the channel composite layer 110. The formation method of the channel composite layer 110 is, for example, performing a power supply process, a vapor deposition process or a low pressure chemical vapor deposition process, and continuously depositing a non-vacuum environment. The spar film 1〇6 and the amorphous stone film should be. The method of forming two layers by this in-situ method can reduce the interface problem between the two layers. Wherein, in the case of forming the amorphous oxide thin film 106, the plasma enhanced chemical vapor deposition process parameters are comprised between 1 GW and 2 Gw. The ambient temperature at which the deposition takes place is, for example, at KKTC. The pressure is, for example, between 4 GG mto. The reaction gas used is, for example, Shi Xi ^ 1 for example between 50 sccm and 5 〇 sccm, and the deposited thickness is, for example, 200. Between angstroms and 1000 angstroms. The strong chemical vapor deposition method of the film material forms an amorphous stone 锗 锗 Μ 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 It is Wei and the ship (GeH4), _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The thickness of the 由 由 例如 例如 例如 例如 例如 例如 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由The second amorphous germanium film 106 is formed on the surface of the amorphous germanium film 108, and the formation conditions are the same as those described above. Therefore, the amorphous germanium film 108 has a channel region The circuit resistance is used to increase the driving current and the component error method to open the emulsion phase to the emulsion phase deposition method or low pressure chemical vapor deposition 7 The cedar has the number of defects _ defects, and the defects in 2::=:: can be related to the optical center = 108 t db B 筇3, so the smoldering flow when the non-stone smear film 108 is formed can be adjusted. The defect density is controlled. The touch/Til reference 1C' forms an ohmic junction θ 12 on the channel composite layer 11G. The material of the contact layer 112 is, for example, azadix sinensis or yttrium = yttrium, which is formed, for example. Plasma enhanced chemical vapor deposition
強型化學⑻目沈積製程參數包括使用的功率例如是 至80 WH行沈積之環境溫度例如是在HXTC 1299^4 19644twf.doc/e 至350 C之間。且工作壓力例如是在300 mtorr至400 mt〇rr 之間。其所使用的反應氣體例如是矽烷、氫化磷(PH3)與氫 氡(H2)’其中石夕烧的流量例如是在5 SCCm至15 sccm之間， 氫化磷的流量例如是在10 ^(:❿至30 sccm之間，而氡氣 的流量例如是800 seem至i20〇 sccm之間。所沈積的^姆 接觸層112的厚度例如是在4〇〇埃〜5〇〇埃之間。The strong chemistry (8) deposition process parameters include the power used, for example, to an ambient temperature of 80 WH deposition, such as between HXTC 1299^4 19644 twf.doc/e to 350 C. And the working pressure is, for example, between 300 mtorr and 400 mt 〇rr. The reaction gas used is, for example, decane, phosphorous hydride (PH3) and hydroquinone (H2), wherein the flow rate of the sinter is, for example, between 5 SCCm and 15 sccm, and the flow rate of the phosphine is, for example, 10 ^(: ❿ is between 30 sccm, and the flow rate of helium is, for example, between 800 seem and i20 〇 sccm. The thickness of the deposited contact layer 112 is, for example, between 4 Å and 5 Å.
其中’形成閘介電層104、通道複合層11〇盥歐姆接 觸層112例如是以臨場方式進行，也就是三道沈積製程是 在同-反應室t，於猶真^的環境下連續進行。同樣的， ^用臨場巧形成之三闕，也會降低彼此之間的介面問 Ϊ另實％射’上述三道製程也可以是以非臨場方 二俊，清繼繽參照圖lc，園茶化歐姆接觸層ιΐ2與 = ’暴露出部分開介電層心以定義出薄膜 料層(5示;if蓋二104上形成導體 例如是掺雜多晶㈣、=層：:導體材料層的材 i多中:是卿礙==成體材: “是先 進行離子植入製程形成摻雜=未摻雜多晶石夕’接著-層’以形成互相分離的源=7二接著，定義導齡 法例如—刻製程===:: 12 19644twf.doc/e ll^b並不限定如_示，可以是兩者左右互換 除未被源極區114a與汲極區屬所覆 姆接 112,而裸露出開極102上之部分通道 姆= 例如是蝕刻法。 m 、本發明之薄膜電晶體利用通道複合層11G作為元件的 通道區，其結合非晶销薄m ι〇8的低阻值以及A自身含 =定量的缺陷數目等優點，可以提升薄膜電晶體的驅動 包肌以及抑制照光操作下之光漏電流。 ★以下將以圖1D對本發明之薄膜電晶體作說明，其中 薄膜電晶體結射部分構件的材質與形成方法已於上^實 施例中提及，故於此不再贅述。 、 請參照圖1D，薄膜電晶體包括基板1〇〇、閘極1〇2、 閘介電層104、通道複合層11〇、歐姆接觸層112、源極區 IHa與汲極區114b，其中通道複合層11〇例如是由配置於 閘介電層104上的非晶石夕薄膜1〇6與配置於非晶石夕薄膜 106上的非晶矽鍺薄膜1〇8所構成。閘介電層1〇4配置於 基板100上並覆蓋配·置於基板100上的閘極1〇2。通道複 合層110配置於部分閘介電層1〇4上。歐姆接觸層112配 置於通道複合層110上，並裸露出閘極1〇2上之部分通道 複合層110。源極區114a與汲極區114b互相分離地配置 於閘介電層104，並覆蓋歐姆接觸層112。 在另一實施例中，通道複合層11〇的結構還可以是與 上述實施例中相反，也就是通道複合層110還可以是由配 置於閘介電層104上的非晶矽鍺薄膜108以及配置於非晶 13 1299^4 19644twf.doc/e 石夕鍺薄，⑽，非晶石夕_1〇6所構成。 值传一提的是，非晶矽鍺薄膜具有低阻值，用於 f膜電晶體的通道區中’可以降低導通電流以提升驅動電 抓。另外’非晶石夕錯薄膜1〇8自身具有一定量的缺陷數目， 可以气由缺陷的特點抑制後薄膜電晶體的光漏電流。 絲上所述，本發明之特點在於： 、1’本發明使㈣晶;5續賴與非晶⑨賴組成通遂 複。層作為相電晶體的通道區，_非晶#鍺薄膜具有 低阻值的優點’大巾|降低源極區與汲極區之間的通道電 阻以提升薄膜電晶體的驅動電流與元件特性。 2,本發明利用㈣增強型化學氣相沈積法或低壓化 二乳相沈積法形成非轉錄薄膜，使非晶補薄膜本身具 ^足夠的缺陷數目。當_電晶體在照光操作下，上述之 缺陷可以作為光漏電流現象發生時的電荷捕捉中心，因此 可以抑制薄膜電晶體的光漏電流。Wherein the formation of the gate dielectric layer 104 and the channel composite layer 11 and the ohmic contact layer 112 are performed, for example, in a field-wise manner, that is, the three deposition processes are continuously performed in the same-reaction chamber t in an environment of a true environment. In the same way, the use of the three sides of the formation of the scene will also reduce the interface between each other. Ϊ % Ϊ % % % % % 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述The ohmic contact layer ιΐ2 and = ' expose a portion of the dielectric layer to define a thin film layer (5; if the conductor formed on the cover 2 104 is, for example, a doped poly (four), = layer:: conductor material layer) i: In the middle of the body: Yes Qing == adult material: "Is first to do the ion implantation process to form doping = undoped polycrystalline stone ' 'then-layer' to form a source of separation from each other = 7 then, define the guide The age method, for example, engraving process ===:: 12 19644twf.doc/e ll^b is not limited to _ shown, but may be interchanged between the two, except that the source region 114a and the bungee region are not covered by 112. And a part of the channel on the open electrode 102 is exposed, for example, an etching method. m. The thin film transistor of the present invention utilizes the channel composite layer 11G as a channel region of the element, which combines the low resistance of the amorphous pin thin m 〇8 The value and A itself contain the number of defects, such as the number of defects, which can improve the driving muscle of the thin film transistor and suppress the light under the illumination operation. Leakage current. The film transistor of the present invention will be described below with reference to FIG. 1D. The material and formation method of the film-forming portion of the thin-film transistor have been mentioned in the above embodiments, and therefore will not be described herein. Referring to FIG. 1D, the thin film transistor includes a substrate 1 闸, a gate 1 〇 2, a gate dielectric layer 104, a channel composite layer 11 〇, an ohmic contact layer 112, a source region IHa, and a drain region 114b, wherein the channel composite layer 11〇 is composed of, for example, an amorphous iridium film 1〇6 disposed on the thyristor layer 104 and an amorphous yttrium film 1〇8 disposed on the amorphous iridium film 106. The thyristor layer 1〇 4 is disposed on the substrate 100 and covers the gate 1〇2 disposed on the substrate 100. The channel composite layer 110 is disposed on the portion of the gate dielectric layer 1〇4. The ohmic contact layer 112 is disposed on the channel composite layer 110. A portion of the channel composite layer 110 on the gate electrode 1 is exposed. The source region 114a and the drain region 114b are disposed apart from each other in the gate dielectric layer 104 and cover the ohmic contact layer 112. In another embodiment, The structure of the channel composite layer 11〇 may also be opposite to that in the above embodiment, that is, the channel The layer 110 may also be an amorphous germanium film 108 disposed on the gate dielectric layer 104 and disposed on the amorphous 13 1299^4 19644twf.doc/e 锗 锗 ,, (10), amorphous 夕 〇 〇 6. It is said that the amorphous germanium film has a low resistance value, which can be used in the channel region of the f-film transistor to reduce the on-current to enhance the driving electric scratch. In addition, the amorphous amorphous film 1〇8 itself has a certain amount of defects, and the light leakage current of the thin film transistor can be suppressed by the characteristics of the defect. According to the above, the invention is characterized in that: 1' the invention makes (four) crystal; With the amorphous 9 Lai composition overnight. The layer serves as the channel region of the phase transistor, and the _ amorphous #锗 film has the advantage of low resistance. The large dish|reduces the channel resistance between the source region and the drain region to improve the driving current and device characteristics of the thin film transistor. 2. The present invention forms a non-transcribed film by (4) enhanced chemical vapor deposition or low pressure two-phase deposition, so that the amorphous film itself has a sufficient number of defects. When the _ transistor is illuminated, the above defect can serve as a charge trapping center when the light leakage current phenomenon occurs, so that the light leakage current of the thin film transistor can be suppressed.
3.在不更動傳統薄膜電晶體製程的情況下，於通道區 ^增^本發明之非晶.錢_，使上述兩點優闕合 於薄膜電晶體顯示n中，以提升元件的操作特性。、 雖然本發明已以較佳實施例揭露如上，然其 限定本發明’任何熟習此技藝者，在 ，圍内’當可作些許之更動與潤飾，因此本發以 乾圍當視後附之申請專利範圍所界定者為準。 ’、 【圖式簡單說明】 圖 1A至圖1D為依照本發明之一實施例所繪示之薄 14 I2992J4 19644twf.doc/e 膜電晶體的製造流程剖面圖。 【主要元件符號說明】 100 :基板 102 :閘極 104 :閘介電層 . 106 :非晶矽薄膜 108 :非晶矽鍺薄膜 110 :通道複合層 # 112 :歐姆接觸層 114a :源極區 114b :汲極區3. In the case of not changing the conventional thin film transistor process, the amorphous layer of the invention is added in the channel region, so that the above two points are better matched to the thin film transistor display n to improve the operational characteristics of the device. . Although the present invention has been disclosed in the above preferred embodiments, it is intended to limit the present invention to any skilled person in the art, and it is possible to make some changes and retouchings. The scope defined in the scope of application for patent application shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are cross-sectional views showing a manufacturing process of a thin 14 I2992J4 19644 twf.doc/e film transistor according to an embodiment of the present invention. [Main component symbol description] 100: substrate 102: gate 104: gate dielectric layer. 106: amorphous germanium film 108: amorphous germanium film 110: channel composite layer #112: ohmic contact layer 114a: source region 114b : bungee area
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