TWI298494B - Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays - Google Patents

Description

1298494 IX. INSTRUCTIONS: [Technical Field of the Invention] This application is based on and claims under 35 USC § 119(e): US Patent Provisional Application No. 60/64, filed on Jan. 3, 2005 No. 229; U.S. Patent Provisional Application No. 60/647,012, filed on Jan. 27, 2005; U.S. Patent Provisional Application No. 60/689,231, filed on June 10, 2005; and application on June 10, 2005 The priority of the U.S. Patent Application Serial No. 60/689,314, the entire disclosure of each of which is incorporated herein by reference. [Prior Art] Non-volatile memory (NVM) refers to a semiconductor memory that continuously stores information even when components are removed from an NVM unit. NVM includes masked read-only memory (Mask ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EpR〇M), and electrically erasable programmable read-only memory Body (EEPROM), and flash memory. Non-volatile memory systems are widely used in the semiconductor industry and are developed to prevent the loss of data-like memory. The end user requirements of the non-volatile memory are stylized, read and/or erased, and the programmed data can be stored for a long period of time. Unit design. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _This setting = 'T power supply hole direct material maintenance is usually poor, partly because even ::: except: rate 'but the M is in the C memory element retention 681939-27U4 1298494 state may exist during the low electric field Direct wear will also occur under strength. Another-NVM design is NR0M (nitride-only memory) which uses a thicker tunnel oxide layer to prevent charge loss during the hold state. However, the car = thick oxide layer may affect the channel erasing rate. As a result, the band-to-band thermal hole (BTBTHH) erasing method can be used to inject the hole (10) to compensate for the (4) sub-, however, the BTBTHH erasing method may cause some reliability problems. For example, the characteristics of the NBT component of the BTBTHH erased branch can be degraded after multiple P/E (stylization/erasing) cycles. Therefore, there is a need in the art for a non-volatile, non-volatile design and array that operates multiple times (stylized/erased/read) with improved data retention performance and increased f-rate. SUMMARY OF THE INVENTION The present invention relates to non-volatile memory elements, and more particularly to non-volatile memory elements including a tunnel dielectric structure that facilitate self-convergence erase operations while also maintaining memory elements in (four) states (four) The charge in the reservoir is maintained. A specific embodiment of the present invention includes a memory unit including: a semiconductor substrate having a source region and a drain region disposed under the surface of the substrate and separated by a channel region; and a dielectric structure And the system is disposed on the channel region, the tunnel dielectric structure comprises at least a layer having a small hole penetrating south of the barrier; a charge storage layer disposed on the channel dielectric structure; The layer is disposed on the charge storage layer, and a gate electrode is disposed on the insulating layer. Another embodiment of the present invention includes a memory unit comprising: a half 681939-27U4 7 1298494 conductor substrate having a source region and a drain region disposed under one surface of the substrate and separated by a channel region; a multilayer tunnel dielectric structure is disposed on the channel region, the multilayer tunnel dielectric structure including at least one layer having a small hole tunneling barrier height; a charge storage layer disposed in the multilayer tunnel a dielectric structure; an insulating layer disposed on the charge storage layer; and a gate electrode disposed on the insulating layer.

In some preferred embodiments, the layer provided with a small hole penetration barrier height may contain a material such as tantalum nitride (Si3N4) or hafnium oxide (Hf02). In some preferred embodiments of the invention, the memory cells comprise a stacked dielectric dielectric structure having a plurality of layers of tunnel dielectric structures, such as hafnium oxide, tantalum nitride, and iridium oxide. These tunnel dielectric structures provide a SONONOS (Shihs oxide-nitride-oxide-oxide/oxide) or super-lattice SONONOS design. In some preferred embodiments of the invention, the tunnel dielectric 1 comprises at least two dielectric layers, each layer having a severity of up to about 4 nm. In addition, in the preferred embodiments of the present invention, the gate electrode has a work function value greater than that of the Ν+ polycrystalline stone. In some preferred embodiments, the tunnel dielectric structure may include a layer comprising a material having a small hole tunneling barrier height, which is present in the layer with a concentration gradient such that the material is concentrated; The department is the maximum. In the case of a pet, a f ===2 non-volatile memory element, which comprises a plurality of memory cells according to the ones described herein, and the plurality of memory cells are used herein. "plural" means two or Two σ or more 681939-27U4 8 1298494 according to the present invention: It is a significantly improved operational property, including the operation of the power supply and the larger operation window. . Including the addition of the speed of the book, "Ming also includes the operation of the fall according to the invention: / name ^ early 兀 and array method.

The vt distribution of the billion rate and the modified component is closely followed by the application of the self-convergence method to program the memory to the element; the component is injected through at least (four); and by applying - in Memory pressure, to read (four) level and stylized state level between the electric evangelism and eclipse 1 'lupe pieces at least one. As used herein, the term "tight" is narrow. And the distribution of the threshold electrical history in many memory cells of an array becomes a tongue, and the threshold voltage distribution is "compact" in which a number of voltages are within a narrow range of each other, so that the operation of the array is better than conventional. Juice improvement. For example, in some preferred embodiments, as indicated by the g-threshold voltage distribution including the compactness of the Να rib array according to the present invention or the memory cells in the plurality of embodiments, The voltage limits are within the range of 〇·5ν. Other use of the memory list according to the present invention

In a chirped array architecture, the "compact" threshold voltage distribution can have a range from about an upper limit to a lower limit of about 1.0V. A specific embodiment of a method of operation in accordance with the present invention includes operating an array in accordance with the present invention by applying a self-converging reset/erase voltage to a substrate and gate in each memory cell to be reset/erased And arranging the plurality of memory cells at least and by applying a voltage between at least one of the erased state level and the stylized state level in the memory elements to read the plurality of memory cells At least one of them. The present invention also includes a method of forming a memory cell, comprising: providing 681939-27U4 9 1298494, a conductor substrate having a source region formed under the surface of the substrate and separated by a pass region and a drain region; forming a tunnel dielectric structure over the via region, wherein forming the tunnel dielectric structure includes forming at least two dielectric layers 'where the at least two dielectric layers have a layer having a ratio of the at least two dielectric layers The other layer has a small hole tunneling barrier height; a charge storage layer is formed on the tunnel dielectric structure; an insulating layer is formed on the charge storage layer; and the gate layer is formed in the insulating layer.

The term "small hole tunneling barrier height" as used herein generally refers to the value of the approximate hole tunneling barrier height of J or equal to cerium oxide. In particular, the tunneling height of the two small holes is preferably less than or equal to about 4.5 eV. A better 糸rL electric tongs with a tooth height is less than or equal to about L9eV. [Embodiment] For the purpose of referring to the present invention and its preferred embodiments, the singular elements of the singularity of the singularity of the singularity of the same or similar parts will be the same or similar. Attention should be paid to the non-graphics:; the form of the uncovering and not in exact proportions. Regarding the ministry, the bottom, the left, and the right, the directional term (such as before and after) is directed against the system. And the following descriptions of the following, below, and the following description of the drawings shall be deemed to be in any application not covered by the patent: =: equal = system. It should be understood that the process steps disclosed herein are the complete process of the integrated circuit. The present invention can be implemented or developed in conjunction with various integrated circuit fabrication techniques of the technique: 681939-27 U4 1298494. The memory unit in accordance with the present invention overcomes some of the reliability issues in SONOS and NR0M components. For example, a memory cell junction in accordance with the present invention can allow for a fast FN channel erase method while maintaining a good charge retention feature. Various embodiments of the memory unit according to the present invention can also alleviate the dependence on the "61^丁1111 erasing method, thereby avoiding degradation of the component after multiple P/E cycles. In an embodiment where the electrical structure is a multilayer structure, an ultra-thin tunnel dielectric or an ultra-thin oxide layer is combined with a small hole tunneling barrier layer. This provides better stress relief. After the /E cycle, the non-volatile memory cell according to the present invention also exhibits a small amount of degradation. The memory cell according to the present invention can be designed using an n-channel or p-channel, as shown in Figures la and lb. Figure la depicts an embodiment of the present invention. A cross-sectional view of the n-channel memory cell 100. The memory cell includes a substrate having at least two n-type doping regions 102 and a 1 〇4 ip-type substrate, wherein the functions of the doping regions 102 and 104 can be applied according to The voltage is the source or the drain. As shown in Figure la, for reference purposes, the doped region 1〇2 can serve as the source and the doped region 104 can serve as the drain. The substrate 1〇1 is in the n-type Further in the interval, include the channel area 1〇6. In the channel area 1〇6 Square (on the surface of the substrate (8) tunnel dielectric structure 12 〇. In some preferred embodiments, the channel 120 may comprise a three-layer thin 〇Ν〇 structure, wherein a small hole tunneling barrier is highly nitrided The layer 124 is sandwiched between a lower thin oxide layer m and an upper germanium oxide layer 126. The memory unit 1 further includes a charge trapping on the intervening dielectric 681939-27U4 11 1298494, and the alpha structure 120 ( Or a charge storage layer i3〇 (preferably a nitride)>, and a germanium edge layer 140 (preferably comprising a barrier oxide) is disposed on the charge trapping layer H. A gate 15 is provided in the insulating layer Figure lb depicts a cross-sectional view of a p-channel memory cell in accordance with an embodiment of the present invention. The memory cell includes an n-type substrate 2〇1 containing at least two P-type doped regions = 2 and 204, The function of the change zone and the function of the change zone may be source or immersion. The base twist basket 201 further encloses a channel zone 206 in the two p-type doping section. ρ channel seal retention - layer thin _ structural ground = = three 丨, 、, 口 〇 22〇 (one of the small holes through the tunneling nitride layer 224 is sandwiched between - the thin oxide layer 222 And above the thin: reed; 4〇22: between a charge trapping (or charge storage) layer 23, - insulating layer 240 and a gate 25 〇. Unit: t including, for example, f Figure 1 & lb and The memory according to the present invention: a thin-layer dielectric structure comprising a -d-cerium oxide layer 01, a tantalum-nitriding layer N1 and a charge storage layer, for example, a second nitrogen layer N2; and - for example, the insulating layer of the third oxidized stone layer 03, 1 wei zhi zhi xiao, + feng conductor matrix (such as Shi Xi matrix) resetting the operation from the base _ charge storage layer. Jia (4) Niu H Invented the memory unit 3::"Efficiency' and better is complete during memory operation; captures such as nitrite layer, Hf〇2 and 〇3 A small hole in the electrical structure is used for the barrier level: 681939-27U4 12 1298494 Preferably, an effective charge storage material such as a nitrogen cut can be used as the charge storage layer in the memory element. Barrier oxide for preventing charge loss: used as an insulating layer 'for example, a third oxygen layer 〇3. The memory unit according to the present invention also includes a gate or an interpole electrode on the insulating layer, such as a polycrystalline intertidal pole. The tunnel dielectric structure, the electric storage layer, the insulating layer and the gate may be formed on at least a portion of the substrate, which is defined by the source region and the non-polar region and disposed therebetween.

A memory cell in accordance with various embodiments of the present invention includes a tunnel dielectric structure that provides a fast FN erase rate of about 10 milliseconds at a negative inter-electrode voltage (10) such as from about _10 to about _2 〇v. On the other hand, charge retention can still be maintained and, in some instances, may be better than many conventional s〇N〇s components. The memory unit according to the present invention can also avoid the use of the inter-band thermal hole erasing operation 'the NRQM element +. Avoiding this two-hole hot hole erasing operation can greatly eliminate the damage caused by the hot hole, which is avoided. Referring to Figure 2, an experimental measurement for the threshold voltage of a structure in accordance with the present invention - an embodiment - shows that - ultrathin (1) chest disorder selection can have - negligible trapping efficiency, as in continuous stylization: It is proved by the constant threshold voltage level. The layer thickness (4) tested for Figure 2 was 3. , 3 () and 35 angstroms (A). As shown in Figure 2, in the use of stylized methods (ie _FN stylized, +fn CHE (woven) stylized) in a number of stylized: the process of the number of = the limit voltage vt remains stable at approximately I · 9 volts. The r ^ 01/N1/02 film can be used as a modulation tunnel. Therefore, this ultra-thin ~ structure. The results under various charge injection methods including CHE, 681939-27U4 13 1298494 + FN and -FN show negligible charge trapping. The process or component structure can be designed to minimize interface traps so that the 01/N1 or N1/02 interface is functional. Figure 3 shows an erase feature of a memory cell having a SONONOS design in accordance with an embodiment of the present invention. The memory cell of the embodiment shown in Figure 3 comprises an n-MOSFET design of a tunnel dielectric structure having a thickness of 15 angstroms and 20 angstroms and 18 angstroms, respectively. The memory cell of this embodiment comprises a tantalum nitride charge storage layer having a thickness of about 70 angstroms, an insulating oxidized oxide layer having a thickness of about 90 angstroms, and a gate comprising any suitable conductive material, such as n-type doping. Polycrystalline germanium. Referring to Figure 3, a fast FN erase can be achieved (e.g., within 10 milliseconds) and an excellent self-convergent erase property can be obtained. Figure 4 shows the charge retention characteristics of a SONONOS component in accordance with a specific embodiment of the memory cell of the present invention described with reference to Figure 3. As shown, these retention features are better than conventional SONOS components and may be of multiple levels in terms of current values. Figures 5a and 5b show an energy band diagram showing the possible effects of using a tunnel dielectric structure containing at least one layer, wherein the at least one layer has a small hole penetration resistance P early. The energy band diagram of the tunnel dielectric structure (01/N1/〇2 three layers in this example), which may exist during a low electric field during the retention of the memory data, is shown in Figure 5a. It can be removed as indicated by a dotted arrow at a low electric field, while providing good charge retention during the hold state. On the other hand, the shift of the energy band under a high electric field (as shown by the head of the 5b towel) can reduce the barrier effect of ni and 02 so that direct wear through (1) may occur. A tunnel dielectric structure having at least a small hole through barrier height layer may allow 681939-27U4 (S: 14 1298494 effect fn erase operation. Figures 5c and 5d show another set of energy band diagrams in one example. For a preferred energy band offset condition in an example, the thickness of N1 may be greater than 01. The energy band diagram of the valence band is at the same electric field E01=14 MV/cm. The tunneling probability according to the WKB approximation is The shaded area is related. In this example, for the thickness N1 = 01, the band offset does not completely block the barrier of 〇 2. On the other hand, for Nl > 01, the band offset can be more easily blocked. Therefore, for the thickness Ν1>〇1, the hole penetration current may be larger under the same electric field in 〇1. An experiment with measured and simulated hole tunneling current (as shown in Figure 6) Some embodiments of the invention pass through a cavity tunnel of a tunnel dielectric structure. For example, a tunneling current through a dielectric of 〇l/Nl/〇2 dielectric can fall between an ultrathin oxide and a thick oxide. In one example, under high electric fields, the tunneling current can approximate an ultra-thin oxide. However, under low electric field, direct tunneling can be suppressed. As shown in Fig. 6, even at a low electric field strength of only 1 MV/cm, the tunnel tunneling current can be detected through a thin oxide layer. At a relatively high electric field strength such as U, a thick oxide can be ignored. However, when a high electric field strength occurs, the tunneling current through a tunnel dielectric structure reaches a thin oxide layer. In 6, the large current leakage caused by tunneling through a low-field hole through a thin oxide can be seen in the region 图 in the figure. In Figure 6, a 01/N1/02 tunnel dielectric structure is passed at high electric field strength. The hole tunneling current can be seen in the area B in the figure. In Figure 6, the 681939-27U4 1298494 tunneling is essentially non-existent at a low electric field through a 01/N1/02 channel dielectric structure and thick oxide. The current can be seen in region c of the figure. The memory cell design in accordance with the present invention can be applied to a variety of memory types including, but not limited to, N〇R and/or NAND type flash memory. As described above, the tunnel The dielectric layer may include two or more layers to Including: one layer that provides a small hole tunneling barrier height. In one example, a layer that provides a small, hole-to-barrier height may contain nitrite. This layer may be placed in a layer of oxidized stone layer. Between the two, if the nitrite is used as the intermediate layer, the 〆0/N/Q channel can be formed. In some preferred embodiments of the present invention, the layers in the channel dielectric structure are up to about 4 nm thick. In some preferred specific examples, the thickness of each layer in the tunnel dielectric structure may be about 1 to 3 nm. In the exemplary component, a three-layer structure may have a ^, a bottom layer of 1 angstrom to 30 angstroms (e.g., a layer of oxidized stone), an intermediate f of about 1 angstrom to a angstrom (e.g., a nitride layer), and a top layer of about 1 angstrom to 3 angstrom (e.g. Further - yttrium oxide layer) C In a specific example, a three-layer structure having a bottom oxidized stone layer of -15 angstroms, a middle fossil layer of 2 angstroms, and a top of 18 angstroms may be used. Oxide layer. In one example, a thin 0/N/0 three-layer structure shows a negligible charge Μ' such as the theoretical energy band diagram and the wear current analysis described in Tea Examinations 5a, 5b, and 6. It may be suggested that The dielectric structure (for example, a 01/N1/02 structure with a thickness of 3 nm or less) can suppress direct tunneling of the hole under low electric field during the holding period. At the same time, effective hole tunneling is still allowed at high electric fields. This can effectively block the N1 and 〇2 tunneling barriers due to the band offset. Therefore, the proposed component provides fast hole tunneling erase while eliminating the problem of conventional SONOS components. Experimental analysis shows the excellent durability and retention properties of the memory cells of the various embodiments of 681939-27U4 16 1298494 in accordance with the present invention. In some preferred embodiments, the tunnel dielectric structure includes at least one intermediate layer and two adjacent layers on opposite sides of the intermediate layer, wherein the intermediate layer and the two adjacent layers each comprise a first material and a first The second material, wherein the second material has a valence level greater than a valence band level of the first material, and the conduction band level of the second material is less than a conduction band level of the first material; The concentration of the two materials is higher than the intermediate layer between the two adjacent layers, and the concentration of the first material is higher in the two adjacent layers than the intermediate layer. Preferably, in a tunnel dielectric structure according to this embodiment of the invention, the first material comprises oxygen and/or oxygenates, and the second material comprises nitrogen and/or nitrogen containing compounds. For example, the first material can include an oxide (e.g., hafnium oxide) and the second material can include a nitride, such as Si3N4 or Six〇yNz. The tunnel dielectric according to this aspect of the invention may be composed of three or more layers, all of which may contain similar elements (e.g., Si, N, and 0) as long as the concentration of the material having the minimum hole tunnel barrier height is in the middle The inner layer of the layer is higher than the two adjacent layers. * In a tunnel dielectric structure according to a prior embodiment of the present invention, the second material may be present in the intermediate layer in a gradient concentration such that the concentration of the second material in the intermediate layer increases from an adjacent layer/intermediate layer interface The maximum concentration at a deep point in the intermediate layer, and from the deep point of the maximum concentration to a lower concentration at the interface of the other adjacent layer/intermediate layer. The increase and decrease in concentration is preferred to be progressive. In still other embodiments of the present invention, the tunnel dielectric structure includes at least one intermediate layer and two adjacent layers on opposite sides of the intermediate layer, wherein two adjacent 681939-27U4 17 8 1298494

a dielectric dip, the first material comprising an oxygen and/or an oxygen containing layer comprising a first material and the intermediate layer comprising a material having a valence band level greater than the first material and the second material comprising nitrogen and/or Or a nitrogenous compound. For example, the first material ς may comprise an oxide (e.g., yttrium oxide) and the second material may comprise a nitride (e.g., Si3N4 or SixOyNz). For example, in a particular embodiment of the invention in which the tunnel dielectric layer comprises a three-layer 〇N〇 structure, the bottom oxide layer and the top oxide layer may comprise dioxide and the intermediate nitride layer may be, for example, bismuth oxynitride. And a tantalum nitride composition, wherein the concentration of tantalum nitride (ie, a material having a smaller hole tunneling barrier height therebetween) is not fixed in the layer, but is between the two interfaces having the sandwiched oxide layer. The maximum is reached at some deep points in the layer. The precise point in the intermediate layer in which the material having the minimum hole penetration height is at its maximum concentration is not critical as long as it occurs in a gradient and reaches its maximum concentration in the tunnel dielectric layer at some point in the intermediate layer. . The gradient concentration of the material having the minimum hole tunneling barrier height can be beneficial to improve various properties of the non-volatile memory component, especially those having a SONONOS or SONONOS-like structure. For example, it can reduce the charge loss of 681939-27U4 18 !298494 fe, which can improve the charge trapping in the tunnel dielectric under the high electric field. The energy band diagram of the intervening dielectric layer can be advantageously modified in accordance with this aspect of the invention such that the valence band level and the conduction band level of the intermediate layer do not have a value, but the thickness across the layer follows A change in the concentration of the material with a minimum hole penetration resistance. Referring to Fig. 5e, a (10) 0 layer-by-channel dielectric (4) correction system according to this aspect of the invention is shown in a transmission-energy band diagram. : The outer layer (layer) and layer 3) are changed by the oxidation of the ) ) i i i i 会 会 会 会 会 会 会 会 会 会 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪 浪Figure 5, the depth of the layer reaches the maximum. It is represented by the inductive material, which is described by the dotted line. As shown in the figure, the concentration of the alternative tantalum nitride is the most ▲ a. The conduction energy band π ^ takes the low-cost energy level and the highest value. The V-level is consistent with the maximum concentration of the bismuth telluride. , the hair (4) and other specific methods are prepared in many ways. For example, any (four) θ m, "冓 can be formed into a -m & county town of the oxidative effect of the gas 虱 虱 矽 矽 or arsenic oxynitride layer, the method sentence twist &: in thermal oxidation, freedom Base (ISSG) oxidation, as well as chemical vapor deposition process. One or two electro-hydraulic emulsification / emulsification: the interlayer can then be, for example, via chemical vapor deposition, in the first - waste part of the open gentleman, Ge Yuanyuan The plasmonics TM to form the second third emulsion or oxynitride. The "upper oxide layer" can then be formed, for example, by oxygen or chemical vapor deposition. Ikeda 虱 作 681939-27U4 19 1298494 - The charge storage layer can then be formed into a mechanical dielectric structure. In a model: households can form a charge of about 5 nm to 1 G nm on the accompanying dielectric structure. In a particular example, nitriding g of about 7 nm or more can be used. The insulating layer on the charge storage layer can be from about 5 nm to 12 nm. ^ 艟: Use an oxidized dream layer of about 9 nm or more. And by heat: at least a portion of the ruthenium oxide layer to form a ruthenium oxide layer. Any known or to-be-developed method of forming a plurality of layers of suitable materials than j is described herein,

H is used to deposit or form an intervening dielectric layer, a charge storage layer, and a domain insulation (3). Suitable methods include, for example, thermal growth methods and chemical vapor deposition methods. In an example, the thermal conversion process can provide a high density or concentration interface that can increase the trapping efficiency of the memory element. For example, the thermal conversion of the nitride can be carried out at about 1000 ° C while the gate flow ratio is H 2 : 〇 2 = 1 〇〇〇 : 4 〇〇〇 sccm. In addition, since tantalum nitride has a very low (about 19 eV) resistance P sheep, its tunneling to the hole can be made unobstructed under a high electric field. At the same time: the total thickness of the tunnel dielectric (such as the ΟΝΟ structure) can prevent electrons from being directly worn under. In the example, this asymmetrical behavior provides that the memory element not only provides fast hole tunneling erase, but also minimizes or eliminates charge leakage during hold. A 0.12 micron NR0 allows Bit technology to create an exemplary component: Table 1 shows the component structure and parameters in the example. It is revealed that there is a ::specific: the tunnel dielectric can change the tunnel tunneling current. In an example, the two-one parent thick (7 nm) N2 layer can serve as a charge trapping layer, and a layer of 〇3 (9 shows no) can serve as a barrier layer. Both N2 and 03 can be fabricated using nr〇m/nb ^ 681939-27U4 20 1298494 Technology Table 1 _ ^ Part Oxide (01) _ Intermediate Nitride (N1) 1 Oxide (02) 1 Nitride ( N2) j and oxide (03) N+ polymorph il 20 18^ 70 90 channel length: 〇.22^£ __ channel width: 0.16 micro-gate can include work function in some preferred embodiments of the invention , two (7) 1 bar with a work function ^ greater than N + polycrystalline Huan (four). DETAILED DESCRIPTION OF THE INVENTION In the present invention, the high work function gate material may comprise, for example, platinum, rhodium, tungsten, and other metals. Preferably, the gate material of these embodiments is preferred, and in the embodiment of the invention, 匕3 is a work function metal such as platinum or rhodium. Further, preferred nitrogen:: _ includes but is not limited to p + polysilicon, and metal nitrides such as titanium nitride and ", S. In a particularly preferred embodiment of the invention, the 'gate material comprises platinum. An exemplary component having a high work function gate material in accordance with a preferred embodiment of the present invention may also be fabricated by a 0.12 micron NROM/NBit technique. Table 2 shows the component structure and parameters in an example. The tunnel dielectric with ultra-thin 0/N/0 can change the tunnel tunneling current. In the example - \ 681939-27U4 21 1298494 a thicker (7 nm) N2 layer can be used as a charge trapping layer, and a layer of 3 (9 m) can be used as a barrier layer. Both N2 and 〇3 can be manufactured using NR〇M/NBit technology.

Table 2

Bottom oxide Intermediate nitride 15 20 Intermediate oxide 18 70 Compound (N2) Barrier oxide Gate: Platinum Channel length: 0.22 μm —— _ Channel width: 0.16 μm __

The memory unit having a high work function gate material according to an embodiment of the present invention, and the eraser property which is much improved by the member than the other specific embodiments. The high work function = pole material suppresses the gate electron trapping layer. In some specific embodiments of the present invention, the "memory cell contains - Ν + polycrystalline stone 闸 亟 亟 在 在 在 抹 = 门 门 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = This self-removal erase effect results in a higher _ limit voltage level in the erased state towel, which may not meet the demand in an ND application. A memory unit having a high power alpha gate material embodiment in accordance with the present invention can be used for various types of memory, including, for example, NOR and NAND type memories. However, a memory cell having a high work function gate material embodiment in accordance with the present invention is particularly suitable for use in NAND applications where the threshold is raised in the erase/reset state. 681939-27U4 22 1298494 does not meet the requirements. According to the present invention, the memory cell having the high work function inter-electrode material can be erased by the hole-punching method and the preferred system by the -FN erasing operation. * - One has - ON An example of a tunneling dielectric and an N+ polysilicon gate can be programmed by the conventional SONOS or NROM method and erased by the tunneling of the FN hole. The figure shows an example in one example. ON. Erasing characteristics of exemplary s〇N〇N〇s components of tunneling dielectric. Refer to Fig. 7a: - Higher gate voltage results in faster erase rate. It also has higher saturation. Vt' is also stronger because of the gate injection and the resulting dynamic equilibrium point (which determines Vt) is higher. The right-hand side of the figure shows that the threshold voltage reaches a minimum value of about 3 to about 5 volts depending on the eraser voltage. The hole tunneling current can be extracted by a transient analysis method by the curve in the differential graph %. The extracted hole current system from the measured value in Fig. 7a is shown in Fig. 6 as discussed above for comparison 'also using WKB approximation Simulated hole tunneling current. The experimental results are reasonably consistent with the prediction. Under field, wear with current. Through the 01/N1/02 stack to reach the ultra-thin, while it is under the low electric field, some specific embodiments of the memory unit with high work function idler material according to the present invention (where the high work function is In the gate suppression idle electron injection), depending on the erase time, the threshold voltage of the component may be much lower and even negative in the erase or reset state. According to the invention, the memory component of the embodiment The threshold voltage value (in which the gate is composed of molybdenum dielectric layer including 15/20/18 angstrom 0N0 structure) is shown in Figure %. As shown in the figure, the -FN erasing operation is similar in the interpole. At the voltage (_i8v), the threshold voltage of the component 681939-27U4 23 1298494 can be set below _3γ with respect to the gate voltage value. Figure 7c shows the corresponding component

Further, in accordance with the present invention, a memory read with a high work function interpole material embodiment of the memory read the ship quality red one. The retention properties of the (fourth) memory element are not shown in Figure 7d, where the capacitance is shown after erasing and stylization, and then after 3G minutes after each operation and two hours after each operation with the gate voltage function. The minimum deviation has been observed. A memory unit in accordance with various embodiments of the present invention can operate with at least two separation schemes. For example, CHE stylization with a read-to-read 1 can be used to perform a -2 bit S/cell operation. In addition, low power programming (mode 2) can be used as a -2 bit/cell operation. Both modes can be used with the same hole through the 13⁄4 erase method. The mode 丨 is preferably used as the imaginary __ of the n〇r type flash memory, and the flash memory of the genre 2 is more than the (4) sin nand type. The example of Fig. 8 shows the excellent endurance properties of the virtual ground array architecture N〇R type flash memory in accordance with an embodiment of the present invention under mode operation. Erasing degradation of such memory elements with tunnel dielectric structures does not occur because hole tunneling erase (Vg = _15V) is a uniform channel erase method. A corresponding iv curve is also shown in Figure 9, which shows a slight degradation of the element after multiple p/E cycles. In one example, this may have good stress relief properties due to the ultra-thin oxide/nitride layer. In addition, the memory element does not suffer from the introduction of thermoelectric holes. Figure 10 is a diagram showing the durability of a NAND type flash memory in mode 2 operation in accordance with an embodiment of the present invention. For faster erasure, a larger bias voltage (Vg = _i6V) can be used. 681939-27U4 % 24 1298494 Excellent durability is also obtained in this example. 4 shows the charge retention of an exemplary SONONOS device in accordance with an embodiment of the present invention in which only a charge loss of 60 mV was observed after 10 hours. This improved solution has a higher current rating than conventional SONOS components. The VG acceleration hold test also shows that direct tunneling can be suppressed at low electric fields. Figure 11 shows an example of a VG acceleration hold test for a 10Kp/E cycle component. The charge loss is small under the -VG stress after 1 〇〇〇 stress, and its I 曰 can suppress the direct tunneling of the hole at the small electric field. Therefore, the s〇N〇N〇s design referred to in the above examples provides a fast hole tunneling erase with excellent durability. As indicated above, this design can be implemented in NOR and NAND type II nitride storage flash memory. Moreover, a memory array in accordance with an embodiment of the present invention can include a plurality of memory elements having similar or different configurations. In various embodiments of the array in accordance with the present invention, memory cells in accordance with the present invention may be used in place of conventional NROM or SONOS components in a virtual (10) column architecture. It can be solved or mitigated by using FN hole wear rather than hot hole injection. Without the specific structure described below, (4) of the present invention, the town will describe various methods of operation of the (10) body array of the present invention for the exemplary facilitated grounding array architecture. More CHE "CHISEL (channel abrupt secondary electron) stylization and reverse can be used for 2-bit/cell memory arrays. And the erasing method can be - ^, iL FN electric / same tunnel erasing. In one example, the array is a virtual ground array or a JTOX array. Referring to Fig. 12a_2, a three-layer structure of f 681939-27U4 25 1298494 oimi/〇2 can be used as a channel dielectric, and the thickness of each layer is about less to provide direct hole penetration. Referring to Figure 12, the heart can be sinful = thick to provide - high trapping efficiency. The insulating layer (Q3) may be rolled (4), for example, converted to a top oxide (oxygen cut), to provide a dense trap at the interface between 〇3 and N2. 〇3 can be thicker to prevent charge loss from this oxygen cut layer. ^

Figures 12a and 12b show an example of a memory single-ground array architecture incorporating the above discussion, such as having a three-layer 〇Ν〇-channel dielectric: memory cell. In particular, _ 12a shows the equivalent circuit of the rhyme-like portion and FIG. 12b shows the exemplary layout of the memory array-part. In addition, FIG. 13 shows the section of several memory cells incorporated in the array. schematic diagram. In one example, the buried diffusion (BD) region can be an N+ doped junction for the source or drain region of the memory cell. The matrix can be a p-type matrix. In order to avoid collapse of the BDOX region (oxide on BD) during _;pN erasure, a thick BDOX (> 50 nm) can be used in one example. Figures 14a and 14b show a possible electronic reset (RESET) scheme for incorporating an exemplary virtual ground array with a 2-bit/cell memory cell of the tunnel dielectric design described above. All components may first experience an electronic "RESET" before performing further P/E cycles. A RESET process ensures that the vt of the memory cells in the same array is consistent and the component vt is raised to the converged erase state. For example, applying ¥8 = -15 i for i seconds (as shown in Figure 14a), there may be an effect of injecting some charge into the nitride trapping layer to achieve dynamic equilibrium conditions. With RESET, although the memory cell is unevenly charged due to, for example, the plasma charging effect in its process 681939-27U4 26 1298494, its vt can be converged. An alternative method for generating self-converging bias conditions is to provide a bias voltage for the gate and substrate voltage «%. For example, referring to Fig. 14b', Vg:=:_8v and ρ well:=+7V can be applied. Figures 15a and 15b show a stylized scheme for incorporating an exemplary virtual ground array with a 2-bit/cell memory cell of the tunnel dielectric design described above. Channel hot electron (CHE) stylization can be used to program the component. For the Bit-Ι stylization shown in the figure ‘l5a, the electron system locally injects the junction edge on the BLN (bit·rude N). For the Bit-2 stylization shown in Figure ISb, the electronics are stored on the BLN-I. A typical stylized voltage for WL (word line) is typically about 3 to 7V for a typical stylized voltage of about 6V to 12VqBL (bit line) and keeps the p well grounded. 16a and 16b show a read scheme for an exemplary virtual ground array for incorporating a 2-bit/cell memory cell having the tunnel dielectric design described above. In one example, a reverse readout system is used to read this. The component performs a 2-bit/cell operation. Referring to Figure 16a, for reading Bit-1, the BLN-I is applied with a suitable read voltage (e.g., L6V). Referring to Figure 16b, the read bit-2' BLN is applied with a suitable read voltage (e.g., 16V). In one example, the read voltage can be in the range of about i to 2V. The word line and p well can be kept grounded. However, other modified read schemes can also be implemented, such as the Vs reverse readout method. For example, a boost Vs reverse readout method can use Vd/Vs spit 8/0.2V for read threat 2 and Vd/Vs42/1_8 for read Bit-1. Figures 14a and 14b also show a sector wipe 681939-27U4 27 1298494 scheme for incorporating an exemplary virtual ground array with a 2-bit/cell memory cell having the above described tunnel dielectric design. In one example, a sector erase and channel hole wear erase can be applied simultaneously to erase the memory cell. The tunnel dielectric having a SONqnos structure in the memory cell provides a fast erase which can occur in about 1 〇 to 5 毫秒 milliseconds and in the self-converging channel erase rate. In one example, the sector erase operation condition can be similar to the RESET process. For example, referring to Figure 14a, ¥(}=about _15¥ is applied simultaneously at WL and all BLs are left floating to reach the sector erase. And the P well can remain grounded.

Alternatively, a sector erase can be achieved by applying about _8V to WL· and about +7V to p well with reference to Figure 14b'. In some examples, a full sector erase operation can be implemented in just milliseconds or less without any cells that are erased or difficult to erase. The design of the upper component can be beneficial—providing channel erasure with excellent self-convergence properties. Figure i7 shows the eraser specification in the example using a SON〇N〇s component. An example of a S0N0 deletion component can make 〇1/m/〇2/N fine factory 约 约 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有The erased t rate for various gate voltages has been shown. More than two gate voltages result in a faster erase rate. Pressed; two = extremely high two::: = electric crystal spade gate or other metal gate as a gate material 2: reduce the gate to inject electrons. Wood 1 spear ^ month ^ shows that the SQNQ swollen component is used for the virtual ground (four) architecture. In some cases the durability is excellent. For the Bit_i 0 type condition, 3rd instar 8. Egg, 0gt; 1 microsecond, for 681939-27U4 28 1298494

Vg/Vs = 8.5/4.6 V, 0·1 microseconds. FN erase can use Vg=_i5v for about 50 milliseconds to erase the two bits at the same time. Because the FN erase is self-converging and the channel is erased, cells that are difficult to erase or erase are usually not present. In this example, the exposed component shows excellent durability, even without the use of stylization/erasing verification or stepping algorithms. Figures 19a and 19b show the characteristics during a P/E cycle in an example. The corresponding Ι-V curves in both the logarithmic scale (Fig. 19a) and the linear scale (Fig. 19b) have been shown. In one example, a SONONOS component has a slight degradation after multiple P/E cycles such that both the threshold swing (s s ) and the transconductance (gm) are nearly identical after multiple cycles. This SONONOS component has superior financial properties over NROM components. One reason for this is that unused thermowell injection is used. In addition, an ultrathin oxide disclosed above may have better stress relief properties than a thick tunnel oxide. Figure 20 shows the CHISEL stylization scheme in one example. An alternative to stylizing this component is to use the CHISEL stylization scheme, which uses a negative matrix bias to enhance impact ionization to increase heat carrier efficiency. The programmed current can also be reduced due to body effects. Typical conditions are shown in this figure, where the base system is applied with a negative voltage (-2V) and the junction voltage is reduced to approximately 3,5V. For the conventional NR〇M components and technology, CHISEL stylization is not applicable. Because the gamma-p-thermal cavity eraser may inject more electrons into the central region of the near channel. And the electronics department has no rate. Figure 21a and the design of the NROM component near the center of the channel. JT〇x Luxu—The JT0X virtual grounding array in the example is a prismatic grounded array that provides an alternative implementation of the 681939-27U4 29 1298494 memory in the memory array. In the example, the components in the jt〇x structure and the virtual (4) (iv)-differential TMX structure are shown in Figure 2la by the STI-method from the typical layout example. Figure 21b shows the corresponding equivalent circuit 'which is the same as the virtual ground array. As disclosed above, the memory cell structure in accordance with the present invention is suitable for both NOR and type (4) reading. An additional example of the memory fresh line design and the J staying mode will be described below. Without the structural restrictions described in (4) below

Various methods of operation of the memory array in accordance with the present invention will be described in the context of the exemplary NAND architecture. As described above, an n-channel S_NOS memory element having a germanium tunnel dielectric can be used for a memory element. Tugua and m show examples of NAND array architectures. Figure 仏 and now appear in two different directions - an example of a cage array. The operating materials in the queue may include side stylized, self-reported (four), and erased items. In addition, some methods may include circuit operation methods to avoid stylized interference. In addition to the monolithic gate structure design, a split gate (spht_gate) (four) can be used, such as a NAND array using SONONOS components between two transistor interposers located near the source/bold regions. In some examples, the split gate design can be adjusted to reduce the size of f|jF = 3G nanometers or less. In addition, these components can be designed to achieve good reliability to reduce or eliminate the floating gate coupling effect, or both. As noted above, a s〇n〇n〇s memory element provides excellent self-convergence erase, which assists in sector erase operations and Vt distribution control. Furthermore, the compact erased state distribution can be advantageous for multiple 681939-27U4 30 1298494 quasi-applications (MLC). By using certain designs as memory array structures, the effective channel length (L e ff ) can be expanded to reduce or eliminate short channel effects. Some examples can be devised to avoid the use of a diffusing junction to avoid the challenge of providing shallow junctions or using pocket implants during memory component processing. Figure 1 shows an example of a memory element with a SONONOS design. Further, Table 1 notes the above examples of materials used as different layers and their thicknesses. In some examples, a P+ polysilicon gate can be used to provide a lower saturation reset/erase voltage vt, which can be achieved by reducing gate injection. Figures 22a and 22b show an example of a memory array, such as a SONOSO-S NAND array having memory cells in accordance with the specific embodiment of Table 1, having a diffusion junction. In one example, separate components can be isolated from one another by various isolation techniques, such as by using shallow trench isolation (STI) or isolation on insulator (SOI) isolation techniques. Referring to Figure 22a, a memory array can include a plurality of bit lines (e.g., BL1 and BL2), and a plurality of word lines (such as WL1, WLN-1, and WLN). In addition, the array can include a source line transistor (or source line select transistor or SLT) and a bit line transistor (or bit line select transistor or BLT). As an example, the memory cells in the array can be designed with SONONOS' and the SLT and BLT can include n-type MOS field effect transistors (NMOSFETs). Figure 22b shows an exemplary layout of a memory array, such as a NAND array. Referring to Figure 22b, the channel length of the Lg-series memory cell is the space between the separation lines of the memory element. In addition, the W-series memory cell has a channel degree and the W s is separated from the bit line or the source/nano-pole interval is 681939-27U4 31 1298494 degrees, which in one example can be STI width. Referring again to the diagram and 22b, the memory elements can be connected in series and form a meta-ND column. For example, a string of memory elements can include 16 or 32 memories 70 pieces, providing a string number of 16 or 32. The BLT and SLT can be used as the gate dielectric of the SLT, which can be an oxide oxide m m that does not include the nitriding layer. This, and the states are in some examples (although not necessarily required in all cases) to avoid possible Vt shifts of BLT and SLT during memory array operation. The remote selection system BLT and SLT can use a combination of a plurality of layers of 〇N〇N〇 layers for their gate dielectric layers. In some models, the gate voltage applied to the body and the town may be small; 〇V' may cause less inter-polar interference. If and if the dielectric layer may be charged or trapped, an additional ν § erase can be applied to the gate of the town or SLT to discharge the dielectric layer between them. Referring to Figure 22 &, each BLT can be lightly coupled to the - bit line (BL). In a command, ... BL may be a metal having the same or approximately the same pitch as the STI WT = ground, * SLT is connected to a source line (SL). The source line is connected to and coupled to the sense amplification 11 of the material read sensing. The source line can be,, (e.g., tungsten) or polycrystalline, or - diffused + doped. Figure 23a shows a cross-sectional view of an exemplary memory array =, = long dry square. In general, coffee close-ups can vary with the technology used for manufacturing. Example 2: Use 5. Nano node. ... demonstrative memory; = 681939-27U4 (3⁄4 32 1298494 SONONOS-NAND memory array) section view along the width of the channel. Referring to Fig. 23b, the pitch in the channel width direction is approximately equal to or slightly larger than the pitch in the channel length direction. Therefore, the size of a unit is approximately 4F2/unit. ° In the manufacture of memory arrays (such as the array), this has been

Cheng can, (iv) only two main masks or lithography processes, such as one for polycrystalline lines and the other for STI (bit lines). Conversely, the creation of the letter D, the floating gate private parts may require at least two (four) processing and another - ^ spar stone processing. Therefore, the structure and process of the disclosed device can be simpler than the NAND type floating gate memory. In the example where the STI is used to isolate the discrete memory elements, the trench depth in the state can be greater than the empty width in the P well, especially when the junction bias used is raised higher. For example, the junction bias can be as high as Η for stylized bit read (materialized (four) unselected bit lines). In the example, the depth of the STI region can range from the scope to the nanometer. After the memory array is fabricated, the reset operation can be performed prior to other operations of the memory array to make the vt distribution compact. Figure 24a shows an example of this operation. In an example, before the start of other operations, VG=about ==Fig. 23a may be applied first. In the example, the space between the word lines (wl) (4) 1 is formed with a shallow junction (such as an N+ doped region). Shallow junction), which can be used as the source of the memory element. As shown in Figure 23a, an additional implantation and/or diffusion process (such as a beveled pocket implant) is performed to provide a "pocket" adjacent to the junction of one or more shallow junction areas. Zone or pocket extension. In some examples, this configuration provides better component characteristics. 681939-27U4 33 1298494 • 7V and P-well = +8V to reset the array (the voltage drop of the VG and P wells can be divided into the idle voltage into the WL and ρ wells). During RESET, the BL can float or rise to the same voltage as the P well. As shown in Figure 24b, the reset operation provides excellent self-convergence properties. In one example, even if the SONONOS component is initially charged to various Vt, this reset operation can make it r compact to the reset/erase state. In one example, the reset time is about 1 millisecond. In this example, the memory array can use an η-channel SONONOS device with ONONO = 15/20/18/70/90 angstroms with an N+ polysilicon gate with Lg/W = 0.22/0.16 microns. In general, conventional floating gate components are not capable of providing self-convergence erase. Conversely, the SONONOS component can be operated with a convergence reset/erase method. In some instances, this operation may become important because the initial Vt distribution is typically in a fairly wide range due to specific process issues such as process inconsistencies or plasma charging effects. An exemplary self-convergence "reset" can help to make the initial Vt distribution of the memory element compact or narrow. In the example of stylized operation, the selected WL can be applied with a high voltage (e.g., a voltage of about +16V to +20V) to induce channel + FN injection. Other PASS gates (other unselected WLs) can be turned on to galvanically invert the layer in a nand string. +FN stylization can be a low power method in some examples. In one example, a parallel stylization method such as stylizing a parallel page of 4K byte units can cause the programmatic flux to burst to more than 1 〇 MB/see while the total current consumption can be controlled within lmA. In some examples, to avoid stylized interference in other BLs, a high voltage (such as a voltage) can be applied to other BLs, so that the inversion layer potential is boosted higher to suppress the unselected 681939-27U4 34 1298494 BL The voltage drop in (e.g., cell B in Figure 25). In the example of a read operation, the selected WL can be boosted to a voltage between an erased level (EV) and a stylized status level (pv). The other wl acts as a PASS gate so that its gate voltage can be raised to a voltage higher than pv. In some examples, the erase operation can be similar to the reset operation described above, which can allow self-convergence to the same or similar reset Vt. Figure 25 shows an example of operating an array of memory. Stylized can include channels

+FN electrons are injected into the s〇N〇N〇s nitride trapping layer. Some examples may include applying V Say+18V to selected WLN_;l, and applying VG==about +1〇V to other WLs and BLT4LT may be turned off to avoid channel hot electron injection in unit B. In this example, because all of the transistors in the NAND string are turned on, the inversion layer passes through the strings. In addition, because of Bu, ground, the inversion layer in BL1 has a zero potential. On the other hand, the other rises to a high potential (such as a voltage of about +7V), so that the other 6 [reversal chip potentials are higher. 9 ^ Especially for cell A (which is the selected stylized cell), the voltage is about +18V, resulting in +FN injection. And vt can be raised to pv ^ at: element B, voltage drop + llv, resulting in much less +ρΝ injection, because, = injection system is sensitive to Vg. As for unit c, only + 1〇v is applied, resulting in 汐 or negligible +FN injection. In some of these examples, stylized operations are not described. In other words, other appropriate stylization techniques can be applied. Figures 24a, 26 and 27 further show some examples of array operation, showing the durability and retention properties of some examples. As an example, component degradation after some operations = 681939-27U4 35 1298494 ring can be kept to a minimum. Figure 24a shows an exemplary erase operation that can be similar to the reset operation. In one example, the erase is performed by a sector or block. As noted above, the memory elements can have good self-convergent erase properties. In some examples, erasing saturation Vt may depend on Vg. For example, a higher Vg can result in a higher saturation Vt. As shown in Fig. 26, the convergence time can be about 10 to 100 milliseconds. Figure 27 shows an example of a read operation. In one example, the reading can be performed by applying a gate voltage between a erased state Vt (EV) and a stylized state Vt (PV). For example, the gate voltage can be about 5 volts. On the other hand, other WL and BLT and SLT systems are applied with a higher gate voltage (e.g., about +9V) to turn on all other memory cells. In an example, if the Vt of cell A is higher than 5V, the read current may be extremely small (<0.1uA). If the Vt of cell A is lower than 5V, the read current may be higher (>0.1uA). As a result, the state of the memory (i.e., the stored information) can be identified. In some examples, the pass gate voltage for other WLs should be higher than the high Vt state or the stylized state Vt, but not too high to trigger gate interference. In one example, the PASS voltage is in the range of about 7 to 10V. The applied voltage at BL can be about IV. Although larger read voltages can induce more current, read disturb may become more apparent in some examples. In some examples, the sense amplifier can be placed on the source line (source sense) or on a bit line (not sensed). Some examples of NAND strings can have 8, 16, or 32 memory elements per string. A larger NAND string saves additional overhead and increases array efficiency. However, in some examples, the read current may be small and the interference may be 681939-27U4 36 1298494. Therefore, the appropriate number of NAND strings should be selected based on various design, fabrication, and operational factors. Apricot Figure 28 shows the cycle durability of certain exemplary components. Referring to Fig. 28, = real ^ has a +FN stylized and TM erased P/E cycle, and the result: shows a good endurance feature. In this example, the erase condition is Vg = about -16V up to the millicenter. In some examples, only a single erase is required and verification of the state is not necessary. The memory Vt window is good without degradation.

Figures and 29b show iv features of exemplary memory elements using different scales. In particular, the small wobble degradation of the display element in Figure 29a, and the small transconductance of the external display element of Figure 2 is degraded. Figure 30 shows the retention characteristics of an exemplary S〇n〇n〇S element. Referring to Figure 30, k is well maintained by having a charge loss of less than 100 mV for an element after a 1 〇 κ cycle and after leaving at room temperature for 200 hours. Figure 30 also shows the acceptable charge loss at high temperatures. In some examples, a split gate design (e.g., a split gate SONONOS_NAND design) can be used to achieve further scaling down of the memory array. Figure 31 shows an example of using this design. Referring to Fig. 31, the space (Ls) between two adjacent memory elements or between two adjacent memory elements sharing the same bit line can be thinned. In one example, Ls can be reduced to about 30 nanometers or less. As an example, a memory element using a split gate design may share only one source region or one; and a polar region along the same bit line. In other words, for some memory elements, the split gate SONONOS-NAND array may not use a diffusion region or junction (e.g., an N+ doped region). In one example, the design can also reduce or eliminate the need for shallow joints and adjacent "pockets", which in some cases can involve more complex processes. Moreover, in some examples, the design is less 681939-27U4 37 (S) 1298494 due to the short channel effect because the channel length has been increased, such as increasing to Lg = 2F-Ls in an example. Figure 32 shows an exemplary process for a memory array using a split gate design. This schematic is merely an exemplary example, and the memory array can be designed and fabricated in a variety of different ways. Referring to Fig. 32, after forming a multilayer material for providing a memory element, the layers may be patterned using a niobium oxide structure as a hard mask formed on the layers. For example, the yttrium oxide regions can be defined by lithography and etching processes. In one example, the pattern used to define the initial yttrium oxide region may have a width of about F and a space of about F of the yttrium oxide region, resulting in a distance of about 2F. After patterning the initial yttrium oxide region, a hafnium oxide spacer can then be formed to expand the respective hafnium oxide regions around the patterned regions and narrow the spacing thereof. Referring again to Figure 32, after forming the hafnium oxide region, it is used as a hard mask to define or pattern its underlying layer to provide one or more memory elements, such as a plurality of NAND strings. In addition, an insulating material such as hafnium oxide can be used to fill the space between adjacent memory elements, such as the space Ls shown in FIG. In one example, the space Ls between adjacent memory elements along the same bit line can range from about 15 nanometers to about 30 nanometers. As described above, in this example, the effective channel length can be expanded to 2F-Ls. In one example, if F is about 30 nm and Ls is about 15 nm, then Leff is about 45 nm. For the operation of these exemplary memory elements, the gate voltage can be reduced to less than 15V. In addition, the polysilicon voltage drop between the word lines can be designed to be no greater than 7V to avoid spacer collapse in the Ls space. In an example, this can be achieved by having an electric field of less than 5 MV/cm between adjacent word lines. 681939-27U4 38 1298494 Leff for the diffusion junction of a conventional NAND floating gate element is about half of its gate length. Conversely, in one example, if F is about nanometer and Leff is about 30 nanometers, Leff is about 8 nanometers of the proposed design (split gate NAND). Longer Leffs provide better component characteristics by reducing or eliminating the effects of short channel effects. As described above, the NAND design of the split gate can further reduce the space (Ls) between the adjacent cells of the same bit line. Conversely, the traditional type

The components of the two-way gate may not provide a small pitch, because the floating gates are lightly connected and the memory window may be lost. When the adjacent floating gate _ light and high electric solution is high, the floating gate is connected to the adjacent memory unit (the floating idle pole = the space is small, so that the coupling capacitance between adjacent floating gates is extremely high, Make the read interference happen). As noted above, the design eliminates the need to fabricate some of the diffusion junctions and to "JE" and if all of the word lines are turned on, the design can be _memory component (four). For example, the above includes structural design, array design, and memory element: (4), which can provide an array size that meets the requirements, excellent reliability, and energy or any combination thereof. Some of the examples described may also apply to the size of small non-volatile flash memory, such as ν Na faster than flash memory for data applications. Some examples provide S QN ΟΝ Ο S components for i ^ convergence channel hole erase. Good durability and reduced memory elements are difficult to erase or, as such, provide good component characteristics, such as how to maintain from the Ρ/Ε station. The components within the memory array can be provided without causing unstable bits or cells. Furthermore, 681939-27U4 39 1298494 = consumption can be provided well by split-closed NAND design, providing better sensing margins during memory component operation. (4) Pre-existing examples, examples; The present invention is disclosed. Variations of the embodiments are not to be construed as the details of the invention. The invention is not limited to the inventive concept. Therefore, decorated. The following is a description of the spirit and scope of the invention defined in the "Description", and the simplification of the schema in the scope of the invention. A better understanding of the drawings of the present invention is as follows: ::: and: r The purpose of the description of the invention is not limited to the arrangement, and the invention should be understood in the drawings: Rod i - * lb cutter is an N-channel according to an embodiment of the present invention. The cross-section of the p-channel memory unit according to an embodiment of the present invention is not intended; the long-term recording is based on the tunnel of the present invention. Graphical representation of the threshold voltage (charge trapping capacity) of the electrical structure under various methods; - the illustration of the SOONOS memory of the prior embodiment of the 7G L-limit voltage changing over time during erasing; 4 is a graphical representation of the threshold voltage of a SONONOS memory cell in accordance with the present invention as a function of time during a hold; 681939-27U4 1298494 electrical junctions in accordance with various embodiments of the present invention. N〇_ for the same-channel dielectric structure of the hole-through current phase type 1 mu invention - the memory unit of the specific embodiment is shown in various indications; the threshold voltage of the threshold voltage changes over time: No::: Ρί, a specific embodiment has a 峨亟-", a graphical representation of the threshold voltage between changes; the voltage = and 7d are the capacitance of the memory cell in _b relative to the electrical and the core - ring diagram (four) domain unit in a set of voltage limit diagrams; ° ^ / erasing cycle in the process of Figure 11 is a diagram of the threshold voltage change with time according to a specific implementation of the present invention The early 70 in % plus FIGS. 12a and 12b are respectively equivalent circuit diagrams and layouts of the virtual ground array according to the present invention, and FIG. 13 is a memory 681939-27U4 according to an embodiment of the present invention shown in FIG. 12b. 41 ί298494 A schematic cross-sectional view taken along line 12B-12B of a virtual ground array; unit FIGS. 14a and 14b are diagrams showing an equivalent circuit diagram of a memory: memory: array according to an embodiment of the invention, and A suitable reset/wipe of a specific embodiment Voltage; Turquoise diagram and 15b are equivalent circuit diagrams comprising a memory array according to an embodiment of the invention, which describes a program according to the present invention, 16a and 16b contain memory according to the invention - a specific embodiment An equivalent circuit diagram of a memory array, which is described in accordance with the method of the present invention; FIG. 18 is a diagram of a threshold voltage of a memory unit according to the present invention in various "belows"; A diagram of a threshold voltage of a memory cell in accordance with an embodiment of the present invention during a number of chemical/erase cycles; _ Figures 19a and 19b are memory cells in accordance with an embodiment of the present invention, in various gates Figure 2 is an equivalent circuit diagram of an array of memory cells in accordance with an embodiment of the present invention, the description of which is programmed according to the present invention. Figure 21a and Figure 21b are a layout diagram and an equivalent circuit diagram of a virtual ground array according to an embodiment of the present invention; Figures 22a and 22b are respectively based on the present invention. Equivalent circuit diagram and layout diagram of the NAND array of the memory unit of the embodiment; 681939-27U4 42 1298494 and FIGS. 23a and 23b are a memory NAND array according to an embodiment of the present invention along the line shown in FIG. 22b 22A_22a and 22b_22b are taken as a cross-sectional view; FIG. 24a is an equivalent circuit diagram of a NAND array according to an embodiment of the present invention, which describes an operation method according to the present invention; Period needle

FIG. 25 is an equivalent circuit diagram of a method of operation in accordance with an embodiment of the present invention; FIG. 26 is an embodiment of the present invention. FIG. 27 is an equivalent circuit diagram depicting a method of operation in accordance with an embodiment of the present invention; FIG. 28 is an illustration of an equivalent circuit diagram of a method of operation in accordance with an embodiment of the present invention; FIG. An illustration of the threshold voltage of a memory unit in a set, characterization, and erasing condition during a stylization/erasing cycle; _ Figures 29a and 29b are in accordance with the present invention: The current at the bottom of the tank is in three different cycles = not according to the logarithmic scale and the linear scale; according to the system - the specific real memory of the memory unit ^ different temperature and cycle conditions τ during the retention period FIG. 3 is a cross-sectional view of a line of NAND array characters 681939-27U4 43 1298494 in accordance with the present invention - and FIG. 32 is a NAND array character in accordance with an embodiment of the present invention. Line forming technology Schematic diagram of the section. 【 [Main component symbol description] 100 η channel memory unit 101 Ρ type substrate 102 Ν type doped region 104 η type doped region 106 channel region 120 tunnel dielectric structure 122 underlying thin oxide layer 124 small hole tunneling barrier high nitrogen Thin oxide layer 130 over layer 126 charge trapping/charge storage layer 140 insulating layer 150 gate 200 germanium channel memory cell 201 n-type substrate 202 p-doped region 204 germanium doped region 206 channel region 220 tunnel dielectric structure 222 Thin oxide layer 224 Small hole tunneling barrier High nitride layer 681939-27U4 1298494 226 Upper thin oxide layer 230 Charge trapping/charge storage layer 240 Insulation layer 250 Gate

681939-27U4 45

Claims (1)

F1298494 X. Patent Application Range: — 1. A memory unit comprising: a semiconductor substrate having a source region and a drain region disposed under a surface of the substrate and separated by a channel region; a dielectric structure disposed on the channel region, the tunnel-dielectric structure comprising at least one intermediate layer and two adjacent layers on opposite sides of the intermediate layer, wherein the intermediate layer and two adjacent layers are respectively The first material and the second material are included, wherein the second material has a valence band level greater than the φ first material valence band level, and the second material has a conduction band level less than the first a conduction energy band level of the material; and wherein the concentration of the second material is higher in the intermediate layer than in the two adjacent layers, and the concentration of the first material is higher in the two adjacent layers In the intermediate layer, the tunneling barrier height of the two adjacent layers is higher than the intermediate layer; a charge storage layer is disposed on the tunnel dielectric structure; and an insulating layer is disposed on the On the charge storage layer; and a gate electrode, Disposed on the insulating layer. # 2. The memory unit of claim 1, wherein the second material is present in the intermediate layer according to a gradient concentration such that the concentration of the second material in the intermediate layer increases from an adjacent layer/intermediate layer interface The maximum concentration at a deep point in the intermediate layer, and from the maximum concentration depth point to a lower concentration at the other adjacent layer/intermediate layer interface. 3. The memory unit of claim 1, wherein the first material comprises oxygen or an oxygenate. 4. The memory unit of claim 1, wherein the second material comprises nitrogen or a 681939-27U4 46 1298494 gas-containing compound. 5. The memory unit of claim 1, wherein the first material comprises cerium oxide. 6. The memory unit of claim 1, wherein the second material comprises tantalum nitride or hafnium oxynitride. 7. The memory unit of claim 1, wherein the first material comprises ruthenium oxide, and wherein the second material comprises tantalum nitride or ruthenium oxynitride. * 8. The memory unit of claim 1, wherein the charge storage layer comprises at least one material selected from the group consisting of tantalum nitride, Al2〇3, and Hf02. φ 9. The memory unit of claim 1, wherein the insulating layer comprises yttrium oxide. 10. The memory unit of claim 1, wherein the tunnel dielectric structure has a negligible trapping efficiency. 11. A memory array comprising a plurality of memory cells, such as claim 1. 12. A memory unit comprising: a semiconductor substrate having a source region and a non-polar region disposed under a surface of the substrate and separated by a channel region; • a tunnel dielectric structure Provided on the channel region, the tunnel dielectric structure includes at least one intermediate layer and two adjacent layers on opposite sides of the intermediate layer, wherein the two adjacent layers comprise a first material and the intermediate layer comprises a first The second material, wherein the second material has a valence band level greater than a valence band level of the first material, and the second material has a conduction band level that is less than a conduction band level of the first material; Wherein the second material is present in the intermediate layer according to a gradient concentration such that the concentration of the second material in the intermediate layer increases from an adjacent layer/intermediate layer interface to 681939-27 U4 47 1298494 The maximum concentration at a deep point in the intermediate layer, and decreasing from the deep point of the maximum concentration to a lower concentration at the interface of the other adjacent layer/intermediate layer, so that the holes of the two adjacent layers penetrate the tunnel a barrier height is higher than the intermediate layer; a charge storage layer disposed on the tunnel dielectric structure; an insulating layer disposed on the charge storage layer; and a gate electrode disposed on the On the insulation layer. • The memory unit of item 12, wherein at least two of the layers of the tunnel dielectric structure have a thickness of up to about 4 nanometers. = The memory unit of claim 12, wherein the tunnel dielectric structure comprises a 15 slice layer, a second yttrium oxide on the first lanthanum layer on the first zirconia layer on the first oxidized (four) Floor. Nitrogen "contains at least one material selected from the group consisting of 16 as claimed in claim 2. The memory unit of item 12, wherein the memory 17 is as negligible as the memory unit of requester 2." The channel dielectric structure has - -: a memory array 'which contains a plurality of memory sheets such as a request item. The memory array of item 18, wherein the at least two bridges leave -v? Yuanzhong L early 7C hunting is separated from a shallow ditch to isolate the middle to small separation - the insulation on the Shi Xizhi Xi Yiyi separated from each other. 20. The memory array of claim 18 has two words 彳 & s , ttt Y 屺 屺 体 array contains to ^ , 兀 line, at least two bit lines and to small 21 · as requested item eve ~ strip source line. '18 memory array, where the 咋k /, the memory array contains to 681939-27U4 48 1298494 kl?...丄14 then j ·, '•................. ...... · .V.. ... I,,..·..· j One less element selects the transistor, which is coupled to a corresponding bit line. 22. The memory array of claim 18, wherein the memory array comprises at least one source line select transistor coupled to a corresponding source line. 23. The memory array of claim 18, wherein the substrate comprises at least one pair of shallow junctions for the memory unit. 24. A method of forming a memory cell, comprising: * providing a semiconductor substrate having a source region and a non-polar region disposed under a surface of the substrate and separated by a channel region; Forming a tunnel dielectric structure on the channel region, wherein forming the tunnel dielectric structure includes forming at least two dielectric layers, wherein the at least two dielectric layers have a hole tunneling barrier height higher than the at least two dielectric layers Another layer; forming a charge storage layer on the associated dielectric structure; forming an insulating layer on the charge storage layer; and forming a gate electrode on the insulating layer. 25. The method of claim 24, wherein forming the tunnel dielectric structure comprises forming a first oxidized chopped layer, a first nitrided chopped layer, and a second oxidized chopped layer. 26. The method of claim 25, wherein the first ruthenium oxide layer, the first ruthenium ruthenium layer, and the second ruthenium oxide layer each have a thickness of from about 1 to about 3 nanometers. 27. The method of claim 24, wherein forming the tunnel dielectric structure comprises nitriding forming an oxide layer and a top surface of the oxide layer. 28. The method of claim 24, wherein forming the tunnel dielectric structure comprises sinking 681939-27U4 49 1298494 yttrium oxide and tantalum nitride such that tantalum nitride is present in the at least two dielectric layers in a layer having a high concentration Appearing in another layer of the at least two dielectric layers. 681939-27U4 50