Claims (1)
'1297575 • 工器能自其輸入端選擇一、组卿㈣以作為輸 出端之輸出，又該SHD選擇模組之輸出端係用以 5孔號連接至該AFE電路。 2.如申請專利範圍第1項所述之可調式CDS訊號電 路結構，其中該SHp選擇模組進一步包含一記憶 體，且該記憶體内存有一第一資料表，且該第一 =料表包含有至少一個該第一選擇訊號，又該記 ► 丨思體係用以被選擇的提供一該第一選擇訊號至該 第一暫存器。 3·如申請專利範圍第1項所述之可調式CDS訊號電 路結構，其中該SHD選擇模組進一步包含一記憶 體’且該記憶體内存有一第二資料表，且該第二 貝料表包含有至少一個該第二選擇訊號，又該記 _ 丨思體係用以被選擇的提供一該第二選擇訊號至該 第二暫存器。 4·如申請專利範圍第1項所述之可調式CDS訊號電 路結構，其中任兩個該SHP訊號間，均存在有N 個單位相位差t，又該單位相位差t為該數位取像 袭置其 CCD (Charge· Coup led Device)訊號時脈頻 率f的1/2N倍之倒數（t=i/〇.5*N*f)，其中該N 為大於等於一之整數。 26 1297575 5. 如申請專利範圍第1項所述之可調式CDS訊號電 路結構，其中任兩個該SHD訊號間，均存在有N 個單位相位差t，又該單位相位差t為該數位取像 裝置其CCD訊號時脈頻率f的1/2N倍之倒數 (t=l/0.5*N*f)，其中該N為大於等於一之整數。 6. 如申請專利範圍第1項所述之可調式CDS訊號電 路結構，其中該DCM模組、該SHP選擇模組， 以及該SHD選擇模組係由硬體描述語言（VHDL， Very high speed integrated circuit Hardware Description Language)方式戶斤達成。 7. 一種數位取像裝置之 CDS(Correlated Doubling Sampler )訊號選擇方法，係應用於一數位取像裝 置之 FPGA(Field Programmable Gate Arrays)電路 中，其包括下列步驟： 擷取一物件影像，係以該數位取像裝置之取 像鏡頭擷取之，並將該物件影像轉換成一類比影 像訊號； 提供一可Μ組選一之SHP訊號及一可Μ組 選一之SHD訊號，其中該Μ為大於一之整數； 選出一組該SHP訊號，係藉由一第一選擇訊 號自該些SHP訊號中選擇之，選出一組該SHD 27 1297575 訊號，係藉由一第二選擇訊號自該些SHD訊號中 號選擇之’又令該選擇後之SHP訊號及SHD訊 號作用於一 AFE(Analog Front End)電路中，對該 類比影像訊號進行取樣以得到-數位影像訊號I 檢視該數位影像訊號是否為合格； 若合格則固定該組SHP及該組SHD訊號， 並完成該組SHP及該組SHD訊號之選擇；以及 選擇另一組該SHP及該SHD訊號，當該數 位影像訊號經檢視為非合格時。 8·如申請專利範圍第7項所述之CDS訊號選擇方 法，其中任兩個該SHp訊號間，均存在有n個單 位相位差t ’又該單位相位差t為該數位取像裝置 其 CCD(Charge_Coupled Device)訊號時脈頻率 f 的1/2^[倍之倒數〇=1/05；^*〇，其中該1^為大 於等於一之整數。 9·如申請專利範圍第7項所述之CDS訊號選擇方 法’其中任兩個該SHD訊號間’均存在有N個 單位相位差t，又該單位相位差t為該數位取像裝 置其CCD訊號時脈頻率f的i/2n倍之倒數 (卜l/〇.5*N*f)，其中該N為大於等於一之整數。 10·如申請專利範圍第7項所述之CDS訊號選擇方 28 1297575 法，其中該些SHP訊號及該些SHD訊號係藉由 一 DCM (Digital Clock Manager)模組加以產生 者。 11·如申請專利範圍第7項所述之CDS訊號選擇方 法，其中該SHP訊號係藉由一 SHP選擇模組加以 選擇之。 12·如申請專利範圍第7項所述之CDS訊號選擇方 法，其中該SHD訊號係藉由一 SHD選擇模組加 以選擇之。 13·如申請專利範圍第7項所述之CDS訊號選擇方 法，其中該第一選擇訊號係選自於一第一資料 表’该苐一 > 料表紀錄有至少一個該第一選擇訊 14·如申請專利範圍第13項所述之CDS訊號選擇方 法，其中該第一選擇訊號係儲存於一第一暫存器。 15·如申請專利範圍第13項所述之CDS訊號選擇方 法，其中該第一資料表係儲存於一記憶體。 16·如申請專利範圍第7項所述之CDS訊號選擇方 法，其中該第二選擇訊號係選自於一第二資料 表，該第二資料表紀錄有至少一個該第二選擇訊 號0 29 1297575 7·如申凊專利範圍第16項所述之Cds訊號選擇方 法，其中該第二選擇訊號係儲存於一第二暫存器。 1 8·如申請專利範圍第16項所述之cds訊號選擇方 法’其中該第二資料表係儲存於一記憶體。 19·如申請專利範圍第7項所述之CDS訊號選擇方 法’其中該數位影像訊號檢視之方法，係將該數 位影像訊號轉換成一第一灰階值，接著將該第一 灰階與一標準灰階值進行對照而檢視之。'1297575 • The tool can select one of the inputs from the input terminal (4) as the output of the output, and the output of the SHD selection module is connected to the AFE circuit with a 5-hole number. 2. The adjustable CDS signal circuit structure according to claim 1, wherein the SHp selection module further comprises a memory, and the memory has a first data table, and the first material table includes There is at least one first selection signal, and the recording system is configured to provide a first selection signal to the first temporary register. 3. The adjustable CDS signal circuit structure of claim 1, wherein the SHD selection module further comprises a memory and the memory has a second data table, and the second material table comprises There is at least one second selection signal, and the recording system is configured to provide a second selection signal to the second temporary register. 4. If the adjustable CDS signal circuit structure described in claim 1 is claimed, wherein there are N unit phase differences t between any two of the SHP signals, and the unit phase difference t is the digital image. The CCD (Charge Coup led Device) signal is reciprocal of 1/2N times the clock frequency f (t=i/〇.5*N*f), where N is an integer greater than or equal to one. 26 1297575 5. The adjustable CDS signal circuit structure according to claim 1, wherein any two of the SHD signals have N unit phase differences t, and the unit phase difference t is the number Like the reciprocal of the 1/2N times the clock frequency f of the CCD signal of the device (t=l/0.5*N*f), where N is an integer greater than or equal to one. 6. The adjustable CDS signal circuit structure of claim 1, wherein the DCM module, the SHP selection module, and the SHD selection module are hardware description languages (VHDL, Very high speed integrated). Circuit Hardware Description Language) A CDS (Correlated Doubling Sampler) signal selection method for a digital image capture device is applied to an FPGA (Field Programmable Gate Arrays) circuit, which comprises the following steps: capturing an image of an object, The image capturing device of the digital image capturing device captures the image and converts the image of the object into an analog image signal; and provides a SHP signal and a SHD signal selected by the group, wherein the image is greater than An integer of one selected from the SHP signals by a first selection signal to select a set of the SHD 27 1297575 signals from the SHD signals by a second selection signal The medium selection selects the selected SHP signal and the SHD signal to be applied to an AFE (Analog Front End) circuit, and samples the analog video signal to obtain a digital video signal I to check whether the digital video signal is qualified. If qualified, fix the set of SHP and the set of SHD signals, and complete the selection of the set of SHP and the set of SHD signals; and select another set of the SHP and the SHD signal, when the number When the image signal is deemed to be unqualified. 8. The method for selecting a CDS signal according to item 7 of the patent application scope, wherein any two of the SHp signals have n unit phase differences t′ and the unit phase difference t is the CCD of the digital image capturing device. (Charge_Coupled Device) The signal clock frequency f is 1/2^[time reciprocal 〇=1/05; ^*〇, where 1^ is an integer greater than or equal to one. 9. The method for selecting a CDS signal according to item 7 of the patent application scope, wherein there are N unit phase differences t between any two of the SHD signals, and the unit phase difference t is the CCD of the digital image capturing device. The reciprocal of the i/2n times of the signal clock frequency f (Bu l/〇.5*N*f), where N is an integer greater than or equal to one. 10. The method of the CDS signal selection party 28 1297575, as described in claim 7, wherein the SHP signals and the SHD signals are generated by a DCM (Digital Clock Manager) module. 11. The method of selecting a CDS signal as described in claim 7 wherein the SHP signal is selected by an SHP selection module. 12. The method of selecting a CDS signal as described in claim 7 wherein the SHD signal is selected by an SHD selection module. 13. The method for selecting a CDS signal according to claim 7, wherein the first selection signal is selected from a first data table, the first data sheet, and the material table records at least one of the first selection messages. The method for selecting a CDS signal according to claim 13, wherein the first selection signal is stored in a first register. 15. The method of selecting a CDS signal as described in claim 13 wherein the first data sheet is stored in a memory. The method of selecting a CDS signal according to claim 7, wherein the second selection signal is selected from a second data table, and the second data table records at least one second selection signal 0 29 1297575 7. The Cds signal selection method according to claim 16, wherein the second selection signal is stored in a second register. 18. The cds signal selection method described in claim 16 wherein the second data sheet is stored in a memory. 19. The method for selecting a CDS signal according to claim 7 of the patent application, wherein the method for viewing the digital image signal converts the digital image signal into a first grayscale value, and then the first grayscale and a standard The grayscale values are compared for comparison.