1297524 九、發明說明： 【發明所屬之技術領域】 造方法，特別是關 各結構及其製造方 本發明係關於一種可變電容結構以及其製 於一種具有南品質因數及較佳線性度的可變電 法0 【先前技術】 f 树代化資訊產業巾，各種數據、資料、訊息、影像等 以電子訊號的形式來傳遞，而用來處理電子訊號的處理電路，^ 就成為現代資訊產業中最重要的基礎。而電路中之震盛哭 (osdllator)則是現代數位系統中不可或缺的重要電路構築雜之 一。例如’在一般的資訊系統(例如：個人電腦)中，需要一總體時 脈(global clock)以協調數位系統中的各個數位電路一起運作γ而時 脈則是由震盛器所產生的。此外，要協調不同的時脈同步(譬如說 在傳輸訊號的通訊祕巾），還需要使财貞相(phase loop loek; PLL) 電路；而鎖相電路中則需要精密的壓控紐器(v〇ltage_c〇ntr〇脇 oscillators ;VCOs)，以電壓來控制壓控震盪器震盪出頻率不同的震 盈訊號，以協調各時脈同步。此外，像是在某些精密的濾波器中， 尚須使用能調整濾波頻率的電阻-電容(RC)濾波器。 然而，不論是電阻-電容(RC)濾波器的濾波特性(像是濾波器的 通帶頻寬），或是電感-電容(LC)壓控震盪器的震盡特性(像是震盪 訊號的頻率）’都可以用改變電容值的方法來加以調整。因此，具 1297524 有可H值之電容’亦即可變電容，已被運用於具有該些特 f生之元件中。而在可變電容之操作範圍内，其電容值係隨加諸其 上之電Μ(控制)而減少。目前已發展出多種可應用於積體電路 元件中之可變電容，而其中αΡΝ接面可變電容(ρΝ_ΰ〇η varactor)以及金氧半導體(metai 〇xide semic〇論倉，腿s)可變電 容兩種結構最常為常見。 無淪是PN接面可變電容或者M〇s可變電容，其設計一般皆 以付&以下1¾項要求為目標：高單位電容㈣心啊咖腦）、高調 譜比值(tuningmtio)、在其操作範圍内之高線性度、以及高品質因 數(quality factor，Q)。高單位電容係指在單位電壓的作用下，單位 面積之電容可儲存較高的電荷。調諧比值則是定義為最大電容和 最小電容的差值比上最小電容值((Cmax_Cmin)/Cmin)。線性度職 作電壓和電容值關係的線性程度。而品質因數值)則與電阻有 關，阻值越小，則Q值越高。然而，在現實上難以同時針對以上 各項目標最佳化。 例如’對PN接面施以逆向偏壓時，可使pn接面可變電容具 有較佳的Q值，然而此種可變電容的調諧比值較小，一般在3〇% 左右’而線寬〇·15微米（//m)的PN接面可變電容的調諧比值更 小’可能小於20%。相反的，一累積模式(accumuiati〇nm〇de)的 M0S可變電容具有較大的調諧比值。然而其線性度較差，亦即小 幅度改變提供於其上之控制電壓，將使壓控震盪器之頻率劇烈改 1297524 變’此項特性使MOS可變電容在操作上較為不便 。是以在應用 上，往往需與其他電容麵，以達到較佳的線性表現。且M〇s可 變電谷的(3錄低’是以，儘管其具雜大_諧比值，仍無法 完全符合使用上的需求。 因此，而要-種同時具有較佳Q值、良好線性度且適當繼 比值的可變電容，以符合目前產業上的需求。 【發明内容】 本發明提供-種可㈣容結構及其製造方法，該可變電容結 構具有較高之Q值及較佳之線性度。 根據本發明之帽細，該方法首先係提供—基底。該基底 其具有-第-導電型離子井’以及複數個隔離結構設於該第一導 電1離4·井周圍。接著’於該基底表面之第一導電型離子井上方 形成-閘極結構，以作為可變電容結構之第一電極。隨後對該基 底表面進仃-第一濃度之離子佈植，以形成兩個第一’導電型高摻 雜區域。其中該第一導電型高摻雜區域中之摻雜物在經過一熱製 程後棘閉極結構下方擴散，甚至互相接觸而形成相連之摻雜區 域三接，於_結構外侧形成—侧壁子結構。最後對該基底表面 進仃-第二濃度之離子佈植，以形成第—導電型電極摻雜區域， 以作為可變電容結構之第二電極。 1297524 【實施方式】 請參見第1圖至第3圖，第— 方法製造-可魏容輯3G. 5 ®齡減本發明之 的貝鉍例。首先請參照第1圖，第1 祕Μ本發狄可變電容賴3G的轉縣底10。半導 體基底10包含有複數個隔離結構12、- N型深離子井14，以及 一 pf離子井16，其中隔離結構U可為-淺溝隔離結構(福low Γ ，STI)°然而’根據本發明之方法，半導體基底Η) 二可具有其他賴’例如，铸縣底ig可為—Ν型基底，則此 時即無須於半導體基底1G上再形成—N型深離子井Μ,而可直 接於其上形成—p麵子井16。且可在_結構⑽成後方進行 離子摻雜娜雜子井14、16，村於離子井Μ、Μ完成後，方 於半導體基底10表面形成隔離結構12。 接著，如第2圖所示，於上述？ _子井16上方形成一間極 …構18 ’以作為可變電容結構3()之第—電極。並對半導體基底 ίο表面進行一低濃度之離子佈植，以於閘極結構18兩侧下方之p 型離子井16巾分卿成兩p叙婦域师t如細 reg1〇_。接著辭導體基底1G表面進行—高濃度之離子佈植， 以於閘極結構18兩侧下方之P型離子井16中分別形成兩p型的 冋摻雜區域22。請繼續參照第3圖，接著進行—熱製程，使兩p 型南掺雜區域22中之離子往閘極結構18下方區域擴散，其中於 本實施例中兩P型高摻雜區域22於熱製程後係相互接觸而形成一 相連之摻雜區域。在完成P型高摻雜區域的離子佈植後，於閘極 1297524 結構18兩侧形成侧壁子(spacer)結構24。接著對基底1〇表面進行 離子佈植’以於兩P _高摻雜區域22中分卿成兩p型之電極 摻雜區域26 ’以作為可變電容結構3〇之第二電極。其中p型高摻 雜區域22’以及電極摻雜區域％的離子佈植濃度皆高於p型之低 摻雜區域20的離子佈植濃度。相較於習知之可變電容結構製造方 法’本發明增加了 一道高濃度離子佈植，能有效改善電容之特性， 增加其Q值以及線性度。 清參見第4圖至第6 ®，第4圖至第6圖顯示另-根據本發 明之方法製造一可變電容結構之實施例。如第4圖所示，可在第i 圖之半導體基底10上形成-閘極結構18後，先對半導體基底1〇 表面進行一低濃度之離子佈植，以於閘極結構18兩側下方之p型 離子井16中为別形成兩p型之低換雜區域2〇。接著於閘極結構 Μ之兩侧形成一侧壁子結構24。其後，如第5圖所示，於侧壁子 、、口構24與半^r體基底1〇接觸處以一傾斜方向28對半導體基底1〇 表面進行離子佈植，以於閘極結構18兩侧下方之p型離子井16 申分別形成兩P型高摻雜區域22。並進行一熱製程以軀入p型高 摻雜區域22之離子。最後，如第6圖所示，對基底1〇表面進行 離子佈植，以於兩P型高摻雜區域22中分別形成兩p型之電極摻 雜區域26以作為可變電容結構3〇之第二電極。其中p型高摻雜 區域22，以及電極摻雜區域26的離子佈植濃度皆高於p型之低摻 雜區域20的離子佈植濃度。此外，由於兩P型高摻雜區域22係 朝向閘極結構18下方之方向佈植，因此兩p型高摻雜區域U較 1297524 兩電極摻雜區域26更為靠近，並可能如第6圖所示般互相連接。 然而本發明之方法並未侷限於此，如第7圖所示，兩 區似亦可不相互接觸。此外，亦可依製程的需要，省略側壁子 結槿24 〇 ▲如第3 ®、第6圖、與第7圖所示，根據本發明所製造出之 可變電容結構30抑知可魏容結财補之處。幢本發明之 可變電容結構3G多了—道高濃度之離子佈植，因此多了兩個互相 分離或連接之高摻雜區域22。然:而，高掺雜區域Μ亦可能於閉極 結構18外圍互相連接’因而僅呈現單一個高捧雜區域π。無論如 ^，由於此高摻_域22的存在，本發啊大财善習知可變電 容結構在Q值及線性度等性質尚無法突破的問題。 〇月多見第8圖’如其所示’在未與其他電容並聯的情況下， 本月之方法所衣造之可變電容結構在施加_1至5伏特電壓的範 圍内已有極為線性的c_v曲線。此外，其繼比值亦趨近於46%， 此已$以應付實際麵上的需要。而第9 _顯示—根據本發明 之新可變電容結構與-習知可變電容結構之Q值 二/、中此新可艾電容結構之電容值約為彻飛法拉㈣，而 此習知可變電容結構之電容值則約為400飛法拉，亦即兩者電容 、不大彳新可變電容結構之q值卻將近是習知電容〇值的 兩么亦即根據本發明所製造出之電容具有較習知電容為佳之^ 值表現此外印參照第1〇圖，根據本發明之方法所製造出之可 1297524 變電容結構，細__福電量倾10歧培(pA)。換言 之本發明之可變電容結構具有相當之可實施性。 必須說明的是’除了上述實補之外，兩高摻_域22亦可 依實際需求以N型離子進行摻雜，此時_子井14為―p型深 子井，而離子井10則為一 N型之離子井。同樣地，當兩高換雜 域，為N型高摻雜區域時，亦可以一 p型半導體基底進行此可變 電容結構30之製造，此時可省略深離子井14之製輕，而逕行= 3L離子井16之離子驗。此外，由於高摻祕域敕、 低摻雜區域20 ’因此歸祕域將無法轉低摻雜濃度，:個 毛月之可變電各結構仍可具有優良之電性表現。換言之 本 區域20的存在與否並不影響可變電容轉之紐二二_雜 選擇性地略絲成低雜區域20之抛。 疋以’可 Μ上所述僅為本發明之較佳實施例，凡依本發 圍所做之均等變化與修飾，皆應私發明之涵蓋範園。利範 11 1297524 【圖式簡單說明】 弟1〜3圖係為根據本發明製造一可變電容結構之方法辛囷 第4〜7圖係為根據本發明製造一可變電容結構之方法示二^。 弟8圖係為本發明之可變電容結構的電容_電壓示专囷 ° 第9圖係為本發明之可變電容結構與習知可變電容結構之q值比 較圖。 第10圖係為本發明之可變電容結構在不同操作電壓下之漏電量示 意圖。 22 ρ型局推雜區域 24 侧壁子結構 26 電極捧雜區域 28 離子佈植方向 30 可變電容結構 【主要元件符號說明】 10半導體基底 12 隔離結構 14 Ν型深離子井 16 Ρ型離子井 18 閘極結構 ⑩ 20 Ρ型低摻雜區域 121297524 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a variable capacitance structure and a method for producing a south quality factor and a better linearity. Substation method 0 [Prior technology] f-treeized information industry towel, various data, data, information, images, etc. are transmitted in the form of electronic signals, and the processing circuit for processing electronic signals becomes a modern information industry. The most important foundation. The osdllator in the circuit is one of the most important circuits in modern digital systems. For example, in a general information system (e.g., a personal computer), a global clock is required to coordinate the various digital circuits in the digital system to operate γ while the clock is generated by the oscillator. In addition, to coordinate different clock synchronization (such as the communication secrets of the transmission signal), it is also necessary to make a phase loop loek (PLL) circuit; in the phase-locked circuit, a precision voltage controller is required ( V〇ltage_c〇ntr threat oscillators; VCOs), by voltage to control the pressure oscillation oscillator to oscillate different frequency signals to coordinate the synchronization of each clock. In addition, as in some sophisticated filters, a resistor-capacitor (RC) filter that adjusts the filter frequency is required. However, whether it is the filter characteristics of a resistor-capacitor (RC) filter (such as the passband bandwidth of a filter), or the inductive-capacitor (LC) voltage-controlled oscillator's shock characteristics (such as the frequency of a oscillating signal) ) ' can be adjusted by changing the value of the capacitor. Therefore, a capacitor having an H value of 1297524 can also be used for variable capacitance, and has been used in components having such characteristics. In the operating range of the variable capacitor, the capacitance value decreases with the power (control) applied to it. At present, a variety of variable capacitors have been developed which can be applied to integrated circuit components, wherein the αΡΝ junction variable capacitance (ρΝ_ΰ〇η varactor) and the MOS semiconductor (metai idexide semic 仓 ,, leg s) are variable. Two structures of capacitance are most common. Innocent is a PN junction variable capacitor or M〇s variable capacitor. Its design is generally targeted at the following 13⁄4 requirements: high unit capacitance (four), high-profile ratio (tuningmtio), High linearity within its operating range, and high quality factor (Q). High unit capacitance means that the capacitance per unit area can store a higher charge under the action of a unit voltage. The tuning ratio is defined as the difference between the maximum capacitance and the minimum capacitance ((Cmax_Cmin)/Cmin). Linearity The linearity of the relationship between voltage and capacitance values. The quality factor value is related to the resistance. The smaller the resistance, the higher the Q value. However, it is difficult to optimize both of the above objectives in reality. For example, when the reverse bias is applied to the PN junction, the variable capacitance of the pn junction can be made to have a better Q value. However, the tuning ratio of the variable capacitor is small, generally about 3〇%, and the line width is调谐·15 μm (//m) PN junction variable capacitance tuning ratio is smaller 'may be less than 20%. Conversely, a cumulative mode (accumuiati〇nm〇de) M0S variable capacitor has a large tuning ratio. However, its linearity is poor, that is, a small change in the control voltage supplied thereto will cause the frequency of the voltage-controlled oscillator to be drastically changed. 1297524 Change this feature makes the MOS variable capacitor inconvenient to operate. Therefore, in application, it is often necessary to use other capacitive surfaces to achieve better linear performance. And M〇s variable electric valley (3 recording low' is, although it has a large _ harmonic ratio, it still can not fully meet the requirements of use. Therefore, the kind has a better Q value and good linearity. The variable capacitance of the appropriate ratio is suitable to meet the needs of the current industry. SUMMARY OF THE INVENTION The present invention provides a (four) capacity structure and a manufacturing method thereof, the variable capacitance structure having a high Q value and preferably Linearity. According to the cap of the present invention, the method first provides a substrate. The substrate has a -first conductivity type ion well and a plurality of isolation structures are disposed around the first conductive 1 and 4 wells. Forming a gate structure over the first conductivity type ion well on the surface of the substrate to serve as a first electrode of the variable capacitance structure. Then, the surface of the substrate is implanted with a first concentration of ions to form two a 'conducting type highly doped region, wherein the dopants in the first conductive type highly doped region diffuse under the spinous closed-pole structure after a thermal process, and even contact each other to form a connected doped region three-way, Formed on the outside of the _ structure The sidewall substructure is finally implanted with a second concentration of ions on the surface of the substrate to form a first conductive type electrode doped region as a second electrode of the variable capacitance structure. 1297524 [Embodiment] Fig. 1 to Fig. 3, the first method to manufacture - Wei Wei series 3G. 5 ® age minus the shellfish example of the invention. First, please refer to Fig. 1, the first secret of the present invention, the variable capacitance capacitor 3G The semiconductor substrate 10 includes a plurality of isolation structures 12, an N-type deep ion well 14, and a pf ion well 16, wherein the isolation structure U can be a shallow trench isolation structure (Folow Γ, STI). However, 'the method according to the present invention, the semiconductor substrate Η) can have other advantages. For example, the ICP can be a Ν-type substrate, and then it is not necessary to form on the semiconductor substrate 1G - the N-type deep ion well Μ, and the p-face well 16 can be formed directly thereon. The ion doping wells 14, 16 can be performed behind the _ structure (10). After the ion wells and ruthenium are completed, the isolation structure 12 is formed on the surface of the semiconductor substrate 10. Next, as shown in Figure 2, above? A pole 18 is formed above the sub-well 16 as the first electrode of the variable capacitor structure 3(). A low-concentration ion implantation is performed on the surface of the semiconductor substrate ί, so that the p-type ion well below the two sides of the gate structure 18 is divided into two groups, such as fine reg1〇_. Next, the surface of the conductor substrate 1G is subjected to high-concentration ion implantation to form two p-type germanium-doped regions 22 in the P-type ion wells 16 below the gate structures 18, respectively. Continuing to refer to FIG. 3, a thermal process is then performed to diffuse ions in the two p-type south doped regions 22 toward the lower region of the gate structure 18. In the present embodiment, the two P-type highly doped regions 22 are hot. The processes are in contact with each other to form a connected doped region. After the ion implantation of the P-type highly doped region is completed, a spacer structure 24 is formed on both sides of the gate 1297524 structure 18. Next, the surface of the substrate 1 is ion implanted to divide the two P-type electrode doped regions 26' into the two P-high doped regions 22 to serve as the second electrode of the variable capacitance structure 3A. The ion implantation concentration of the p-type highly doped region 22' and the electrode doped region % is higher than the ion implantation concentration of the p-type low doped region 20. Compared with the conventional method for manufacturing a variable capacitance structure, the present invention adds a high concentration ion implantation, which can effectively improve the characteristics of the capacitor, increase its Q value and linearity. See Figures 4 through 6®, and Figures 4 through 6 show another embodiment of manufacturing a variable capacitance structure in accordance with the method of the present invention. As shown in FIG. 4, after the gate structure 18 is formed on the semiconductor substrate 10 of the first embodiment, a low concentration ion implantation is performed on the surface of the semiconductor substrate 1 to be below the both sides of the gate structure 18. In the p-type ion well 16, a low-interval region 2〇 of two p-types is formed. A sidewall substructure 24 is then formed on both sides of the gate structure. Thereafter, as shown in FIG. 5, the surface of the semiconductor substrate 1 is ion-implanted in an oblique direction at the side of the sidewall, the interface 24, and the half of the substrate, so that the gate structure 18 is formed. The p-type ion wells 16 below the two sides form two P-type highly doped regions 22, respectively. A thermal process is performed to implant ions into the p-type highly doped region 22. Finally, as shown in FIG. 6, ion implantation is performed on the surface of the substrate 1 to form two p-type electrode doping regions 26 in the two P-type highly doped regions 22 as variable capacitance structures. Second electrode. The ion implantation concentration of the p-type highly doped region 22 and the electrode doped region 26 is higher than the ion implantation concentration of the p-doped low doped region 20. In addition, since the two P-type highly doped regions 22 are implanted in the direction below the gate structure 18, the two p-type highly doped regions U are closer to the 1297524 two-electrode doped regions 26, and may be as shown in FIG. Connected as shown. However, the method of the present invention is not limited thereto, and as shown in Fig. 7, the two regions may or may not be in contact with each other. In addition, the sidewall spacers 24 can be omitted according to the needs of the process. As shown in the third, sixth, and seventh figures, the variable capacitor structure 30 manufactured according to the present invention can be suppressed. Make up for money. The variable capacitance structure 3G of the present invention has a high concentration of ion implantation, thereby adding two highly doped regions 22 which are separated or connected to each other. However, the highly doped regions Μ may also be interconnected at the periphery of the closed-pole structure 18 and thus exhibit only a single high-doping region π. Regardless of ^, due to the existence of this highly-blended _ domain 22, the problem of the Q-value and linearity of the variable-capacitor structure is still unbreakable. In the month of the month, see Figure 8 'as shown.' In the case of not being connected in parallel with other capacitors, the variable capacitor structure made by this month's method has been extremely linear in the range of _1 to 5 volts applied. C_v curve. In addition, its success ratio has also approached 46%, which has been met to meet the needs of the actual surface. And the ninth _ display - the new variable capacitance structure according to the present invention and the conventional variable capacitance structure Q value two /, the capacitance value of the new acryl capacitance structure is about Cheby Farah (four), and this conventional The capacitance value of the variable capacitor structure is about 400 femtofarads, that is, the q values of the two capacitors and the new variable capacitor structure are close to those of the conventional capacitors, that is, according to the present invention. The capacitor has a better value than the conventional capacitor. Referring to the first drawing, the 1297524 variable capacitor structure manufactured by the method of the present invention has a fine structure of 10 deg. In other words, the variable capacitance structure of the present invention has considerable implementability. It must be stated that 'in addition to the above-mentioned actual compensation, the two highly doped domains 22 can also be doped with N-type ions according to actual needs. At this time, the sub-well 14 is a p-type deep well, while the ion well 10 is It is an N-type ion well. Similarly, when the two high-switching domains are N-type highly doped regions, the fabrication of the variable capacitor structure 30 can also be performed on a p-type semiconductor substrate. In this case, the deep ion well 14 can be omitted, and the path can be omitted. = 3L ion well 16 ion test. In addition, due to the high doping of the domain, the low doped region 20 ′ will therefore be unable to turn down the doping concentration, and the variable electrical structures of the hairy month can still have excellent electrical performance. In other words, the presence or absence of the region 20 does not affect the conversion of the variable capacitance to the new impurity region. The present invention is only a preferred embodiment of the present invention, and all changes and modifications made in accordance with the present invention should be covered by the invention. Lifan 11 1297524 [Simple description of the drawing] The brothers 1 to 3 are a method for manufacturing a variable capacitance structure according to the present invention. The fourth to seventh drawings are a method for manufacturing a variable capacitance structure according to the present invention. . The figure 8 is the capacitance of the variable capacitance structure of the present invention. The voltage diagram of the variable capacitance structure of the present invention is a comparison of the q value of the variable capacitance structure of the present invention and the conventional variable capacitance structure. Figure 10 is a schematic illustration of the leakage current of the variable capacitance structure of the present invention at different operating voltages. 22 ρ-type interfering region 24 sidewall substructure 26 electrode holding region 28 ion implantation direction 30 variable capacitance structure [main component symbol description] 10 semiconductor substrate 12 isolation structure 14 深 type deep ion well 16 Ρ type ion well 18 gate structure 10 20 Ρ type low doped area 12