TWI297501B - Method and apparatus for determining sensing timing of flash memory - Google Patents

Description

1297501 IX. Description of the invention: [Technical field to which the invention pertains]

The present invention relates to a method for determining a sensing time and a device for performing the method, and more particularly to a page buffer (page buffer) which can be determined in a memory cell array of a flash memory component. A method of sensing time and a device for performing the method. The sensing time determines the triggering of the control signal to initiate a read and verify operation in the flash memory component. [Prior Art] In a NAND type flash memory, data stored in a memory cell is read via a one-page buffer. This page buffer is also used for program verification and erase verification with similar functions to read verification. This page buffer has many different aspects of design. 1 is a design aspect of a conventional page buffer, which is published in "A 3·3 V 32 Mb NAND flash memory with incremental step pulse programming scheme" (IEEE Journal of Solid-State-Circuit, Vol. 30). , No. 11, p. 1149-1155, November 1995). Its read operation is described below. First, a word line (not shown) is switched to a low level so that no current occurs in the memory cell. Thereafter, the bit line BL is grounded by turning on the NMOSs 102 and 103. Next, the bit line BL is turned to vcc by turning off the NMOSs 1 and 3 and turning on the PMOS 101. The page buffer uses a mirrored current provided by PMOS 101 to boost the potential of bit line BL. The mirror current 104986.doc -6 -

E39981 104986 005192358-1 1297501 is used to define the potential of the bit line BL as compared to the current flowing through an accessed cell (not shown). If the accessed cell is at a low threshold voltage, meaning to be in an erase state, it will be turned on by the word line and will have a ratio during read and verify operations. The mirror shoots a larger current. Therefore, the bit line BL will gradually discharge and the NMOS 105 will be turned off. If the accessed cell is at a high threshold voltage, meaning that it is in a program state, the potential of the word line will not be able to turn on the accessed cell. Therefore, the mirror current boosts the bit line BL to a high level state to turn on the NMOS 105. After a certain period of time (ie, signal development time), the state of the accessed cell will be transmitted to one of the page buffers by triggering a 'READ" pulse signal and The NMOS 106 is turned on. Therefore, the data stored in the accessed cell will be transferred to the page buffer. In U.S. Patent No. 1,6,671,204, the current mirror mode of Figure 1 is discarded and the buffer line of Figure 2 is used. When the bit line BLE is selected for reading, another bit line BLE is used as a shielding bit line. FIG. 3 is a timing diagram of each signal in FIG. 2. In the region 2, first, the bit lines BLE and BLO are grounded and discharged by turning on the NMOSs 201 and 203, wherein the signal VIRPWR is grounded. At this time, the node SO is also discharged by turning on the NMOSs 202 and 204. After entering zone 3, signal BLSHFO switches to a low level, word line WL is gradually boosted to a high level and signal BLSHFE is biased to 2.0V and signal PLOAD drops to a low level. At this point node SO is boosted to Vce and the bit line BLE is charged to (2.0V-Vth), where Vth is the threshold voltage of NMOS 204 and is typically 1.0V. The 2.0V bias voltage and the threshold of the NMOS 204 (S E39981 104986 005192358-1 104986.doc -7· 1297501 voltage will clamp the potential of the bit line BLE. When the potential of the bit line BLE is stabilized, it enters Area 4. In area 4, signal BLSHFE is pulled to grounded to turn off NMOS 204. In other words, the signal on bit line BLE begins to develop. If the cell is accessed with a low threshold voltage and is When turned on, the bit line BLE will be discharged to a lower potential. Conversely, if the accessed cell has a high threshold voltage, it will not be turned on and the bit line BLE will remain at the precharge potential (pre- Charge voltage) 进入 After the signal development time (ie, region 4), enter region 5. Here, NMOS 204 is turned on again, but the potential of signal BLSHFE is only 1.3V. If bit line BLE is at low level (NMOS 204 Turned on, the node SO with the Vee level will be discharged to the bit line BLE. However, if the bit line BLE is at 1.0V or the accessed cell has a high threshold voltage, the node SO will remain at the Vec level. And the NMOS 204 is turned off. Then by triggering a pulse PBLCHM, the node SO The state will be sent to a register 205. In this prior art, a timer is required to trigger the pulse PBLCHM. The timer will calculate a predetermined time to ensure that the signal PLOAD has been switched to high in region 4. Then, in region 6, all of the bit lines and nodes SO will be grounded again. All control signals will be disabled in area 7. US Patent No. 6,925,005 discloses a sensing method for tracking. The memory cell is located in the direction of the bit line and the direction of the word line. The memory cell array is divided into a plurality of blocks. Each region has a reference bit line for controlling the sensing time of the region. The reference bit line is Each intersecting word line has a reference cell, meaning that all reference bit lines have the same connection as the normal bit line. However, this design will be 104986.doc - 8 -

E39981 104986 005192358-1 1297501 makes it impossible to adjust the threshold voltage of the reference cell. Another consideration is the problem of drift and disturbance of the reference threshold voltage, which is caused by the immediately adjacent normal bit line and the reference bit line. That is, when a normal cell is written, the corresponding word line is raised to a high level to affect the threshold voltage of the reference cell. Similarly, the threshold voltage drift of the reference cell also occurs in the erase operation. In another conventional technique, U.S. Patent No. 6,304,486 uses a signal reference bit line and a plurality of reference cells. Each of the reference cell lines is located at an intersection of the signal reference bit line and the plurality of word lines. It means that each page has a reference cell. When the reference cell is verified by erasing, the normal cell erase verification is initiated. In addition, when the reference cell passes the write verification, the normal cell write verification will be initiated. However, if one of the reference cells fails, its corresponding word line will not be able to access the normal cell. Another consideration is the reliability of the reference cell due to repeated write verification and erase verification of the normal cell. • U.S. Patent No. 5,754,475, which is incorporated herein by reference in its entirety in the the the the the the the the the Wherein there is a reference cell at the intersection of each word line and each of the reference bit lines. The reference cells on each reference bit line have a pre-tuned threshold voltage. However, this design is very time consuming to pre-adjust the threshold voltage, thus greatly increasing the manufacturing cost and not being feasible. For example, there are 32,000 word lines in a 1Gb NAND type flash memory device, so 96,000 reference cells will need to adjust their threshold voltage. Another problem is the drift and interference of the reference threshold voltage, 104986.doc - 9 -

E39981 104986 005192358-1 1297501 This is caused by the immediately adjacent frequent bit line and reference bit line. All of the above techniques require a timer to control a control signal (e.g., signal PBLCHM in Figure 2) to initiate a read or write verify operation. In addition, the timing n will be calculated - a predetermined time to ensure that the signal plqad can be switched to a high level in the area 4 of FIG. In practice, the sensing time controlled by the timer (that is, the time point in which the pulse PBLCHM is raised to a high level in the region 5 of FIG. 3) is first determined by computer simulation, and then implemented on the hardware circuit. . Therefore, the sensing time controlled by the timer is extremely likely to cause a failure due to variations in the processing of the bit line RC value (the product of the resistance value and the capacitance value). SUMMARY OF THE INVENTION A method of sensing time in one of the page buffers of a memory cell array and a device for the method. A secondary object of the present invention is to provide a method and

The threshold voltage drift and interference of the reference cells caused by writing and erasing operations in a flash memory device are eliminated. The purpose of the meta-report, the present invention discloses a kind of decision-flash memory: one of the memory cell array buffers - the sensing time: a first - reference bit line, - the first current slot - - - - : Ϊ: Ϊ: zone, - second reference bit line, a second current slot and - second. The first reference bit line is lightly coupled between the first current slot and the first reference page buffer, and the second second current slot and the second reference page buffer line are coupled to each other. The slots are all disposed outside the memory cell array, and the heart should be:

104986.doc Ε39981 104986 005192358-1 -10· 1297501 The position of the normal cell and the normal bit line. Therefore, the drift of the reference cell threshold voltage generated during the writing and enclosing operations can be eliminated. In addition, the first and second current slots respectively provide the first reference bit line and the second reference bit line to a ground path and are respectively disposed at a farthest distance from the first and second reference page buffers. .

In one embodiment, the first and second current sinks are each formed by a single reference cell (e.g., NAND cell) and the control gate is coupled to a reference word line. In another embodiment, the first and second current slots each comprise a plurality of fuses. Each fuse is connected in series with a transistor (for example, M〇s). After the plurality of fuses are connected in parallel, the gates of the transistors are connected in common to a multi-test sub-line. These fuses are used to adjust the amount of current flowing through the current sink. In addition, the reference word line of the first and second current slots is electrically isolated from the seven-state element line of the normal cell. Therefore, the shift of the reference cell voltage can be effectively eliminated. In addition, the device of the present invention further includes a first reference masking bit 70 line and a third reference bit line for respectively shielding the younger and the second reference bit line. A method for sensing time of one of a page buffer of a memory cell array in a flash memory device of the present invention, comprising: coupling a first reference page to a first reference page via a first current sink The first reference bit line of the buffer is discharged, (2) discharging a first reference bit line coupled to a second reference page buffer via a second current slot; (3) when the first reference bit When the voltage of the line reaches a first predetermined voltage, a first control signal is generated; and (4) when the voltage of the first reference bit 70 reaches a second predetermined voltage, a first control apostrophe is generated. The second control signal is generated by the first control

104986.doc E39981 104986 005192358-1 -11 - 1297501 The state of the signal signal and the potential of a node coupled to the second reference bit line are determined, the first and second control signals are provided to the page buffer, And the generation time of the second control signal determines the sensing time. [Embodiment] Hereinafter, a method of determining a sensing time of a flash memory device of the present invention and an embodiment of an apparatus for performing the same will be described. 4 is a schematic diagram showing a memory cell array 4 of a sensing time device 5 using one of the flash memory elements of the present invention. The memory cell array 4 includes a string select line SSL, a ground source line GSL, a plurality of word lines (WL0 WLWLn), and a plurality of normal cell lines (normal cell) Bit line) (BL0~BLm). Each of the word lines (WL0~WLn) is coupled to a plurality of control gates of the normal cells 40, and each of the normal cell lines (BL0~BLm) is coupled to an individual string selection transistor. (string select transistor) SST, its individual normal cell page buffer (ΡΒ0~PBm) and individual ground source transistor GST. The device 5 for determining the sensing time of a flash memory component of the present invention comprises: a first reference bit line RBL0, a second set of reference bit lines RBL1 and RBL2, a first current slot 52, and a first The two current slots 54, a first reference page buffer RPB0 and a second reference page buffer RPB1. The first reference bit line RBL0 is coupled between the first current slot 52 and the first reference page buffer RPB0, and the second group of reference bit lines includes a second reference bit line RBL1 and a third The reference bit line RBL2 is coupled between the second current slot 54 and the second reference page buffer RPB 1. Physical layout of each reference bit line RBLO, RBL1, and RBL2 (physical 104986.doc -12-

E39981 104986 005192358-1 1297501 layout) is the same as the physical layout of the normal cell line (BL0~BLm), which is achieved by the same process; but each reference bit line RBL0, RBL1 and RBL2 and their corresponding The source electrode of the string selection transistor SST is not electrically connected. Therefore, each reference bit line RBL0, RBL1

And the parameter variation of RBL2 and the normal cell line (BL0~BLm) due to ambient temperature or process, such as RC variation, can cancel each other out. In addition, in the writing or erasing operation, in order to eliminate the problem of threshold voltage drift of the reference cells (not shown) located in the first and second current slots 52 and 54, the first and second current slots 52 and 54 are disposed outside the memory cell array 4 and are respectively disposed at the farthest ends of the first and second reference page buffers RPB0 and RPB1. In addition, the first and second current slots 52 and 54 are the only ground paths of the first reference bit line RBL0 and the second set of reference bit lines RBL1 and RBL2, respectively. The device for determining the time of sensing one of the flash memory components of the present invention

A first reference mask bit line SBL0 is further coupled to the first reference page buffer RPB0 and used to mask the first reference bit line RBL0. In operation, if the second reference bit line RBL1 is set to be discharged via the second current slot 54, the third reference bit line RBL2 will be grounded by the second reference page buffer RPB1 to shield the second reference bit line RBL1. The second reference bit line RBL1; vice versa. In other words, if the third reference bit line RBL2 is set to be discharged via the second current slot 54, the second reference bit line RBL1 will be grounded by the second reference page buffer RPB1 to shield the third Reference Bit Line RBL2 ° FIGS. 5(a) and 5(b) are schematic circuit diagrams showing two embodiments of the first current sink 52. Referring to Fig. 5(a), the first current sink 52 is formed by a NAND cell, 104986.doc -13 E39981 104986 005192358-1 1297501, whose control gate is connected to a reference word line RWL. The NAND cell has a reference cell with an adjustable threshold voltage and the reference word line RWL is at a high level only for reading, verifying (including write verify and erase verify). In addition, the reference word line RWL and the normal cell line are electrically isolated from each other, so that no interference occurs. When reading or verifying, the control signal of the normal cell page buffer (ΡΒ0~PBm) will be started and the control signals of the first and second reference page buffers RPB0 and RPB 1 will also be activated. Thereafter, the first and second reference page buffers RPB0 and RPB1 output signals to the normal cell page buffer (ΡΒ0~PBm) to sense the data stored in the normal cell 40. As a result, the output signals of the first and second reference page buffers RPB0 and RPB1 (like the signals PLOAD, PBLCHM and PBLCHC in Fig. 2) are automatically triggered without the need to additionally design a counter to control the triggering of the above output signals. The first current slot 52 in FIG. 5(b) includes a plurality of fuses FUSE, each fuse FUSE is connected in series with a transistor MOS, and the plurality of wires are connected in parallel to the first reference bit line RBL0 and The gates of the respective transistor MOS are commonly connected to the reference word line RWL. Figures 5(c) and 5(d) are similar to those of Figures 5(a) and 5(b), respectively, illustrating an embodiment of the second current sink 54 having an additional two control signals SEL1 And SEL2. The roles of the two control signals SEL1 and SEL2 are described below. When MOS1 is turned on and MOS2 is turned off, the second reference bit line RBL1 will be discharged via the second current slot 54 and the third reference bit line RBL2 will be grounded via the second reference page buffer RPB 1 To mask the second reference bit line RBL1. Similarly, when MOS2 is turned on and MOS1 is turned off, the third reference bit line RBL2 will be discharged via the second current sink 54 and the second reference 104986.doc • 14-

E39981 104986 005192358-1 1297501 The test bit line RBL1 will be grounded via the second reference page buffer RPB1 to mask the third reference bit line RBL2. 6 is a circuit diagram of an embodiment of the first reference page buffer RPB0 for determining a time at which a first control signal (eg, signal PLOAD of FIG. 2) is switched to a high level, that is, the end of the signal development time. point. 7 is a circuit diagram of an embodiment of the second reference page buffer RPB1 for determining a time at which a second control signal (eg, signal PBLCHM or BLCHC of FIG. 2) is switched to a high level, that is, starting reading. Sensing time for write verification or erase verification. Referring to Figures 2, 6 and 7, the first and second control signals will be provided to a page buffer comprising two registers 205 and 206. The working principle of Fig. 6 will be described in detail below with reference to Fig. 8, wherein Fig. 8 is a timing chart of each signal in Fig. 4 during the read operation. It is assumed that the signal VBL is designed to be a waveform of VBLE as shown in Fig. 3 when the even bit line or the odd bit line is set to access data. In the region 2 of Fig. 8, first, the first reference bit line RBL0 is ground-discharged by turning on the NMOS 601. At this time, the node RSOO is also discharged. After entering zone 3, the signal RBLSHF remains at 2.0V and the signal RPLOAD is pulled to the low level. Since the node RSOO is boosted to Vcc by turning on the PMOS 604 and the signal PHI is at a high level, an inverter 605 including QP and QN will receive a high level input signal, so according to the circuit design of FIG. 6, the signal PLOAD will be pulled to a low level. At the same time, the first reference bit line RBL0 will be stabilized at about 1.0V and the signal RWL' (ie, the signal on the reference word line RWL) will be raised to a high level so that the first reference bit line RBL0 can pass through the first A current sink 52 is grounded (see Figure 5(a) or 5(b)). After entering zone 4, signal RPLOAD switches to high level to close

E39981 104986 005192358-1 104986.doc _15 _ 1297501 Free PMOS 604. At the same time, the signal RWL1 has a high level such that the first reference bit line RBL0 is grounded via the first current slot 52. Therefore, node RSOO will begin to discharge via NMOS 603 to the first reference bit line RBL0. When the potential of the node RSOO and the first reference bit line RBL0 is discharged to a first predetermined voltage (for example, 〇_3V), the inverter will sense the low level signal of the node RSOO and output a high level signal. The signal PL0AD is switched back to the high level again (refer to path 1 of FIG. 8), which indicates that the signal development time is completed. At this time, the normal cell line corresponding to the accessed cell having the low threshold voltage is discharged to a potential of about the first predetermined voltage and the signal of the node SO (refer to FIG. 2) is ready to be connected to the normal cell position. Yuan line. The position of the signal PL0AD will be maintained in the area 6, but the signal PHI will be converted to the low level. The read signal RD, the erase verify signal E VR and the write verify signal P VR in Fig. 6 are used to ensure that the initial state of the signal PL0AD is high. In addition, the NM0S 602 is continuously turned on, so that the first reference mask bit line SBL0 is grounded to shield the first reference bit 7 RB RB L 0 . FIG. 7 is a circuit diagram of an embodiment of a second reference page buffer RPB1, wherein the third reference bit line RBL2 is configured to mask the second reference bit line RBL1 and refer to FIG. 5(c) or 5 ( d) In the present embodiment, the signal SEL1 is continuously maintained at a high level. Referring to Figure 8, signal PL0AD switches to a high level at the end of region 4. After entering the area 5, the node RS01 is turned on to the first reference bit line RBL1. In other words, when the second reference bit line RBL1 is discharged by the second current slot 54 to a second predetermined voltage (eg, 0.3V), M〇S 701 will be turned on and the node RS01 will be from the high level of Vcc. Discharge. When the potential of the node RSO1 drops to approximately 〇5Vcc, the inverter Q1 will be 104986.doc -16 -

E39981 104986 005192358-1 1297501 senses a low level input signal and outputs a signal PUL. The signal PUL is input to a circuit D1 together with the read signal RD and the write verification signal PVR to generate a pulse signal PBLCHM (refer to path 2 of FIG. 8) for initiating read and write verification operations (refer to US patent). 1; 86, 671, 204 and 7 and Figure 9). In addition, the signal PUL can be input to a circuit D2 together with the erase verify signal EVR to generate a pulse signal PblcHC for initiating an erase verify operation (refer to US Pat. No. 6,671, 2-4). Circuit A (including a capacitor C1, inverters Q2 and Q3) in Fig. 7 is used to delay the generation of pulse signals pBLCHM and PBLCHC, but circuit A can be omitted. Circuit b (including a capacitor C2 and an inverter Q4) is used to determine the pulse width of the pulse signals PBLChm and PBLCHC. As shown in FIG. 7, the second control signal PBLChm (or PBLCHC) is generated by the state of the first control signal pl〇ad and the potential of the node RS〇1 that is coupled to the second reference bit line RBL1. Determined. In a NAND type flash memory device, normal cells need to be erased and written. The operation of erasing verification and write verification is similar to the reading operation. Therefore, the method for determining the sensing time of one of the flash memory components of the present invention and the apparatus for performing the method can also be applied to the above-mentioned erasing verification and writing. Enter the verification operation. For example, 'in Figure 2' signal PblchM is triggered during read and write verification (see Figure 9 and Figure 7 of US Patent US 6,671,204); signal PBLCHC is triggered during erase verification ( See Figure 16 of U.S. Patent No. 6,671,2,4. The circuits of Figures 6 and 7 in conjunction with the circuit of Figure 4 are used to generate control signals PLOAD, PBLCHM and PBLCHC automatically, accurately and without the use of a timer. In addition, the method and apparatus proposed by the present invention can omit the conventional technique 104986.doc -17-

E39981 104986 005192358-1 1297501 The computer simulation steps necessary to determine the sensing time in the art, and the design of the NAND-type flash memory component does not need to take into account the extreme operating environment (such as abnormal ambient temperature or operation). Under the condition of voltage). In addition, the method and apparatus of the present invention can eliminate the problem of drift of the reference voltage of the reference cell during write verification or erase verify operation. In summary, the present invention does achieve the intended purpose. The technical contents and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing a page buffer circuit in a conventional NAND type flash memory device; FIG. 2 is a schematic diagram showing a page buffer circuit in another conventional nand type flash memory device; FIG. 4 is a schematic diagram of a memory cell array according to the present invention; FIG. 5(a) and FIG. 5(b) are circuit diagrams of a second embodiment of a first current sink; 5(c) and 5(d) are schematic diagrams of a second embodiment of a second current sink; FIG. 6 is a circuit diagram of one embodiment of a first reference page buffer; and FIG. 7 is a second reference page buffer A circuit diagram of an embodiment; and FIG. 8 is a timing diagram of each signal during a read operation.

104986 °〇5192358-1 104986.doc -18-

1297501 [Description of main component symbols] 4 Memory cell array 5 Determines one of the flash memory components sensing time device 40 Normal cell 52 First current slot 54 Second current slot

102~106, 201~204, 601~603, 70 and QN NMOS 101, 604 and QP PMOS 107 latch 205~206 register 605 inverter A, B circuit BL bit line BL0~BLm normal cell Line BLE, BLO Bit Line FUSE Fuse GSL Ground Source Line GST Ground Source ΡΒ0~PBm Normal Cell Page Buffer RBL0 First Reference Bit Line RBL1 Second Reference Bit Line RBL2 Third Reference Bit Line RPB0 First reference page buffer RPB1 second reference page buffer SBL0 first reference mask bit line SSL string select line SST string select transistor WL0~WLn word line Q1~Q8 inverter C1~C2 capacitor 104986.doc -19- ;,, A E39981 104986 005192358-1

Claims (1)

1297501 X. Patent application scope: The method of flashing § 己 忆 兀 § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § § The method includes the following steps: when one of the reference page buffers refers to the first predetermined voltage of the page buffer, the second predetermined voltage is discharged to a first reference bit line via a first current slot; Discharging a first reference bit line to be discharged via a second current slot; generating a first control signal when the voltage of the first reference bit line reaches _; and when the voltage of the second reference bit line Reaching a second control signal; wherein the generating of the second control signal determines the first and second controls by a state of the first control signal and a potential of a node coupled to the second reference bit line The signal is provided to the page ^ ^ ^ ^ ^ 1 The generation of the second control signal determines the sensing time. The method of requesting the flash memory component sensing time according to claim 1, wherein the second control signal is used to initiate reading, /, /, and authentication. Intrusion verification or smearing test 3. The method of flash memory component sensing time according to claim 1 further includes the step of grounding a first reference occlusion bit line, the dying image: Shielding bit line system Coupling to the first reference page is slow " multiple reference reference bit line. _ first 4. According to the method of requesting the flash memory component sensing time of the device i, 104986.doc 1297501 further comprises the step of grounding a second inflammation, the test bit line, the third reference bit The green system is coupled to the 箆 兮 兮 兮 & 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The decision 1 of the flash memory component senses that the physical layout of the first and second 夂I - & 矣 彡 7 线 lines is the same as the physical layout of the π line of the normal cell. J (4) The method of claim 1 for flash memory component sensing time, the gate is connected: the slot or the second current slot includes a helper cell, and the control 7 gate is connected to the reference character line. The method of determining the time at which the flash memory component senses, the height: i. When the line is read, written, verified or smeared, it is in the middle of the method of determining the time of sensing the flash memory component, the basin is connected; and the body, the second and the second The reference bit line and the NAND cell string are connected to the third reference bit line and the cell line. The μ second reference bit line is used to shield the second reference bit. 9. According to the method of requesting the item 1, the time of sensing the time of the flash memory component, the bean meal first ^ _ /, 盥 - The electric body body slot includes a plurality of fuses, and each of the fuses is connected with two or more fuses in parallel, and the idle poles of each of the transistors determine the time of sensing the flash memory components. 104986.doc E39981 104986 005192358-1 1297501 = = slot = with two transistors, respectively connected to the second reference 11 12. 13. 14. • According to the request item 丨 two fixed ^ yuan line for the use of occlusion control . The method of flash memory component sensing time memory component - _ type flash memory component where the = item 1 determines the method of flash memory component sensing time _ Λ, ~ and second The current slot is disposed outside the memory cell array. Element: a device for sensing time of a flash memory component, the flash memory 1 is located in a cell of a memory cell, the device comprising: a stomach in the middle of the shout [and a plurality of 1 first current slots; a second current buffer; a first reference page buffer; a second reference page buffer; a first reference bit line coupled between the first current slot and the first reference page buffer; a second reference bit line coupled between the second current slot and the second reference page buffer; wherein the first and second reference bit lines are respectively discharged to the first and second current slots The first predetermined voltage and the second predetermined voltage are used to determine a first control signal and a second control signal, and the second control signal is generated by the state of the first control signal and the first The voltage of the node of the second reference bit line is determined, and the first and second control signals are supplied to the page buffer. According to the apparatus of claim 13, the device for sensing the time of the flash memory component, the first current slot or the second current sink of the 104986.doc 1297501 includes a nand cell connected to a reference word line. • According to the device 14 for determining the time of flash memory component sensing, the 16 character line is electrically isolated from the normal character line of the cell. • The apparatus for determining the flash memory component sensing time by the method of the first reference frame, which is coupled to the first reference page buffer to mask the first reference bit line. ^ According to the device of claim 16, the device for sensing the time of the flash memory component, wherein the first reference mask bit line is grounded to shield the first line. The device for determining the time of the flash memory component sensing according to claim 13, further comprising a third reference bit line, the system is coupled to the second reference page buffer and the second current slot, The second reference bit line is shielded. 19. The sensing of the mosquito flash memory component sensing time according to claim 18, wherein the second reference bit line is grounded to shield the second reference bit line. The apparatus for sensing the time of flash memory component sensing according to claim 13, wherein the physical layout of the first and second reference bit lines is the same as the physical layout of the bit line of the normal cell. 21. The device for flash memory component sensing time according to the method of claim 13, wherein the first or second current slot comprises a plurality of fuses, each fuse is connected in series with a transistor, and the plurality of fuses are connected in parallel The gates of each of the transistors are connected in common to a reference word line. 22. A device for sensing a time of flash memory component sensing according to claim 21 The second current slot of the 97599.doc E39981 104986 005192358-1 1 further includes two transistors, which are respectively connected in series with the second reference bit line and a third reference bit line for use in the shading control. 23. The means for sensing the time of flash memory component sensing according to claim 13, wherein the first and second current slots are disposed outside of the memory cell array. 24. The device for sensing the time of flash memory component sensing according to claim 23 is repeated. The first and second current slots are disposed at a farthest end from the first reference page buffer. Brother one Device, component. It is: according to the request i 3 determines the flash memory component sensing time, the Shaanxi flash memory component is a NAND flash memory 104986.doc