>C/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種導線結構，且特別是有關於一種 在晝素陣列内之驅動晶片間’用來傳遞電源的導線結構。 【先前技術】>C/006 IX. Description of the Invention: [Technical Field] The present invention relates to a wire structure, and more particularly to a wire structure for transferring power between drive chips in a pixel array. [Prior Art]
圖1A係繪示一種習知之自動焊接帶（TapeAut()mated Bonding，TAB )形式之畫素陣列與印刷電路板部分的連接 關係示意圖。請參照圖1，在早期，晝素陣列與印刷電路 板的連接，多藉由自動焊接帶技術，例如自動焊接帶 TAB1、TAB2和TAB3將晝素陣列100與印刷電路板12〇 彼此連接起來。而在每一自動焊接帶上，都配置有驅動驅 動晶片’例如A1、A2和A3。而每-自動焊接帶有都配置 有二穩壓電容’例如電容C卜C2和C3，以作為驅動晶片 ，? _示圖1A之等效電路圖。請參照圖ΐβ，驅1A is a schematic view showing the connection relationship between a pixel array in the form of a conventional tape bond (TAB) and a printed circuit board portion. Referring to Fig. 1, in the early stage, the connection of the pixel array to the printed circuit board was connected to the printed circuit board 12 by the automatic soldering tape technology, such as the automatic soldering strips TAB1, TAB2 and TAB3. On each of the automatic soldering strips, drive drive wafers 'e.g., A1, A2, and A3 are disposed. Each of the automatic soldering strips is provided with two voltage stabilizing capacitors, such as capacitors Cb, C2 and C3, as the driving chip, and the equivalent circuit diagram of Fig. 1A is shown. Please refer to the figure ΐβ, drive
;V 系分別電性連接至電源端(例如類比工作 :二〜Γ/乍老電壓Vdd)和接地端GND。其中，每 壓。-般來說，電容C置有電容C1〜C3 ’係用來進行穩 鈥而，炎 〜C3的典型值大約為105(100000)PF。 具競爭力。因此降=晶顯示11的製造成本’以使其能更 造晝素陣列的㈣，别已經有些液晶顯示面板，能夠在製 夠藉由節省印刷^也將轉晶片整合在其上，以致於能 降低製造的成本，板的體積，及減少焊接帶材的使用來 5 doc/006 圖2A係緣示一種習知之陣列佈線(wire〇nArray，簡 稱WOA)形式的晝素陣列與印刷電路板部分的連接關係示 意圖。請參照圖2A，在晝素陣列100上，係整合了多數個 驅動晶片（A1〜A5)。這些驅動晶片（A1〜A5)是分別甩來驅動 • 在晝素陣列100上的多數條資料線和多數條掃描線。晝素 ' 陣列10()可以藉由軟性印刷電路板102而電性連接至一印 刷電路板12()，藉此，配置在印刷電路板102上的控制電 路就得以控制所有在晝素陣列1 〇〇上的驅動晶片（A1〜A5)。 圖2B係繪示圖2A之部分放大圖。請合併參照圖2a 和圖2B,在相鄰的驅動晶片之間的類比工作電壓端 和數位工作電壓端VDD以及接地端GND，係利用導線 (Conductive lines or wires) 2卜 23 和 25 彼此互相電性連 接。藉此，印刷電路板120上的控制電路，就可以將電源 傳送至晝素陣列1〇〇上所有的驅動晶片。 、 在電路上來說，為了使負載的電壓穩定，會在靠近負 載的地方會配置一個電容用來穩壓。因此，對晝素陣列上 • 的驅動晶片來說，最理想的偏壓方式，是在連接類比工作 電壓端vAA和數位工作電壓端Vdd，以及接地端gnd配 置一旁置電容。然而由於晝素陣列製程上的限制，以致於 • 難以實現上述的技術。而在實際的情況中，為了使每一驅 - 動晶片2接收之電壓能夠穩定，因此設計者會在印刷電路 板120罪近軟性印刷電路板之處配置旁置 然而，旁置電容122距離驅動晶片（A1〜A5)太遠，因此稃 壓的效果有限。 〜 6 1296¾¾ wf.doc/006 此外’在驅動晶片（A1〜A5)的製程上，會在驅動晶片 内部配置一内部電容，因此也有些設計者利用驅動晶片的 内部電容來進行穩壓。圖係繪示圖2A之部份等效電路 圖。請參照目2C，利用陣列佈線技術所配置的驅動晶片 Α$1:Α3，僅能夠利用其内部所配置的電容(未繪示）來進行 穩壓而，由於這些内部電容是配置在驅動晶片的内部， 因^電容值無法太大。典型來說，驅動晶片之内部電容的 又。十之私谷值，最大也大約只有奸左右，因此利用 内部電容來進行穩壓的效果並不是很理想。 【發明内容】 之莫本發明的目的就是在提供一種具有高寄生電容 電容來以在驅動晶片的電源端提供靖^ 用於種具有高寄生電容之導線結構，可以適 多的驅動曰片1^晝素陣列中°在基板上還配置有許 都具有-i曰一^來驅Ϊ晝素陣列，並且每一驅動晶片 線結構包括了】源端。本發明所提供的導 相鄰之驅動晶片上^層’係形成在基板上，以電性連接 -。在第弟—電源端和第二電源端二者其中之 導電層上。一】二：形成一絕緣層’並且覆蓋在第-第-導體層㈣性,係形成在絕緣層上，並且不同於 的第二電源端二者^妾相^^動晶片上的第一電源端和 具有不同的電位。另外 、^導電層和第一導電層 在弟一V电層上還覆蓋有一保護 1296亂。_ 層0 其中，第-電源端所接收的電壓可以是類比 或是數位工作電壓。另外，第二電源端可以是接屯 觀點來看’本發明提供一種具有高寄生電容之 =層結構’同樣也可以適用在基板上的晝素陣列中 二板上也配置有許多的驅動晶片來轉晝素_ 一驅動晶片都具有一第一電源端、_ + w且母 端。本發明所提供之導線層結構包三 V線。第一導線包括了一第一 V線和弟二 以電性連接相鄰之驅動晶片上的J二電源基板上， 和第三電源端三者其中之-。在第— 弟二電源端 絕緣層。而第—縣層上配置=層上覆蓋有第一 =電層而電性連接相鄰之驅動晶1不同於第 —電源端和第三電源端三去 上的弟一電源端、第 一導電層具有不同的電位。另外，於第二導電層與第 有-第一保護層。類似地 ^二導電層上還覆蓋 同樣配置在基板上，以電性 ，具有-第三導電層， :、二:第二電源端和第三電源 々、、、。構相同，在第三 “中之一。與第一 在、，二絕緣層上，同樣也配置覆蓋有第二絕緣層。而 =電層而電性連接相鄰=導電層’其不同於第 ^源端和第三電源端三者另^片上的第1源端、第 上思層具有不同之電後。其中，，致於第四導電層與第 包源端、第二電源端和第三^鄰之驅動晶片上的第 〜而係分別電性連接至第 1296¾^ twf.doc/006 1296¾^ twf.doc/006 弟四導電層四者至 ‘笔層、苐一導電層、第三導電層和 少其中之一。 山ft ’第—電源端所接收的電壓可以是類比工作電壓 弟二電源端所接收的電壓可以是數位工作電壓，而第 二電源端可以是接地端。 =上所述’由於第—導電層和第二導電層之間具有不 雷:電，’而第三導電層和第四導電層之間也具有不同的 本發明所提供的導線結構可以具有較高的寄 生私谷來提供驅動晶片之電源端的穩壓。 為讓本發明之上述和其他目的、特徵和優點能更明顯 ‘重，下文特舉較佳實施例，她合所關式，作詳細說 明如下。 【實施方式】 圖3係緣示-種液晶顯示面板之内部結構示意圖。請 參照圖3，在液晶顯示器中，包括了配置在基板31〇 ，的畫素_以及印刷電路板33。。在基板31。上配置有 夕數條資齡DU〜DLm，係料―方向彼此互相平行排 列:此外，在基板310上還配置有多數條掃描線su〜SLn， 係=第二方向彼此互相平行排列。其中，資料線沉卜沉瓜 和，描線SL1〜SLn會彼此交錯但不會接觸，並且第一方向 和第二方向可以彼此垂直。 在每一資料線DL1〜DLm和掃描線SL丨〜SLn所圍的空 間内，都配置一畫素單元，因此在基板31〇會形成書 列。此外，每-畫素單元都會具有―閘極端和—源極端， I29695L2wf.d〇 c/006 係分別對應連接至其中一條掃描線SL1〜SLji和資料線 DL1〜DLm。例如’在資料線dl〇和DL1以及掃描線SL〇 和SL1所圍的空間内，係配置有晝素單元312。而畫素單 元的問極端係耦接至掃描線SLO，而其源極端則是耦 接資料線DLG。由於已财？篇專利在討論晝素單元的結 構及原理’而為了不讓熟習此技藝者混淆本發明的精神， 因此在此；f對晝素單元咖部結構及卫作原理細的介 紹。 、The V system is electrically connected to the power supply terminal (for example, analog operation: two ~ Γ / 乍 old voltage Vdd) and the ground GND. Among them, each pressure. In general, capacitor C is provided with capacitors C1 to C3' for stabilization, and the typical value of inflammation ~C3 is approximately 105 (100,000) PF. Competitive. Therefore, the manufacturing cost of the crystal display 11 is 'to make it more versatile (4), and there are some liquid crystal display panels, which can be integrated on the wafer by saving printing, so that Reduce the cost of manufacturing, the volume of the board, and reduce the use of soldered strips. 5 doc/006 Figure 2A shows a conventional array of wiring arrays (WOA) in the form of a pixel array and a printed circuit board. Diagram of the connection relationship. Referring to Fig. 2A, on the pixel array 100, a plurality of driving chips (A1 to A5) are integrated. These drive chips (A1 to A5) are respectively driven to drive a plurality of data lines and a plurality of scan lines on the pixel array 100. The pixel array 10() can be electrically connected to a printed circuit board 12() by a flexible printed circuit board 102, whereby the control circuit disposed on the printed circuit board 102 can control all of the pixel arrays 1 Driver wafers (A1 to A5) on the crucible. 2B is a partial enlarged view of FIG. 2A. Referring to FIG. 2a and FIG. 2B together, the analog operating voltage terminal and the digital operating voltage terminal VDD and the grounding terminal GND between adjacent driving chips are electrically connected to each other by using conductive lines or wires 2 and 23 and 25 Sexual connection. Thereby, the control circuit on the printed circuit board 120 can transfer power to all of the drive chips on the pixel array 1. In terms of circuit, in order to stabilize the voltage of the load, a capacitor is placed near the load for voltage regulation. Therefore, for the driver chip on the pixel array, the most preferable bias mode is to configure a side capacitor at the connection analog voltage terminal vAA and the digital operating voltage terminal Vdd, and the ground terminal gnd. However, due to limitations in the process of the halogen array, it is difficult to achieve the above technology. In the actual case, in order to stabilize the voltage received by each of the driving wafers 2, the designer will arrange the side of the printed circuit board 120 near the flexible printed circuit board. However, the side capacitor 122 is driven by the distance. The wafers (A1 to A5) are too far away, so the effect of rolling is limited. ~ 6 12963⁄43⁄4 wf.doc/006 In addition, in the process of driving the chips (A1 to A5), an internal capacitor is placed inside the driver chip, so some designers use the internal capacitance of the driver chip for voltage regulation. The figure shows a part of the equivalent circuit diagram of Figure 2A. Please refer to item 2C. The driver chip Α$1:Α3 configured by the array wiring technology can only be regulated by the internal capacitor (not shown), since these internal capacitors are arranged inside the driver chip. Because the capacitance value cannot be too large. Typically, the internal capacitance of the chip is driven. Ten private valleys, the largest is only about a few people, so the use of internal capacitors for voltage regulation is not very satisfactory. SUMMARY OF THE INVENTION The object of the present invention is to provide a wire structure having a high parasitic capacitance to provide a high-parasitic capacitance at the power supply end of the driving chip, and a plurality of driving blades can be provided. In the halogen array, a substrate is further disposed on the substrate, and each of the driving wafer line structures includes a source end. The adjacent driving chip of the present invention is formed on the substrate to be electrically connected. On the conductive layer of both the first power source and the second power terminal. a second: forming an insulating layer 'and covering the first-first conductor layer (four), formed on the insulating layer, and different second power terminals to the first power supply on the wafer The ends have different potentials. In addition, the conductive layer and the first conductive layer are covered with a protection 1296 disorder. _ Layer 0 where the voltage received by the first-power terminal can be analog or digital. In addition, the second power supply terminal may be an interface view. The present invention provides a layer structure having a high parasitic capacitance. The same applies to a pixel array on a substrate. The transfer transistor has a first power supply terminal, _ + w and a female terminal. The wire layer structure provided by the present invention comprises a three-wire line. The first wire includes a first V wire and a second wire electrically connected to the J power source substrate on the adjacent driving chip, and the third power source terminal. In the first - second power supply insulation layer. The first-level layer is covered with the first=electric layer and electrically connected to the adjacent driving crystal 1 different from the first power supply end and the third power supply end. The layers have different potentials. In addition, the second conductive layer and the first-first protective layer. Similarly, the two conductive layers are also covered on the substrate, electrically, having a third conductive layer, :, two: a second power supply terminal and a third power source 々, , . The structure is the same, in the third "one. With the first, the second insulating layer, the same is also covered with a second insulating layer. And = electrical layer and electrically connected adjacent = conductive layer' is different from the first ^ The source end and the third power supply end have the first source end and the upper layer of the upper layer have different electric powers. Among them, the fourth conductive layer and the first package source end, the second power supply end and the The third on the driver chip is electrically connected to the 12963⁄4^ twf.doc/006 12963⁄4^ twf.doc/006 four conductive layers four to the 'pen layer, the first conductive layer, the third The conductive layer and one of the less. The voltage received by the mountain ft 'the power terminal can be the analog operating voltage. The voltage received by the power supply terminal can be a digital operating voltage, and the second power terminal can be a ground terminal. The wire structure provided by the present invention may have a higher height due to the difference between the first conductive layer and the second conductive layer, and the third conductive layer and the fourth conductive layer. The parasitic private valley provides the voltage regulation of the power supply terminal of the driving chip. The purpose, features, and advantages of the present invention will be more apparent. The following is a detailed description of the preferred embodiment, which will be described in detail below. [Embodiment] FIG. 3 is a schematic diagram showing the internal structure of a liquid crystal display panel. Referring to Fig. 3, in the liquid crystal display, a pixel _ and a printed circuit board 33 disposed on the substrate 31 are included. On the substrate 31, DAYs DU to DLm are arranged, and the materials are oriented to each other. Arranged in parallel with each other: in addition, a plurality of scanning lines su to SLn are arranged on the substrate 310, and the second direction is arranged parallel to each other. wherein the data lines are submerged and the lines SL1 to SLn are interlaced but not The first direction and the second direction may be perpendicular to each other. A pixel unit is disposed in a space surrounded by each of the data lines DL1 to DLm and the scanning lines SL丨 to SLn, and thus is formed on the substrate 31. In addition, each pixel unit has a "gate terminal" and a source terminal, and I29695L2wf.d〇c/006 is respectively connected to one of the scan lines SL1 to SLji and the data lines DL1 to DLm. For example, 'in the data Line dl〇 and The space surrounded by the DL1 and the scan lines SL〇 and SL1 is provided with a pixel unit 312. The polarity of the pixel unit is coupled to the scan line SLO, and the source terminal is coupled to the data line DLG. The patents are discussing the structure and principle of the unit of the prime unit. In order to prevent the skilled person from confusing the spirit of the present invention, here, f is a detailed introduction to the structure and the principle of the satellite unit.
，基板310上還具有驅動晶片D〇〜Dm以及s〇〜sn， j =一驅動晶片S0〜Sn係分別對應耦接其中一條掃描鱗The substrate 310 further has driving chips D〇~Dm and s〇~sn, j=one driving wafers S0~Sn are respectively coupled to one of the scanning scales.
Wc二精t ’驅動晶片S〇〜Sn可以利用一掃描訊號摩 刀別驅動母-條掃描線SL1〜SLn上所配置的晝素單元。類 似地’每-驅動晶片D0〜Dm也分別對應輕接其中一The Wc-second precision t' drive wafers S〇~Sn can drive the pixel units arranged on the mother-strip scan lines SL1 to SLn by a scan signal. Similarly, each of the driving chips D0 to Dm is also lightly connected to one of them.
料線DL1〜DLm，以致於驅動晶片DG〜D 料訊號來點亮每一個晝素單元。 稭由產生貝The feed lines DL1 DL DLm are such that the wafer DG ~ D signal is driven to illuminate each of the pixel units. Straw
基板310上的晝素陣列，係藉由軟性電路板η帝 性連接至印刷電路板330。藉此，印刷 而电 制電路就可以透過配置在相鄰之驅動晶片 上的控 ==導線’來將電源傳送至每—驅^^^ 圖4係沿圖2B之線2a-2a，所綠示 剖面圖。請參照圖4,傳統的導線結構 、冓的部分 係先於基板410上形成導電層412，A當鱼j導電層， αττ)基板的第-金屬層同時圖案化形成，而此^曰曰= loc/006 係用來連接例如圖2中驅動晶片上之類比工作電壓端 VAA、數位工作電壓端vDD和接地端GND三者其中之一。 接著’在導電層412上會覆蓋一層絕緣層414。此時，可 以利用傳統的姓刻技術在絕緣層414表面钮刻出孔洞，以 將部分導電層412的表面曝露出來。然後可以利用傳統的 沉積方法將例如鎢的金屬填滿孔洞，以形成接觸窗插塞 (Contact Plug) 416。再來，可以用傳統的沉積方法在絕緣 層414上如導電層412 一般沉積出導電層418，因此導電 層418係與導電層412為等電位。最後，在導電層418上， 再覆蓋保護層420。 圖5係繪示依照本發明之一較佳實施例的一種導線層 結構之透視圖。請參照圖5，本發明所提供的導線群5〇〇， 係用來連接例如圖3中之相鄰的兩個驅動晶片的類比工作 電壓端VAA和數位工作電壓端Vdd以及接地端GND。在 f線群500中，包括導線51〇和52〇。在本發明中，驅動 曰曰片上之類比工作電壓端Vaa和數位工作電壓端以及 接地端GND，係分別連接導線51〇和52〇至少其中之一。 而在圖5所繪示的實施例中，數位工作電壓端Vdd和類比 工作電壓端VAA係分別連接導線5丨〇和52〇，而接地端gnd 貝JlT以用例如插塞532，而同時連接至導電層612。 在本貝施例中，驅動晶片之類比工作電壓端VAA所接 =電壓’係用提供晶片玉作時所需的類比電壓訊號，而 =曰日片之數位玉作電壓端Vdd所接收的電壓，則是提供 曰曰片工作時所需的數位電壓訊號。 1296SUdoc/cK^ 圖6係繪示依照本發明之一較佳實施例的一種導線結 構之部分剖面圖。在圖6中所繪示的剖面圖，係沿圖5之 線5a_5a’之剖面所繪示。在本發明中，導線510和520的 結構大體上相同。首先假設目6所繪示的導線結構為導線 510所在位置的剖面圖。在本發明中，例如玻璃基板的基 板係形成導電層612，其會連接驅動晶片之類比工 作電壓端vAA和數位工作電壓端Vdd以及接地端gnd三 者ί中之一。在本實施例中，導電層612係電性連接至接 地女而+GND。接著’可以利用傳統的沉積技術在導電層612 上復盍纟巴緣層614。在較佳的實施例中，絕緣層614的 料可以是氮化矽(SiNx)。 ^接著在絶緣層6丨4上形成導電層616，其不同於導 私層612而屯性連接至驅動晶片上之類比工作電壓端Vaa 和數位工作電壓端Vdd以及接地端 GND三者另一，以致 於層612和616可以具有不同的電位。在圖5所緣示 的貫施例巾，導線的導電層⑽係連接數位工作電壓 端vDD、。在較佳的情況下，導電層612可以是鋁、銅 (’ Γ導電層616的材料可以是1呂、銅或是鎢。 笔=後’可以利用傳統的沉積技術而在導電層 618上覆 C呆f層618。而在較佳的實施例中，保護層618的材料 可以是氮化石夕。 導線52〇的結構與導線M0 A致相同，其中導線汹 層616囉也是電性連接至驅動晶片上之類比工作 电[端VAA和數位工作電壓端VDD以及接地端三者 12 I296mf doc/006 其中之一，但是不同於導電層612，以致於導 ㈣也具有不同的電位。在本實施例中，導電層;12係牙連 接至驅動晶片上的接地端咖，而導線520的導電層剔 係連接至驅動晶片上的類比工作電壓端。 曰 總的來說’ W上之類Μ作電壓端I和數位 ΐΐΪ壓端VDD以及接地端_係至少連接導線510的 V =層616，導線520的導電層616以及導電層616其中 綜上所述，由於導電層612與導線510的導電層616 具有不同的電位’因此會在絕緣層6M中形成寄生^容。 同樣的情形也會發生在導線似中。典型來說，在ςς声 614中所形成之寄生電容的電容值總共大約為數千微^ 拉左右’因此本發明可脉_晶㈣電源端提供 一個电谷值較大的電容來進行穩壓。 一另外，由於本發明在相鄰的兩個驅動晶片之間可以配 置三條導線的空間中，僅配置兩條導線。因此，導線5川 和520的寬度/表面積可以相對地較寬，這也有助 生電容的電容值。 、曰加可 圖7係繪示依照本發明另一實施例的一種導線处 部分剖面圖。請參照圖7，在另一選擇實施例中，^形 例如圖3中之畫素陣列内的電極時，同時也可以在保護層 618上形成-電極層62〇,其巾電極層例如是—銦^ (ΙΤΟ)層，並且電極層620可以連接至—共同電位，例如是 共同電壓(Common Voltage，VC0m)，以致於電椏層62〇 ^ 13 ‘包層616具有不同的電位。因此，在保護層训中也可 ^電谷’並且與絕緣層614中的寄生電容串 提供更大之電容值的電容來進行穩壓。或者電 ΰ曰、"可透過接觸窗插塞分別與導電層612_電性連 接，以增加其與導電層616重疊 、 電容值來進行穩壓。 U畔，就奸供更兩的 —雖然本發明已以較佳實施_露如上，職 限疋本發明，任何熟習此技藝者， 二 ’當可作些許之更動與_ 圖1Β#身不圖1Α之等效電路圖。 圖2Α係緣示一種習知 印刷電路板部的連接關係示意圖。佈線形式的晝素陣列與 ，迚係綠示圖1之部分放大圖。 會示圖2Α之部份等效電路圖。 示意圖。"不一種液晶顯示面板之導線結構的内部結構The pixel array on the substrate 310 is connected to the printed circuit board 330 by a flexible circuit board. Thereby, the printed circuit can transmit power to each drive through the control == wire ' disposed on the adjacent drive wafer. FIG. 4 is along line 2a-2a of FIG. 2B. Show the profile. Referring to FIG. 4, the conventional wire structure and the portion of the wire are formed on the substrate 410 to form a conductive layer 412, and the first metal layer of the substrate of the fish j conductive layer, αττ) is simultaneously patterned, and this is The loc/006 is used to connect, for example, one of the analog operating voltage terminal VAA, the digital operating voltage terminal vDD, and the grounding terminal GND on the driving wafer of FIG. Next, an insulating layer 414 is overlaid on the conductive layer 412. At this time, holes can be formed on the surface of the insulating layer 414 by a conventional surname technique to expose the surface of the portion of the conductive layer 412. The metal, such as tungsten, can then be filled with holes using conventional deposition methods to form a Contact Plug 416. Further, the conductive layer 418 can be deposited on the insulating layer 414 as the conductive layer 412 by conventional deposition methods, so that the conductive layer 418 is equipotential to the conductive layer 412. Finally, on the conductive layer 418, the protective layer 420 is overlaid. Figure 5 is a perspective view showing the structure of a wire layer in accordance with a preferred embodiment of the present invention. Referring to FIG. 5, the wire group 5〇〇 provided by the present invention is used to connect, for example, the analog operating voltage terminal VAA and the digital operating voltage terminal Vdd and the grounding terminal GND of two adjacent driving chips in FIG. In the f-line group 500, wires 51A and 52B are included. In the present invention, the analog operating voltage terminal Vaa and the digital operating voltage terminal and the grounding terminal GND on the driving die are respectively connected to at least one of the wires 51A and 52B. In the embodiment illustrated in FIG. 5, the digital operating voltage terminal Vdd and the analog operating voltage terminal VAA are respectively connected to the wires 5丨〇 and 52〇, and the grounding terminal gnd is used to connect with the plug 532 at the same time. To the conductive layer 612. In the present embodiment, the analog voltage of the driving chip is connected to the operating voltage terminal VAA = voltage is used to provide the analog voltage signal required for the wafer jade, and the digital voltage of the digital chip is the voltage received by the voltage terminal Vdd. , is to provide the digital voltage signal required for the operation of the cymbal. 1296 SUdoc/cK^ Figure 6 is a partial cross-sectional view showing a wire structure in accordance with a preferred embodiment of the present invention. The cross-sectional view shown in Fig. 6 is shown along the line 5a-5a' of Fig. 5. In the present invention, the structures of the wires 510 and 520 are substantially the same. It is first assumed that the wire structure shown in Fig. 6 is a sectional view of the position of the wire 510. In the present invention, for example, the substrate of the glass substrate is formed with a conductive layer 612 which is connected to one of the analog voltage terminal vAA and the digital operating voltage terminal Vdd and the ground terminal gnd of the driving chip. In this embodiment, the conductive layer 612 is electrically connected to the ground female and +GND. The pad layer 614 can then be overlaid on the conductive layer 612 using conventional deposition techniques. In a preferred embodiment, the material of the insulating layer 614 may be tantalum nitride (SiNx). Then, a conductive layer 616 is formed on the insulating layer 6丨4, which is different from the conductive layer 612 and is electrically connected to the analog operating voltage terminal Vaa and the digital operating voltage terminal Vdd and the grounding terminal GND on the driving wafer. That is, layers 612 and 616 can have different potentials. In the embodiment shown in Fig. 5, the conductive layer (10) of the wire is connected to the digital operating voltage terminal vDD. In a preferred case, the conductive layer 612 may be aluminum or copper (the material of the conductive layer 616 may be 1 liter, copper or tungsten. The pen = back may be overlaid on the conductive layer 618 using conventional deposition techniques) C is a layer 618. In a preferred embodiment, the material of the protective layer 618 may be nitride nitride. The structure of the wire 52 is the same as that of the wire M0 A, wherein the wire layer 616 is also electrically connected to the drive. The analog power on the wafer [the end VAA and the digital operating voltage terminal VDD and the ground terminal 12 I296mf doc / 006 one of them, but different from the conductive layer 612, so that the conduction (four) also has a different potential. In this embodiment The conductive layer; the 12-series is connected to the grounding terminal on the driving wafer, and the conductive layer of the wire 520 is connected to the analog working voltage terminal on the driving wafer. 曰 In general, the voltage of the W is used. The terminal I and the digital voltage terminal VDD and the ground terminal are connected to at least the V=layer 616 of the wire 510, the conductive layer 616 of the wire 520, and the conductive layer 616, as described above, due to the conductive layer 612 and the conductive layer 616 of the wire 510. Have different potentials' so will be The parasitic layer 6M forms a parasitic capacitance. The same situation also occurs in the wire like. Typically, the capacitance value of the parasitic capacitance formed in the click 614 is about several thousand micro pulls in total. The pulse-crystal (four) power supply terminal provides a capacitor with a large electric valley value for voltage regulation. In addition, since the present invention can configure three wires in the space between two adjacent drive chips, only two wires are disposed. Therefore, the width/surface area of the wires 5 and 520 can be relatively wide, which also has the capacitance value of the auxiliary capacitor. Fig. 7 is a partial cross-sectional view showing a wire according to another embodiment of the present invention. Referring to FIG. 7, in another alternative embodiment, when an electrode in the pixel array of FIG. 3 is formed, for example, an -electrode layer 62 can also be formed on the protective layer 618, and the electrode layer is, for example, An indium layer, and the electrode layer 620 may be connected to a common potential, such as a common voltage (VC0m), such that the cap layer 616 has different potentials. Protective layer training is also available ^Electrical Valley' and a capacitor with a larger capacitance value in the parasitic capacitance string in the insulating layer 614 is used for voltage regulation. Alternatively, the electro-optical, " can be electrically connected to the conductive layer 612_ through the contact window plug, In order to increase the overlap with the conductive layer 616, the capacitance value is used for voltage regulation. U, the traitor is more than two - although the present invention has been better implemented - as described above, the scope of the present invention, anyone skilled in the art, The second 'when it can make some changes and _ Figure 1Β# is not the equivalent circuit diagram of Figure 1. Figure 2 shows the connection relationship of a conventional printed circuit board part. The halogen form of the wiring form and the green part of the green line of Fig. 1 are shown. Part of the equivalent circuit diagram of Figure 2 is shown. schematic diagram. "The internal structure of a wire structure of a liquid crystal display panel
Si圖=心崎示之部分剖面圖。 結構之透視圖。 較锃貫施例的一種導線層 圖6係1會示依照本發明之—較佳實施例的-種導線結 f.doc/006 構之部分剖面圖。 圖7係繪示依照本發明另一實施例的一種導線結構的 部分剖面圖。 【主要元件符號說明】 100 :畫素陣列 102、314 :軟性印刷電路板 120、330 :印刷電路板 310 ' 410 > 610 :基板 • 312 :晝素單元 412、418、612、616 :導電層 414、614 ·•絕緣層 416 :接觸窗插塞 420、618 :保護層 500 :導線層 510、520 :導線 620 :電極層 鲁 A1〜A5、D1〜Dm、S1〜Sn :驅動晶片 C1〜C3 :電容 DL1〜DLm :資料線 SL1〜SLn . TAB1〜TAB3 :自動焊接帶 15Si map = part of the cross section of the heart. Perspective view of the structure. A wire layer of a more conventional embodiment. Fig. 6 is a partial cross-sectional view showing a wire junction f.doc/006 in accordance with a preferred embodiment of the present invention. Figure 7 is a partial cross-sectional view showing a wire structure in accordance with another embodiment of the present invention. [Main component symbol description] 100: pixel array 102, 314: flexible printed circuit board 120, 330: printed circuit board 310 '410 > 610: substrate • 312: halogen unit 412, 418, 612, 616: conductive layer 414, 614 · Insulation layer 416: contact window plugs 420, 618: protective layer 500: wire layer 510, 520: wire 620: electrode layer Lu A1 ~ A5, D1 ~ Dm, S1 ~ Sn: drive wafer C1 ~ C3 : Capacitors DL1 to DLm: data lines SL1 to SLn . TAB1 to TAB3: automatic soldering belts 15