1296879 爲第91120418號中文全份說明書無劃線修正本 修正日期:2003.9.9 玖、發明說明： 發明領域 本發明是有關於一種延遲鎖定迴路(Delay Locked Loop， DLL)，且較特別的是，有關於一種具有多時相（multi-phases) 之延遲鎖定迴路。 習知技術 使用內建記憶體，高速處理訊號的半導體裝置，使用 一個時相鎖定迴路(Phase Locked Loop，PLL)，或是一個延 遲鎖定迴路(Delay Locked Loop，DLL)，讓輸入/輸出資料 與系統時脈同步。DLL的特色是具有較少跳動(jitter)，並 且較PLL可靠。然而，相較於PLL而言，DLL的缺點是具 有有限的時相（phases)。近來，各種不同的克服DLL缺點 的方法，已經被硏究出來。因爲即使在電源雜訊非常嚴重 的數位區塊(digital block)中，DLL依舊可以可靠地運作， 所以具有廣泛的應用。 第1圖是一個現有的DLL的方塊圖。請參考第1圖，現 有的DLL 101包括一個時相比較器(phase comparator)lll， —個電荷幫浦（electric charge pump) 121，一個過濾器 (€山61*)131，和一個延遲元件((161&}^161116111)141。首先時相 比較器111會比較一個輸入時脈訊號（CLKIN)，和一個輸出 時脈訊號（CLK0UT)的時相。接下來，時相比較器會把時 相差，當成第一訊號(UP)或第二訊號(DN)輸出。電荷幫浦 121則根據第一訊號（UP)或第二訊號（DN)，增加或減少輸 出電壓(VI)。接下來，過濾器131會消除包含在輸出電壓(VI) 10008pifl.doc/008 5 1296879 爲第91120418號中文全份說明書無劃線修正本 修正曰期:2003.9.9 的交流成分(AC)。最後，延遲元件141會將輸入時脈訊號 (CLKIN)，延遲一個時間週期，將訊號當成輸出時脈訊號 (CLKOUT)輸出，並且根據過濾器131的輸出電壓，改變輸 出時脈訊號（CLKOUT)的延遲時間。 在現有的DLL 101中，有限的時相捕捉範圍，有可能會 引起諧波鎖定（harmonic lock)。 第2A圖繪示與輸入時脈訊號(CLKIN)同步的第1圖中的 DLL 101的輸出時脈訊號。在一個時間週期（T1)之後，輸 出時脈訊號（CLKOUT)的上升邊緣(rl)，會與輸入時脈訊號 (CLKIN)的上升邊緣(r2)同步。 第2B圖繪示在諧波鎖定狀態中的第1圖中的輸出時脈訊 號。在兩個時間週期(T1+T2)之後，輸出時脈訊號(CLKOUT) 的上升邊緣(r3)，會與輸入時脈訊號(CLKIN)的上升邊緣(r4) 同步。即使在三個時間週期之後，輸出時脈訊號（CLKOUT) 的上升邊緣(r3)，會與輸入時脈訊號(CLKIN)的上升邊緣同 步，輸出時脈訊號依舊是在一個被視爲異常狀態的諧波鎖 定狀態中。然而，時相比較器111，會將此判斷爲正常狀 態。這就是現有的DLL 101的問題。 IEEE J. Solid-state Circuits, vol 32, pp.1683-1692, Nov 1997,發表一種在DLL最初的運作中，以最小的延遲啓動延 遲線的方法，當成一種諧波鎖定的解決方案。然而，在該 文獻中所發表的方法，只能部分地解決諧波鎖定，並不是 諧波鎖定的基本解決方案。 美國專利標準申請案編號5,663,665，揭露另一種解決 10008pifl.doc/008 6 1296879 爲第91120418號中文全份說明書無劃線修正本 修正日期:2003.9.9 諧波鎖定的方法。該專利標準申請案的時相鑑別器(phase discriminator)，可以檢測延遲元件的最後標記（last tab)訊 號的上升邊緣，是否與中間標記（middle tabs)訊號的上升 邊緣相同。如果時相鑑別器檢測到有相同的上升邊緣，爲 判斷諧波鎖定存在，並且藉由調整延遲速度，以避免諧波 鎖定。然而，如果沒有任何中間標記訊號的上升邊緣，與 最後標記訊號的上升邊緣相同，則該專利標準申請案所定 義的時相鑑別器，無法檢測到時相差，所以無法避免諧波 鎖定。 之外，在有些範例中，DLL的使用者需要使用任意的 (randomly)延遲時脈訊號。然而，現有的DLL只能將輸出 時脈訊號，延遲一個預定的時間。 發明槪述 爲解決上述問題，本發明的第一目的，是提供一種可 以完全避免諧波鎖定的延遲鎖定迴路(DLL)。 本發明的第二目的，是提供一種可以選擇性地輸出任 意的延遲時脈訊號的DLL。 根據本發明，所提供的延遲鎖定迴路DLL包括：一個 延遲單元，用來接收一個輸入時脈訊號，產生一個時相在 輸入時脈訊號之後的輸出時脈訊號，並且響應輸入時脈訊 號，產生複數個具有不同時相延遲的延遲訊號；一個諧波 鎖定避免單元，用來接收輸入時脈訊號和複數延遲訊號， 比較輸入時脈訊號和該些延遲訊號的時相，根據比較的結 果，產生一個第一訊號，或是一個第二訊號，並且輸出第 10008pin.doc/008 7 1296879 爲第91120418號中文全份說明書無劃線修正本 修正曰期:2003.9.9 一訊號或第二訊號；一個電荷幫浦，用來接收第一訊號和 第二訊號，產生一個時相控制訊號，並且響應第一訊號和 第二訊號，將時相控制訊號的電壓，調成高於或低於一個 預定的電壓；一個過濾器，用來消除包含在時相控制訊號 中的交流成分AC，並且將已過濾的訊號，傳送給延遲單 元；以及複數個啓動電路（start-up circuits)，在產生輸出 時脈訊號之前，在初始狀態中，供給一個第一電壓給電荷 幫浦，並且使電荷幫浦提供一個第二電壓給延遲單元，其 中延遲單元提供一個延遲鎖定電路，用來響應時相控制電 壓，調整輸出時脈訊號和複數延遲訊號的時相。 延遲單元最好可以包括：複數個串列連接的延遲元件， 用來延遲輸入時脈訊號，並且輸出輸出時脈訊號和複數延 遲訊號；以及一個偏壓單元（bias unit)，根據過瀘器輸出 訊號的電壓，控制該些延遲元件的延遲量。複數延遲訊號， 最好是從複數個延遲元件的特定元件所輸出。 諧波鎖定避免單元最好可以包括：複數個時相檢測器， 用來比較輸入時脈訊號和複數延遲訊號中的兩個鄰近的訊 號，如果發現有時相延遲(phase lag)，就啓動第一訊號， 如果發現有時相超前(phase lead)，就啓動第二訊號，並且 接收輸入時脈訊號和複數延遲訊號中的兩個鄰近的訊號； 一個第一NOR閘和第二NOR閘，每一個NOR閘都接收 複數個時相檢測器一半的輸出；一個第三NOR閘，用來 接收第一 NOR閘和第二NOR閘的輸出，並且輸出第一訊 號；以及一個第一^ NAND聞’用來接收第一* NOR閑和第 10008pifl .doc/008 8 1296879 爲第91120418號中文全份說明書無劃線修正本 修正日期:2003.9.9 二NOR閘的輸出，並且輸出第二訊號。該些時相檢測器 最好可以包括：一個第一延遲正反器（delay flip-flop)，用 來接收電源電壓和第一延遲訊號，並且產生時相檢測器的 輸出；一個第二延遲正反器，用來接收電源電壓，和具有 最接近第一延遲訊號時相的第二延遲訊號；以及一個第二 NAND閘，用來接收第一延遲正反器和第二延遲正反器的 輸出，並且提供輸出給第一延遲正反器和第二延遲正反 器。此外，如果第一訊號被啓動，電荷幫浦最好可以將時 相控制訊號的電壓，調成高於預定電壓，如果第二訊號被 啓動，電荷幫浦最好可以將時相控制訊號的電壓，調成低 於預定電壓。電荷幫浦包括一個第一電晶體，該電晶體輸 出一個電源電壓，並且藉由啓動電路的輸出控制其閘門 (gated) 〇 如果時相控制電壓變成高於預定電壓，則輸出時脈訊 號和複數延遲訊號的時相，最好可以超前（advanced)。如 果時相控制電壓變成低於預定電壓，則輸出時脈訊號和複 數延遲訊號的時相，最好可以落後（delayed)。啓動電路最 好可以包括：一個第一延遲正反器，用來接收輸入時脈訊 號和讀出時脈訊號；以及一個第二延遲正反器，用來接收 第一延遲正反器和輸出時脈訊號的輸出，並且產生啓動電 路的輸出。如果在輸出時脈訊號產生之前，輸出時脈訊號 在初始狀態是在邏輯低狀態（logic low)，則啓動電路最好 可以輸出邏輯低狀態，開啓第一電晶體，並且將電源電壓 提供給過濾器，以使得輸出時脈訊號，可以很快地與輸入 10008pifl .doc/008 9 1296879 爲第91120418號中文全份說明書無劃線修正本 修正曰期:2003.9.9 時脈訊號同步。 根據本發明的第二個方面，所提供的延遲鎖定迴路包 括：一個延遲單元，用來接收一個輸入時脈訊號，產生一 個時相在輸入時脈訊號之後的輸出時脈訊號，並且響應輸 入時脈訊號，產生具有不同時相延遲的第一複數延遲訊號 和第二複數延遲訊號；一個諧波鎖定避免單元，用來接收 輸入時脈訊號和第一複數延遲訊號，輸出一個第一訊號和 一個第二訊號，比較輸入時脈訊號和該些延遲訊號的時 相，並且根據比較的結果，產生第一訊號，或是第二訊號； 一個電荷幫浦，用來接收第一訊號和第二訊號，產生一個 時相控制訊號，並且響應第一訊號和第二訊號，將時相控 制訊號的電壓，調成高於或低於一個預定的電壓；一個過 濾器，用來消除包含在時相控制訊號中的交流成分AC， 並且將已過濾的訊號，傳送給延遲單元；以及一個解碼器， 用來解碼一個接收到的位址訊號，並且提供已解碼的訊號 給延遲單元，其中延遲單元響應已解碼的訊號，選擇性的 輸出部分的第二複數延遲訊號，並且提供一個延遲鎖定電 路，用來響應過濾器的輸出訊號，調整輸出時脈訊號和的 第一複數延遲訊號的時相。 延遲單元最好可以包括：複數個串列連接到輸入時脈 訊號的延遲元件；一個偏壓單元，根據過濾器輸出訊號的 電壓，控制該些延遲元件的延遲量；以及複數個開關元件， 連接到相對應的延遲元件的輸出，並且由已延遲的訊號切 換，用來輸出第二複數延遲訊號，其中第一複數延遲訊號， 10008pifl.doc/008 10 1296879 爲第91120418號中文全份說明書無劃線修正本 修正日期:2003.9.9 最好是由延遲元件的特定元件所輸出。開關元件最好可以 是傳輸閘(transmission gate)。 第二複數延遲訊號的個數，最好可以大於第一複數延 遲訊號的個數。 根據本發明的另一方面，所提供的延遲鎖定迴路包括： 一個延遲單元，用來接收一個輸入時脈訊號，產生一個時 相在輸入時脈訊號之後的輸出時脈訊號，並且響應輸入時 脈訊號，產生具有不同時相延遲的複數延遲訊號；一個諧 波鎖定避免單元，用來接收輸入時脈訊號和複數延遲訊 號，輸出一個第一訊號和一個第二訊號，比較輸入時脈訊 號和該些延遲訊號的時相，並且根據比較的結果，產生第 一訊號，或是第二訊號；一個電荷幫浦，用來接收第一訊 號和第二訊號，產生一個時相控制訊號，並且響應第一訊 號和第二訊號，將時相控制訊號的電壓，調成高於或低於 一個預定的電壓；一個過濾器，用來消除包含在時相控制 訊號中的交流成分AC，並且將已過濾的訊號，傳送給延 遲單元；複數個啓動電路，在產生輸出時脈訊號之前，在 初始狀態中，供給一個第一電壓給電荷幫浦，並且使電荷 幫浦提供一個第二電壓給延遲單元；以及一個解碼器，用 來解碼一個接收到的位址訊號，並且提供已解碼的訊號給 延遲單元，其中延遲單元響應已解碼的訊號’選擇性的輸 出部分的第二複數延遲訊號，並且響應過濾器的輸出訊 號，調整輸出時脈訊號和的第一複數延遲訊號的時相。本 發明可以避免諧波鎖定。 10008pifl .doc/008 1296879 ^ 爲第91120418號中文全份說明書無劃線修正本 修正日期:2003.9.9 爲讓本發明之上述和其他目的、特徵、和優點能明顯 易懂，下文特舉一較佳實施例’並配合所附圖式，作詳細 說明如下。 ^ 圖式之簡單說明= 第1圖繪示一個現有的延遲鎖定迴路(DLL)的方塊圖； 第2A圖和第2B圖分別繪示與輸入時脈同步，以及在 諧波鎖定狀態中的第1圖所繪示的DLL的輸出時脈；1296879 is the full text of the Chinese version of No. 91112418 without a slash correction. This revision date: 2003.9.9 发明, invention description: FIELD OF THE INVENTION The present invention relates to a Delay Locked Loop (DLL), and more particularly, It relates to a delay-locked loop with multi-phases. Conventional technology uses built-in memory, high-speed processing of semiconductor devices, using a Phase Locked Loop (PLL), or a Delay Locked Loop (DLL) to allow input/output data and System clock synchronization. The DLL features less jitter and is more reliable than a PLL. However, DLLs have the disadvantage of having a limited phase compared to PLLs. Recently, various methods for overcoming the shortcomings of DLLs have been investigated. Because DLLs can operate reliably even in digital blocks where power supply noise is very severe, they have a wide range of applications. Figure 1 is a block diagram of an existing DLL. Referring to FIG. 1, the existing DLL 101 includes a phase comparator 111, an electric charge pump 121, a filter (mountain 61*) 131, and a delay element ( (161&}^161116111) 141. First, the phase comparator 111 compares an input clock signal (CLKIN) with a phase of the output clock signal (CLK0UT). Next, the phase comparator compares the time difference. When the first signal (UP) or the second signal (DN) is output, the charge pump 121 increases or decreases the output voltage (VI) according to the first signal (UP) or the second signal (DN). Next, filtering The device 131 will eliminate the AC component (AC) included in the output voltage (VI) 10008pifl.doc/008 5 1296879 as the full specification of the Chinese No. 9112418 without the slash correction of this revision period: 2003.9.9. Finally, the delay element 141 The input clock signal (CLKIN) is delayed by one time period, and the signal is output as the output clock signal (CLKOUT), and the delay time of the output clock signal (CLKOUT) is changed according to the output voltage of the filter 131. DLL 101, limited phase The capture range may cause a harmonic lock. Figure 2A shows the output clock signal of the DLL 101 in Figure 1 synchronized with the input clock signal (CLKIN). In a time period (T1) After that, the rising edge (rl) of the output clock signal (CLKOUT) is synchronized with the rising edge (r2) of the input clock signal (CLKIN). Figure 2B is shown in the first figure in the harmonic lock state. Output clock signal. After two time periods (T1+T2), the rising edge (r3) of the output clock signal (CLKOUT) is synchronized with the rising edge (r4) of the input clock signal (CLKIN). After three time periods, the rising edge (r3) of the output clock signal (CLKOUT) is synchronized with the rising edge of the input clock signal (CLKIN), and the output clock signal is still in a harmonic that is considered abnormal. In the locked state, however, the phase comparator 111 will judge this as a normal state. This is a problem with the existing DLL 101. IEEE J. Solid-state Circuits, vol 32, pp. 1683-1692, Nov 1997, published One that initiates the delay line with minimal delay in the initial operation of the DLL France, as a solution for the harmonic lock. However, the method in this document is published only partially solve the harmonic lock is not substantially harmonic lock solution. U.S. Patent Application No. 5,663,665, discloses another solution. 10008pifl.doc/008 6 1296879 is the full specification of the Chinese version of No. 9112418. No correction is made. Correction date: 2003.9.9 Harmonic locking method. The phase discriminator of the patent standard application can detect whether the rising edge of the last tab signal of the delay element is the same as the rising edge of the middle tabs signal. If the phase discriminator detects the same rising edge, it is judged that the harmonic lock is present, and by adjusting the delay speed to avoid harmonic locking. However, if there is no rising edge of any intermediate mark signal, which is the same as the rising edge of the last mark signal, the phase discriminator defined in the patent application application cannot detect the phase difference, so harmonic lock cannot be avoided. In addition, in some examples, users of DLLs need to use any (randomly) delayed clock signals. However, existing DLLs can only delay the output of the clock signal for a predetermined amount of time. Disclosure of the Invention In order to solve the above problems, a first object of the present invention is to provide a delay locked loop (DLL) which can completely avoid harmonic locking. A second object of the present invention is to provide a DLL that can selectively output any delayed clock signal. According to the present invention, a delay locked loop DLL is provided comprising: a delay unit for receiving an input clock signal, generating an output clock signal after a phase pulse input signal, and generating a clock signal in response to the input clock signal a plurality of delay signals having different phase delays; a harmonic lock avoidance unit for receiving the input clock signal and the complex delay signal, comparing the input clock signals with the phases of the delayed signals, and generating according to the comparison result A first signal, or a second signal, and the output of the 10008pin.doc/008 7 1296879 is the full specification of the Chinese version of No. 91112418 without a slash correction. The revised period: 2003.9.9 a signal or a second signal; The charge pump is configured to receive the first signal and the second signal, generate a phase control signal, and adjust the voltage of the phase control signal to be higher or lower than a predetermined one in response to the first signal and the second signal. Voltage; a filter used to remove the AC component AC contained in the phase control signal and transmit the filtered signal to the delay a unit; and a plurality of start-up circuits that supply a first voltage to the charge pump and provide a second voltage to the delay unit in the initial state before generating the output clock signal The delay unit provides a delay lock circuit for adjusting the phase of the output clock signal and the complex delay signal in response to the phase control voltage. Preferably, the delay unit may include: a plurality of serially connected delay elements for delaying the input clock signal, and outputting the output clock signal and the complex delay signal; and a bias unit according to the output of the filter The voltage of the signal controls the amount of delay of the delay elements. The complex delay signal is preferably output from a particular component of a plurality of delay elements. Preferably, the harmonic lock avoidance unit may include: a plurality of phase detectors for comparing two adjacent signals in the input clock signal and the complex delay signal, and if phase lag is found, the first phase is started. a signal, if it is found that sometimes a phase lead, the second signal is activated, and two adjacent signals in the input clock signal and the complex delay signal are received; a first NOR gate and a second NOR gate, each A NOR gate receives half of the output of the plurality of phase detectors; a third NOR gate is provided for receiving the outputs of the first NOR gate and the second NOR gate, and outputs the first signal; and a first ^ NAND smell ' Used to receive the first * NOR idle and the 10008pifl .doc / 008 8 1296879 is the full specification of the Chinese No. 91112418 without a slash correction. This correction date: 2003.9.9 The output of the two NOR gate, and the second signal is output. Preferably, the phase detectors comprise: a first delay flip-flop for receiving the supply voltage and the first delay signal and generating an output of the phase detector; a second delay positive a counter for receiving a power supply voltage and a second delay signal having a phase closest to the first delay signal; and a second NAND gate for receiving the output of the first delay flip-flop and the second delay flip-flop And providing an output to the first delay flip-flop and the second delay flip-flop. In addition, if the first signal is activated, the charge pump preferably adjusts the voltage of the phase control signal to be higher than the predetermined voltage. If the second signal is activated, the charge pump preferably controls the voltage of the phase control signal. , adjusted to be lower than the predetermined voltage. The charge pump includes a first transistor that outputs a power supply voltage and controls its gate by the output of the startup circuit. If the phase control voltage becomes higher than a predetermined voltage, the clock signal and the complex number are output. The phase of the delayed signal is preferably advanced. If the phase control voltage becomes lower than the predetermined voltage, the phase of the output clock signal and the complex delay signal may preferably be delayed. Preferably, the startup circuit can include: a first delay flip-flop for receiving the input clock signal and reading the clock signal; and a second delay flip-flop for receiving the first delay flip-flop and output The output of the pulse signal and the output of the startup circuit. If the output clock signal is in a logic low state before the output clock signal is generated, the startup circuit preferably outputs a logic low state, turns on the first transistor, and supplies the power supply voltage to the filter. In order to make the output clock signal, it can be quickly input with 10008pifl.doc/008 9 1296879 for the full text of the Chinese version of No. 91112418 without a slash correction. The correction period: 2003.9.9 clock signal synchronization. According to a second aspect of the present invention, a delay locked loop is provided, comprising: a delay unit for receiving an input clock signal, generating an output clock signal of a phase after the input clock signal, and responding to the input a pulse signal, generating a first complex delay signal and a second complex delay signal having different phase delays; a harmonic lock avoidance unit for receiving the input clock signal and the first complex delay signal, outputting a first signal and a The second signal compares the input clock signal with the phase of the delayed signals, and generates a first signal or a second signal according to the comparison result; and a charge pump for receiving the first signal and the second signal Generating a phase control signal and, in response to the first signal and the second signal, adjusting the voltage of the phase control signal to be higher or lower than a predetermined voltage; a filter for eliminating the inclusion in the phase control The AC component of the signal is AC, and the filtered signal is transmitted to the delay unit; and a decoder is used to decode one Receiving the address signal, and providing the decoded signal to the delay unit, wherein the delay unit responds to the decoded signal, selectively outputs a second complex delay signal of the portion, and provides a delay locking circuit for responding to the filter The output signal adjusts the phase of the output clock signal and the first complex delay signal. Preferably, the delay unit may include: a plurality of delay elements connected in series to the input clock signal; a bias unit that controls the delay amount of the delay elements according to the voltage of the filter output signal; and a plurality of switching elements, connected The output of the corresponding delay element is switched by the delayed signal to output the second complex delay signal, wherein the first complex delay signal is 10008pifl.doc/008 10 1296879. Line Correction This correction date: 2003.9.9 is preferably output by a specific component of the delay element. The switching element may preferably be a transmission gate. Preferably, the number of the second complex delay signals is greater than the number of the first complex delay signals. According to another aspect of the present invention, a delay locked loop is provided, comprising: a delay unit for receiving an input clock signal, generating an output clock signal of a phase after the input clock signal, and responding to the input clock a signal, generating a complex delay signal having different phase delays; a harmonic lock avoidance unit for receiving the input clock signal and the complex delay signal, outputting a first signal and a second signal, comparing the input clock signal and the Delaying the phase of the signal, and generating a first signal or a second signal according to the result of the comparison; a charge pump for receiving the first signal and the second signal, generating a phase control signal, and responding to the a signal and a second signal, the voltage of the phase control signal is adjusted to be higher or lower than a predetermined voltage; a filter for eliminating the AC component AC included in the phase control signal, and the filter is filtered The signal is transmitted to the delay unit; a plurality of start-up circuits are provided in the initial state before the output clock signal is generated. a first voltage is applied to the charge pump, and the charge pump provides a second voltage to the delay unit; and a decoder for decoding a received address signal and providing the decoded signal to the delay unit, wherein The delay unit responds to the second complex delay signal of the selectively output portion of the decoded signal, and adjusts the phase of the first complex delay signal of the output clock signal and the response signal in response to the output signal of the filter. The present invention can avoid harmonic locking. 10008pifl .doc/008 1296879 ^ For the full text of the Chinese version of No. 91112418, there is no slash correction. The date of this amendment: 2003.9.9 is to make the above and other objects, features, and advantages of the present invention obvious and easy to understand. The preferred embodiment is described in detail with reference to the accompanying drawings. ^ Simple description of the schema = Figure 1 shows a block diagram of an existing delay-locked loop (DLL); Figures 2A and 2B show the synchronization with the input clock, and the second in the harmonic lock state. 1 shows the output clock of the DLL;
第3圖繪示一個根據本發明的一個較佳實施例的DLL 的方塊圖； 第4圖繪示一個電路圖’用來說明在第3圖中的啓動 電路，電荷幫浦和過濾器； 第5圖詳細繪示一個第3圖中所繪示的延遲單元； 第6圖繪示一個第3圖中所繪示的諧波鎖定避免單元 的電路圖； 第7圖繪示一個第6圖中所繪示的時相檢測器的電路 圖； 第8A圖到第8E圖繪示第5圖中的延遲單元的延遲訊 號被發現是將被解鎖(unlocked)時的波形；以及 第9A圖到第9E圖繪示在通過繪示在第6圖中的諧波 鎖定避免單元之後，繪示在第8圖中的已解鎖延遲訊號同 步的情形。 標示之簡單說明= 101 延遲鎖定迴路DLL 111 時相比較器 10008pifl.doc/008 12 1296879 修正日期:2003.9.9 爲第91120418號中文全份說明書無劃線修正本 121 電荷幫浦 131 過濾器 141 延遲元件 301 延遲鎖定迴路DLL 311 諧波鎖定避免單元 321 電荷幫浦 331 過濾器 341 延遲單元 351 啓動電路 361 解碼器 411 第一延遲正反器 412 第二延遲正反器 421 第一電流源 422 第二電流源 431 第一 PMOS電晶體 432 第二PMOS電晶體432 433 第三PMOS電晶體433 441 電容 611- >618 時相檢測器 621 第一 NOR閘 622 第二NOR閘 623 第三NOR閘 631 第一 NAND閘 711 第一延遲正反器 10008pifl.doc/008 13 1296879 爲第91120418號中文全份說明書無劃線修正本修正曰期:2003.9.9 712 第二延遲正反器 721 第二 NAND 閘 較佳實施例 . 第3圖繪τκ一個根據本發明的一個較佳實施例的DLL 的方塊圖。請參考第3圖，DLL 301包括一個諧波鎖定避 免單元311，一個電荷幫浦321，一個過濾器331，一個延 遲單元341，一個啓動電路351，和一個解碼器361。 延遲單元341將輸入時脈訊號(CLKIN)，延遲一個預定 的時間，並且輸出輸出時脈訊號（CLKOUT)。此外，延遲 單元341輸出落後輸入時脈訊號（CLKIN)時相，並且領先 輸出時脈訊號（CLKOUT)時相的第一複數延遲訊號 (dl〜dm)，和第二複數延遲訊號（dll〜din)。第一複數延遲 訊號（dl〜dm)，被輸送到諧波鎖定避免單元311。延遲單元 341連接到解碼器361，並且根據解碼器361的輸出訊號 (ADD0UT)，從第二複數延遲訊號(dll〜din)中，輸出至少 一延遲訊號。因爲延遲單元341包括一個電壓控制的延遲 線（Voltage Controlled Delay Line，VCDL)，可以藉由過濾 器331輸出的一個訊號（V4)，調整輸出時脈訊號 (CLKOUT),第一複數延遲訊號(dl〜dm)，和第二複數延遲 訊號（dll〜din)的延遲時間。 解碼器361解碼接收到的位址訊號（ADDIN)，並且輸 出已解碼的位址訊號(ADD0UT)。 因爲延遲單元341，根據已解碼的位址訊號 (ADD0UT)，輸出具有不同時相的第二複數延遲訊號 10008pifl.doc/008 14 1296879 爲第91120418號中文全份說明書無劃線修正本 修正曰期:2003.9.9 (dll〜din)，所以DLL使用者可以選擇使用dll〜din ,以及 輸出時脈訊號（CLKOUT)。 啓動電路351，接收延遲單元341所輸出的輸出時脈 訊號（CLKOUT)，並且設定訊號（V4)的啓始電壓，其中訊 號(V4)是在輸入時脈訊號(CLKIN)，被輸入到延遲單元341 之前，由過濾器331提供給延遲單元341。輸入時脈訊號 (CLKIN)，與輸出時脈訊號(CLKOUT)相比，具有一個很大 的時相差，其中輸出時脈訊號（CLKOUT)是在輸入時脈訊 號（CLKIN)，被輸入到延遲單元341之前，在開機(power-on)期間，在一個粗糙模式(coarse mode)的初始狀態中，由 過濾器331當成一個輸出時脈訊號（CLKOUT)所輸出的。 換句話說，在初始狀態中，輸出時脈訊號（CLKOUT)是在 邏輯低狀態。如果啓動電路351接收到初始狀態的輸出時 脈訊號（CLKOUT)，就會輸出一個輸出訊號（S1)，當成一 個邏輯低狀態訊號，並且將輸入到延遲單元341的訊號(V4) 的電壓，提升到與電源電壓相同。 因爲啓動電路351，在初始狀態的粗糙模式中，將輸 入到延遲單元341的訊號(V4)的初始電壓，設定成預定的 電壓。所以延遲單元341的輸出時脈訊號（CLKOUT)，就 會很快地與輸入時脈訊號(CLKIN)同步。 在粗糙模式結束之後，DLL 301會在一個細緻模式(fine mode)下運作，以精確地匹配(match)時相。本發明的DLL 301，在細緻模式中，可以避免諧波鎖定，並且精確地匹 配時相。 10008pifl.doc/008 15 1296879 爲第91120418號中文全份說明書無劃線修正本修正日期:2003.9.9 諧波鎖定避免單元311，接收從延遲單元341所輸出 的第一複數延遲訊號（dl〜dm)，並且輸出第一訊號（UP)和 第二訊號（DN)。諧波鎖定避免單元311，會比較在第一複 數延遲訊號（dl〜dm)中鄰近的延遲訊號的時相。如果延遲 訊號的時相差超過一個預定値，諧波鎖定避免單元311， 就會啓動第一訊號(UP)或第二訊號(DN)。 電荷幫浦321接收第一訊號(UP)和第二訊號(DN)，並 且產生一個時相控制訊號（V2)。如果第一訊號（UP)被啓 動，則時相控制訊號(V2)的電壓就爲上升。如果第二訊號 (DN)被啓動，則時相控制訊號(V2)的電壓就爲下降。 過濾器331消除包含在時相控制訊號(V2)中的AC訊 號，並且將具有純DC訊號的訊號（V4)，傳送給延遲單元 341° 如上所述，諧波鎖定避免單元311，會檢測從延遲單 元341所輸出的第一複數延遲訊號(dl〜dm)之間的時相差。 諧波鎖定避免單元311，會檢測時相差是否超過一個預定 範圍，並且將輸出時脈訊號（CLKOUT)，與輸入時脈訊號 (CLKIN)，做精確的同步。因此，可以避免輸出時脈訊號 (CLKOUT)進入諧波鎖定狀態。 第4圖繪示啓動電路351，電荷幫浦電路321和過濾 器電路331的實施例。 請參考第4圖，啓動電路351包括一個第一延遲正反 器411和一個第二延遲正反器412。 第一延遲正反器411，接收一個參考時脈訊號（Fref)和 10008pifl.doc/008 16 1296879 爲第91120418號中文全份說明書無劃線修正本 修正日期:2003.9.9 輸出時脈訊號（CLKOUT)，並且每當參考時脈訊號(Fref)的 位準，從邏輯低上升到邏輯高時，就會產生一個時脈訊號 (P1)。第一延遲正反器411輸出時脈訊號（P1)，該時脈訊 號(P1)是將參考時脈訊號(Fref)，除以二所產生的結果。第 二延遲正反器412輸出訊號（S1)，該訊號（S1)是將第一延 遲正反器411所輸出的時脈訊號(P1)，除以四所產生的結 果。第一延遲正反器411和第二延遲正反器412，接收輸 出時脈訊號（CLKOUT)。如果輸出時脈訊號（CLKOUT)是邏 輯高位準，則兩個正反器411和412都會正常工作。如果 輸出時脈訊號（CLKOUT)是邏輯低位準，則正反器411和 412就會被重設(reset)。如果第二延遲正反器412被重設， 則啓動電路351就會不管輸入的訊號，而將訊號（S1)以邏 輯低訊號輸出。換句話說，如果延遲單元341在初始狀態 時的輸出時脈訊號（CLKOUT)是一個邏輯低訊號，則啓動 電路351就會將訊號(S1)，以一個邏輯低位準輸出。 電荷幫浦321包括一個第一 PMOS電晶體431，一個 第二PM0S電晶體432，一個第三PM0S電晶體433，一 個第一電流源421，和一個第二電流源422，並且輸出時 相控制訊號(V2)。當啓動電路351的輸出是邏輯低時，第 一 PM0S電晶體431被開啓，並且將電源電壓(VDD)，當 成一個時相控制訊號(V2)輸出。當第一訊號（UP)是邏輯低 時，第二PMOS電晶體432會輸出電源電壓(VDD)，並且 增加時相控制訊號（V2)的電壓。當第二訊號（DN)是邏輯低 時，第三PMOS電晶體433會輸出接地電壓(GND)，並且 10008pifl.doc/008 17 爲第91120418號中文全份說明書無劃線修正本 修正日期:2〇〇3·9·9 降低時相控制訊號(V2)的電壓。第一電流源421和第二電 流源422提供固定的電流，並且在某些範例中，可以被省 略或是取代。 如上所述，當第一訊號（UP)和第二訊號（DN)被啓動成 邏輯低時，電荷幫浦321會使時相控制訊號(V2)的電壓’ 高於一個預定的電壓。 過濾器331包括一個電容441，用來消除包含在時相 控制訊號(V2)中的AC，以提供具有純DC訊號的訊號(V4) 給延遲單元341。此外，電容441會被充電到一個特定的 電壓，而且訊號(V4)也會維持在一個預定的電壓上。然而’ 因爲時相控制訊號(V2)的電壓上升，電容器441和訊號(V4) 的電壓也會上升。如果時相控制訊號(V2)的位準變成低位 準，則電容器441和訊號(V4)的電壓也會下降。 如上所述，在輸出時脈訊號(CLKOUT)被正常地輸出之 前，在初始狀態中，啓動電路351會輸出邏輯低。接下來’ 第一 PMOS電晶體431被開啓，並且經由過濾器331，提 供電源電壓(VDD)給延遲單元341，以使得輸出時脈訊號 (CLKOUT)，可以快速地與輸入時脈訊號(CLKIN)同步。 第5圖詳細繪示第3圖中所繪示的延遲單元341的一 個實施例。請參考第5圖，延遲單元341包括複數個延遲 元件（delay elements)(Bl〜Bn)，複數個開關元件（switching elements)(Ql〜Qn-1)，和一個偏壓單元(bias unit)5 11 0 複數個串列連接到輸入時脈訊號（CLKIN)的延遲元件 (B1〜Bn)，會將輸入時脈訊號(CLKIN)，延遲一個預定的時 10008pin.doc/008 18 1296879 爲第91120418藏中文全份說明書無劃線修正本 修正日期:2003.9.9 間，並且輸出第一複數延遲訊號（dl〜dm)，第二複數延遲 訊號（dll〜din)，和輸出時脈訊號（CLKOUT)。每一個第一 複數延遲訊號（dl〜dm)，都是由特定的延遲元件所輸出， 換句話說，就是由每相隔兩個延遲元件，每相隔四個延遲 元件，或是每相隔八個延遲元件所輸出。每一個第二複數 延遲訊號(dll〜din)，都是由一個單一的延遲元件所輸出。 因此，第二複數延遲訊號(dll〜din)的個數，會大於第一複 數延遲訊號（dl〜dm)的個數。然而，在某些範例中，第一 複數延遲訊號（dl〜dm)的個數，可以等於第二複數延遲訊 號(dll〜din)的個數。 根據解碼器361的輸出訊號(ADDOUT)，複數個開關 元件（Q1〜Qn-Ι)會被開啓(turned on)或關閉（turned off)。舉 例來說，如果開關元件(Q1〜Qn-1)是傳輸閘，而且解碼器361 的輸出訊號(ADD0UT)是邏輯高，則開關元件(Q1〜Qn-Ι)會 被開啓。如果解碼器361的輸出訊號(ADD0UT)是邏輯低’ 則開關元件(Q1〜Qn-Ι)會被關閉。如果開關元件(Q1〜Q11·1) 被開啓，則延遲元件(B1〜Bn)的輸出訊號就會被輸出。如 果開關元件(Q1〜Qn-Ι)被關閉開啓’則延遲元件(B1〜Bn)的 輸出訊號就不會被輸出。根據解碼器361的輸出訊號 (ADD0UT)，有可能開啓部分或是所有的開關兀件 (Q1 〜Qn-1)。 根據過濾器331的訊號(V4)的電壓，偏壓單元會啓動 一個第三訊號(AP)或一個第四訊號(AN)。換句話說，如果 訊號(V4)的電壓增加，就會啓動第二訊號(AP)。如果訊遗 10008pifl.doc/008 19 1296879 爲第91120418號中文全份說明書無劃線修正本 修正日期:2003.9.9 (V4)的電壓降低，就會啓動第四訊號（AN)。如果訊號(V4) 的電壓維持不變，則第三訊號(AP)和第四訊號(AN),兩者 都會被停用（deactivated)。響應第三訊號（AP)或第四訊號 (AN)，延遲元件(B1〜Bn)會調整輸入時脈訊號（CLKIN)的延 遲時間。舉例來說，如果第三訊號（AP)被啓動，則延遲元 件(B1〜Bn)會降低輸入時脈訊號(CLKIN)的延遲時間。如果 第四訊號（AN)被啓動，則延遲元件（B1〜Bn)會增加輸入時 脈訊號（CLKIN)的延遲時間。 根據DLL 311的使用目的，可以選擇延遲元件(B1〜Bn) 的個數。 第6圖繪示一個第3圖中所繪示的諧波鎖定避免單元 311的一個實施例的電路圖。請參考第6圖，諧波鎖定避 免單元311，包括複數個時相檢測器(611〜618)，一個第一 NOR閘到一個第三NOR閘（621〜623)，和一個第一 NAND 閘 631 〇 每一個時相檢測器611到618,都會從具有小量時相 差的第一複數延遲訊號（dl〜dm)中，接收兩個延遲訊號， 和輸入時脈訊號(CLKIN)，並且檢測所收到訊號的時相差。 時相檢測器611到618，將參考第7圖，在底下詳細說明。 第一 NOR閘621和第二NOR閘622，分別接收時相 檢測器的輸出P1〜P4和P5〜P8。第三NOR閘623接收第 一 NOR閘621和第二NOR閘622的輸出P9和P10，並 且輸出第一訊號(UP)。第一 NAND閘631接收第一 NOR 閘621和第二NOR閘622的輸出P9和P10，並且輸出第 10008pifl.doc/008 20 1296879 爲第91120418號中文全份說明書無劃線修正本 修正曰期:2003.9.9 二訊號(DN)。 當第一複數延遲訊號（dl〜dm)的延遲時間（tl)，超過下 列公式1所定義的時間時，諧波鎖定避免單元311會產生 一個時相錯誤訊號，並且啓動第一訊號（UP)或第二訊號 (DN)。 [公式1] τ /1 = —x4 η 其中，Τ是輸入時脈訊號(CLKIN)的週期，η在第5圖 中所繪示的延遲元件(Β1〜Bn)的個數。舉例來說，如果輸 入時脈訊號（CLKIN)的週期是20[ns]，而且延遲元件(B1〜Bn)3 is a block diagram of a DLL according to a preferred embodiment of the present invention; and FIG. 4 is a circuit diagram 'illustrating the startup circuit, charge pump and filter in FIG. 3; FIG. A delay unit illustrated in FIG. 3 is illustrated in detail; FIG. 6 is a circuit diagram of a harmonic lock avoidance unit illustrated in FIG. 3; and FIG. 7 is a diagram illustrated in FIG. Circuit diagram of the phase detector; 8A to 8E are diagrams showing the waveform of the delay unit of the delay unit in FIG. 5 when it is found to be unlocked; and FIG. 9A to FIG. 9E After the harmonic lock avoidance unit shown in Fig. 6, the synchronized unlocked signal synchronization in Fig. 8 is illustrated. Simple description of the label = 101 Delay-locked loop DLL 111 Phase comparator 10008pifl.doc/008 12 1296879 Revision date: 2003.9.9 For the full instruction of the Chinese version of No. 91112418, there is no scribe correction. 121 Charge pump 131 Filter 141 Delay Element 301 Delay Lock Loop DLL 311 Harmonic Lock Avoidance Unit 321 Charge Pump 331 Filter 341 Delay Unit 351 Start Circuit 361 Decoder 411 First Delay Rectifier 412 Second Delay Rectifier 421 First Current Source 422 Second Current source 431 first PMOS transistor 432 second PMOS transistor 432 433 third PMOS transistor 433 441 capacitor 611- > 618 phase detector 621 first NOR gate 622 second NOR gate 623 third NOR gate 631 A NAND gate 711 first delay flip-flop 10008pifl.doc/008 13 1296879 is the full specification of the Chinese version of No. 91112418 without a slash correction. The revision period: 2003.9.9 712 second delay flip-flop 721 second NAND gate A preferred embodiment. Figure 3 depicts a block diagram of a DLL in accordance with a preferred embodiment of the present invention. Referring to Fig. 3, the DLL 301 includes a harmonic lock avoidance unit 311, a charge pump 321, a filter 331, a delay unit 341, a start circuit 351, and a decoder 361. The delay unit 341 delays the input clock signal (CLKIN) by a predetermined time and outputs an output clock signal (CLKOUT). In addition, the delay unit 341 outputs the backward input clock signal (CLKIN) phase, and leads the first complex delay signal (dl~dm) of the output clock signal (CLKOUT) phase, and the second complex delay signal (dll~din) ). The first complex delay signal (dl~dm) is supplied to the harmonic lock avoiding unit 311. The delay unit 341 is connected to the decoder 361, and outputs at least one delay signal from the second complex delay signal (dll~din) according to the output signal (ADD0UT) of the decoder 361. Because the delay unit 341 includes a voltage controlled delay line (VCDL), the output clock signal (CLKOUT) can be adjusted by the signal (V4) outputted by the filter 331, and the first complex delay signal (dl) ~dm), and the delay time of the second complex delay signal (dll~din). The decoder 361 decodes the received address signal (ADDIN) and outputs the decoded address signal (ADD0UT). Because the delay unit 341 outputs a second complex delay signal having different phases according to the decoded address signal (ADD0UT), 10008pifl.doc/008 14 1296879 is the full specification of the Chinese version of No. 91112418 without a slash correction. :2003.9.9 (dll~din), so DLL users can choose to use dll~din and output clock signal (CLKOUT). The startup circuit 351 receives the output clock signal (CLKOUT) output by the delay unit 341, and sets the start voltage of the signal (V4), wherein the signal (V4) is input to the delay signal (CLKIN) and is input to the delay unit. Before 341, it is supplied to the delay unit 341 by the filter 331. The input clock signal (CLKIN) has a large phase difference compared to the output clock signal (CLKOUT), wherein the output clock signal (CLKOUT) is input to the delay signal (CLKIN) and is input to the delay unit. Prior to 341, during power-on, in the initial state of a coarse mode, the filter 331 is output as an output clock signal (CLKOUT). In other words, in the initial state, the output clock signal (CLKOUT) is in a logic low state. If the startup circuit 351 receives the output timing pulse signal (CLKOUT) of the initial state, an output signal (S1) is outputted as a logic low state signal, and the voltage input to the signal (V4) of the delay unit 341 is boosted. It is the same as the power supply voltage. Since the start circuit 351, in the rough mode of the initial state, the initial voltage of the signal (V4) input to the delay unit 341 is set to a predetermined voltage. Therefore, the output clock signal (CLKOUT) of the delay unit 341 is quickly synchronized with the input clock signal (CLKIN). After the rough mode ends, the DLL 301 operates in a fine mode to precisely match the phase. The DLL 301 of the present invention, in the fine mode, avoids harmonic locking and accurately matches the phase. 10008pifl.doc/008 15 1296879 is the Chinese full specification of No. 91112418. There is no slash correction. This correction date: 2003.9.9 The harmonic lock avoidance unit 311 receives the first complex delay signal output from the delay unit 341 (dl~dm). And output the first signal (UP) and the second signal (DN). The harmonic lock avoidance unit 311 compares the phases of the adjacent delay signals in the first complex delay signals (dl~dm). If the phase difference of the delayed signals exceeds a predetermined threshold, the harmonic lock avoidance unit 311 activates the first signal (UP) or the second signal (DN). The charge pump 321 receives the first signal (UP) and the second signal (DN) and generates a phase control signal (V2). If the first signal (UP) is activated, the voltage of the phase control signal (V2) rises. If the second signal (DN) is activated, the voltage of the phase control signal (V2) drops. The filter 331 removes the AC signal included in the phase control signal (V2), and transmits the signal (V4) having the pure DC signal to the delay unit 341. As described above, the harmonic lock avoiding unit 311 detects the slave. The phase difference between the first complex delay signals (dl~dm) output by the delay unit 341. The harmonic lock avoidance unit 311 detects whether the phase difference exceeds a predetermined range, and accurately synchronizes the output clock signal (CLKOUT) with the input clock signal (CLKIN). Therefore, it is possible to prevent the output clock signal (CLKOUT) from entering the harmonic lock state. Fig. 4 shows an embodiment of the start-up circuit 351, the charge pump circuit 321 and the filter circuit 331. Referring to Figure 4, the start-up circuit 351 includes a first delay flip-flop 411 and a second delay flip-flop 412. The first delay flip-flop 411 receives a reference clock signal (Fref) and 10008 pifl.doc/008 16 1296879 is the full specification of the Chinese version of No. 91112418. There is no scribe correction. The correction date is: 2003.9.9 Output clock signal (CLKOUT) ), and whenever the reference clock signal (Fref) level rises from logic low to logic high, a clock signal (P1) is generated. The first delay flip-flop 411 outputs a clock signal (P1) which is a result of dividing the reference clock signal (Fref) by two. The second delay flip-flop 412 outputs a signal (S1) which is a result of dividing the clock signal (P1) output by the first delay flip-flop 411 by four. The first delay flip-flop 411 and the second delay flip-flop 412 receive the output clock signal (CLKOUT). If the output clock signal (CLKOUT) is at a logic high level, both flip-flops 411 and 412 will operate normally. If the output clock signal (CLKOUT) is at a logic low level, the flip-flops 411 and 412 are reset. If the second delay flip-flop 412 is reset, the enable circuit 351 outputs the signal (S1) as a logic low signal regardless of the input signal. In other words, if the output clock signal (CLKOUT) of the delay unit 341 in the initial state is a logic low signal, the start circuit 351 outputs the signal (S1) at a logic low level. The charge pump 321 includes a first PMOS transistor 431, a second PMOS transistor 432, a third PMOS transistor 433, a first current source 421, and a second current source 422, and outputs a phase control signal. (V2). When the output of the startup circuit 351 is logic low, the first PMOS transistor 431 is turned on, and the power supply voltage (VDD) is output as a phase control signal (V2). When the first signal (UP) is logic low, the second PMOS transistor 432 outputs a power supply voltage (VDD) and increases the voltage of the phase control signal (V2). When the second signal (DN) is logic low, the third PMOS transistor 433 outputs a ground voltage (GND), and 10008pifl.doc/008 17 is the full specification of the Chinese No. 91112418 without a slash correction. Amendment date: 2 〇〇3·9·9 Reduce the voltage of the phase control signal (V2). The first current source 421 and the second current source 422 provide a fixed current and, in some examples, may be omitted or replaced. As described above, when the first signal (UP) and the second signal (DN) are activated to a logic low, the charge pump 321 causes the voltage of the phase control signal (V2) to be higher than a predetermined voltage. The filter 331 includes a capacitor 441 for canceling the AC included in the phase control signal (V2) to provide a signal (V4) having a pure DC signal to the delay unit 341. In addition, capacitor 441 is charged to a specific voltage and signal (V4) is maintained at a predetermined voltage. However, because the voltage of the phase control signal (V2) rises, the voltage of the capacitor 441 and the signal (V4) also rises. If the level of the phase control signal (V2) becomes low, the voltage of the capacitor 441 and the signal (V4) also drops. As described above, the start-up circuit 351 outputs a logic low in the initial state before the output clock signal (CLKOUT) is normally output. Next, the first PMOS transistor 431 is turned on, and via the filter 331, the power supply voltage (VDD) is supplied to the delay unit 341 so that the output clock signal (CLKOUT) can be quickly input with the clock signal (CLKIN). Synchronize. Fig. 5 shows in detail an embodiment of the delay unit 341 shown in Fig. 3. Referring to FIG. 5, the delay unit 341 includes a plurality of delay elements (B1 to Bn), a plurality of switching elements (Q1 to Qn-1), and a bias unit 5. 11 0 A plurality of serially connected delay elements (B1~Bn) connected to the input clock signal (CLKIN) will delay the input clock signal (CLKIN) by a predetermined time of 10008pin.doc/008 18 1296879 for the 911041818 The Chinese manual does not have a slash correction date: 2003.9.9, and outputs the first complex delay signal (dl~dm), the second complex delay signal (dll~din), and the output clock signal (CLKOUT). Each of the first complex delay signals (dl~dm) is output by a specific delay element. In other words, it is separated by two delay elements, four delay elements each, or eight delays per interval. The output of the component. Each of the second complex delay signals (dll~din) is output by a single delay element. Therefore, the number of second complex delay signals (dll~din) is greater than the number of first complex delay signals (dl~dm). However, in some examples, the number of first complex delay signals (dl~dm) may be equal to the number of second complex delay signals (dll~din). According to the output signal (ADDOUT) of the decoder 361, a plurality of switching elements (Q1 to Qn-Ι) are turned on or turned off. For example, if the switching elements (Q1 to Qn-1) are transmission gates and the output signal (ADD0UT) of the decoder 361 is logic high, the switching elements (Q1 to Qn-Ι) are turned on. If the output signal (ADD0UT) of the decoder 361 is logic low', the switching elements (Q1~Qn-Ι) are turned off. If the switching elements (Q1 to Q11·1) are turned on, the output signals of the delay elements (B1 to Bn) are output. If the switching elements (Q1 to Qn-Ι) are turned off, the output signals of the delay elements (B1 to Bn) are not output. According to the output signal (ADD0UT) of the decoder 361, it is possible to turn on some or all of the switching elements (Q1 to Qn-1). According to the voltage of the signal (V4) of the filter 331, the bias unit activates a third signal (AP) or a fourth signal (AN). In other words, if the voltage of the signal (V4) increases, the second signal (AP) is activated. If the newsletter 10008pifl.doc/008 19 1296879 is the full text of the Chinese version of No. 91112418, there is no slash correction. Amendment date: 2003.9.9 (V4) The voltage is reduced, the fourth signal (AN) will be activated. If the voltage of the signal (V4) remains unchanged, both the third signal (AP) and the fourth signal (AN) will be deactivated. In response to the third signal (AP) or the fourth signal (AN), the delay elements (B1 to Bn) adjust the delay time of the input clock signal (CLKIN). For example, if the third signal (AP) is activated, the delay elements (B1 to Bn) will reduce the delay time of the input clock signal (CLKIN). If the fourth signal (AN) is activated, the delay elements (B1 to Bn) increase the delay time of the input clock signal (CLKIN). According to the purpose of use of the DLL 311, the number of delay elements (B1 to Bn) can be selected. Fig. 6 is a circuit diagram showing an embodiment of a harmonic lock avoidance unit 311 shown in Fig. 3. Referring to FIG. 6, the harmonic lock avoiding unit 311 includes a plurality of phase detectors (611 to 618), a first NOR gate to a third NOR gate (621 to 623), and a first NAND gate 631. 〇 Each of the phase detectors 611 to 618 receives two delay signals, and inputs a clock signal (CLKIN) from the first complex delay signal (dl~dm) having a small amount of phase difference, and detects the received The time difference to the signal. The phase detectors 611 to 618 will be described in detail below with reference to FIG. The first NOR gate 621 and the second NOR gate 622 receive the outputs P1 to P4 and P5 to P8 of the phase detector, respectively. The third NOR gate 623 receives the outputs P9 and P10 of the first NOR gate 621 and the second NOR gate 622, and outputs a first signal (UP). The first NAND gate 631 receives the outputs P9 and P10 of the first NOR gate 621 and the second NOR gate 622, and outputs the first 10008pifl.doc/008 20 1296879 to the Chinese full specification of the No. 91112418 without a slash correction. 2003.9.9 Two signals (DN). When the delay time (tl) of the first complex delay signal (dl~dm) exceeds the time defined by the following formula 1, the harmonic lock avoidance unit 311 generates a phase error signal and activates the first signal (UP). Or second signal (DN). [Formula 1] τ /1 = —x4 η where Τ is the period of the input clock signal (CLKIN), and the number of delay elements (Β1 to Bn) shown by η in Fig. 5. For example, if the period of the input clock signal (CLKIN) is 20 [ns], and the delay elements (B1 to Bn)
T 的個數是20，則延遲時間(tl)就是4[ns]。^必須乘以4的 理由是，第一複數延遲訊號（dl〜dm)是由每相隔四個延遲 元件輸出的。如果第一複數延遲訊號（dl〜dm)是由每相隔 Γ 兩個延遲元件輸出，5就必須乘以2。如果第一複數延遲The number of T is 20, and the delay time (tl) is 4 [ns]. The reason why ^ must be multiplied by 4 is that the first complex delay signal (dl~dm) is output by four delay elements each. If the first complex delay signal (dl~dm) is output by two delay elements per phase, 5 must be multiplied by two. If the first complex delay
T 訊號(dl〜dm)是由每相隔八個延遲元件輸出，7就必須乘以 8 ° 請參考第7圖，時相檢測器611包括一個第一延遲正 反器711，一個第二延遲正反器712，和一個第二NAND 閘721。第一延遲正反器711所接收的輸入時脈訊號 (CLKIN)，和第二延遲正反器712所接收的延遲訊號（dl)， 具有一個時相差。換句話說，延遲訊號（dl)比輸入時脈訊 號（CLKIN) ’被延遲更長的時間。時相檢測器611會產生 10008pifl.doc/008 21 1296879 爲第91120418號中文全份說明書無劃線修正本 修正曰期:2003.9.9 一個脈衝寬度相對應於延遲時間的脈衝訊號(P1)。 第8A圖到第8E圖繪示第5圖中的第一複數延遲訊號 (dl〜dm)被發現是將被解鎖(unlocked)時的波形。 如果包含在延遲單元341的複數延遲元件(B1〜Bn)的故 障(malfunction)，延遲第一複數延遲訊號（dl〜dm)的時相， 則包含在諧波鎖定避免單元311中的時相檢測器611到 618，就會檢測被延遲的時相，產生繪示在第8A圖到第8C 圖的訊號，並且將這些訊號傳送給第一 NOR閘621和第 二NOR閘622。接下來，第一 NOR閘621產生第8B圖 中所繪示的訊號。第二NOR閘622產生第8D圖中所繪示 的訊號。因爲第一 NOR閘621和第二NOR閘622的輸出 (P9, P10)，是藉由第三NOR閘623結合，所以第一訊號(UP) 具有第8E圖中所繪示的波形。電荷幫浦321會增加時相 控制訊號（V2)的電壓，和加速延遲單元341的延遲元件 (B1〜Bn)的動作。接下來，第一複數延遲訊號（dl〜dm)的延 遲訊號，和輸出時脈訊號（CLKOUT)的延遲會被降低。輸 出時脈訊號(CLKOUT)會快速地與輸入時脈訊號(CLkin)同 步。換句話說，可以避免輸出時脈訊號（CLKOUT)，進入 諧波鎖定狀態。 第9A圖到第9E圖繪示在通過繪示在第6圖中的諧波 鎖定避免單元311之後，繪示在第8圖中的已解鎖延遲訊 號同步的情形。如在第9圖中所繪示，如果延遲單元341 的延遲元件（B1〜Bn)正常動作，則時相檢測器611到618 就不會檢測到時相錯誤。接下來，因爲第一訊號（UP)被當 10008pifl.doc/008 22 1296879 爲第91120418號中文全份說明書無劃線修正本 修正日期:2003.9.9 成邏輯高輸出，所以可以維持時相控制訊號(V2)的電壓。 如上所述，根據本發明，延遲單元341會產生第一複 數延遲訊號（dl〜dm)。諧波鎖定避免單元311，會檢測第一 複數延遲訊號（dl〜dm)的時相，並且避免輸出時脈訊號 (CLKOUT)落後。因此，可以避免輸出時脈訊號(CLKOUT)， 進入諧波鎖定狀態。此外，延遲單元341會產生第二複數 延遲訊號(dll〜din)。解碼器361會選擇部分的第二複數延 遲訊號(dll〜din)，而且DLL使用者可以選擇性地使用具有 不同時相的延遲訊號。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 與範圍內，當可作少許之變動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 10008pifl.doc/008 23The T signal (dl~dm) is output by eight delay elements separated by each other, and 7 must be multiplied by 8 °. Referring to Fig. 7, the phase detector 611 includes a first delay flip-flop 711, and a second delay is positive. Counter 712, and a second NAND gate 721. The input clock signal (CLKIN) received by the first delay flip-flop 711 and the delay signal (dl) received by the second delay flip-flop 712 have a phase difference. In other words, the delay signal (dl) is delayed by a longer time than the input clock signal (CLKIN)'. The phase detector 611 will generate 10008 pifl.doc/008 21 1296879. For the full instruction of the Chinese version of No. 91112418, there is no scribe correction. The correction period: 2003.9.9 A pulse signal (P1) corresponding to the delay time of a pulse width. 8A to 8E are diagrams showing the waveform when the first complex delay signal (dl~dm) in Fig. 5 is found to be unlocked. If the malfunction of the complex delay elements (B1 to Bn) included in the delay unit 341 delays the phase of the first complex delay signal (dl~dm), the phase detection included in the harmonic lock avoidance unit 311 The devices 611 to 618 detect the delayed phase, generate signals shown in Figs. 8A to 8C, and transmit the signals to the first NOR gate 621 and the second NOR gate 622. Next, the first NOR gate 621 generates the signal shown in Fig. 8B. The second NOR gate 622 produces the signal depicted in Figure 8D. Since the outputs (P9, P10) of the first NOR gate 621 and the second NOR gate 622 are combined by the third NOR gate 623, the first signal (UP) has the waveform shown in Fig. 8E. The charge pump 321 increases the voltage of the phase control signal (V2) and the operation of the delay elements (B1 to Bn) of the acceleration delay unit 341. Next, the delay signal of the first complex delay signal (dl~dm) and the delay of the output clock signal (CLKOUT) are lowered. The output clock signal (CLKOUT) is quickly synchronized to the input clock signal (CLkin). In other words, it is possible to avoid outputting the clock signal (CLKOUT) and entering the harmonic lock state. 9A to 9E illustrate the case where the unlocked delay signal is synchronized in Fig. 8 after being shown by the harmonic lock avoidance unit 311 in Fig. 6. As shown in Fig. 9, if the delay elements (B1 to Bn) of the delay unit 341 operate normally, the phase detectors 611 to 618 will not detect a phase error. Next, because the first signal (UP) is used as 10008pifl.doc/008 22 1296879 for the full Chinese manual of No. 91112418, there is no slash correction. The correction date: 2003.9.9 is a logic high output, so the phase control signal can be maintained. (V2) voltage. As described above, according to the present invention, the delay unit 341 generates a first complex delay signal (dl~dm). The harmonic lock avoidance unit 311 detects the phase of the first complex delay signal (dl~dm) and avoids the output clock signal (CLKOUT) falling behind. Therefore, it is possible to avoid outputting the clock signal (CLKOUT) and entering the harmonic lock state. In addition, delay unit 341 generates a second complex delay signal (dll~din). The decoder 361 selects a portion of the second complex delay signal (dll~din), and the DLL user can selectively use delay signals having different phases. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 10008pifl.doc/008 23