.'...， .--·. ： .. ； ； ... ； ... .· 九、發明說明： 1發明所屬之技術領域y ^ 本發鴨賴一種_電顧及錄造方法，特別是 關於一種雙通道的薄膜電晶體及其製造方法。 jr 先前技術】 心主動養有❿電激發光顯示器以薄膜電晶體驅動有機 r 極體來顯示晝面 ::為考'光......極體 ’以提供更多的亮度選 明諸圖1 ’_-峡式有靖 ^104' ^ 108' • ^電源線11〇、一有機發光二極體112及一電容114等元 不再贅述。值得一提的是’驅動電晶體108真有雙通道， ^剖面讀參照圖 2 彳 1085。通道1〇84位於閘極金屬1083下方，兩者之間以一 者之間以一絕緣層1087隔開。值得一提的是，通道log# 5 及1085均採用非晶矽材料以適合傳統的低溫製程。 然而’由於非晶矽的電子移動效能(mobility)相對 而1較弱’例如其電子移動效能可能僅有低溫多晶矽的 千分之一，因此有機電激發光二極體的效能表現也會受 到影蟫。解決的方式為增加一額外的金屬1〇88及1〇89 於$道應4两端，並^ 金屬1082。須強調的是，源極金屬丨〇8丨及金暴顺 須有一部分重疊於閘極金屬1083 ;波極金屬 1089岑必須有，部分重疊於閘極金屬簡^ 動效能。 .. ·. ...... - _. ' 金屬l〇8l·及汲極金屬細 屬細3的先襄圖案以達到重疊的t 厨案的設計土應有較嚴格的要求。 【發明内容】 本發明之目的在於以較簡化的方法製作一雙通道薄膜 電晶體，該薄膜電晶體的雨個通道皆為多晶矽通道。 .,， ' ..... , .· '.‘. , ... 本發明之薄膜電晶體包括一第一多晶梦層、一第；絕 緣層、一閘極各屬、>第$絕緣層、一第二多晶梦層及一 金屬層。該第一絕緣層位於該第一多晶砍層上方。該間極 金屬位於該第“絶緣層上方。該第二絕緣層位於該閘極金 屬及該第一絕緣層上方。該第一絕緣層輿該第二絕緣層的 重疊部位具有兩接觸孔分別對應於該第一多晶矽層之兩 端。該第二多晶梦層位於談第二絕緣層上方。以及，該金 1296855.'..., .--.. : .. ; ; ... ; ... .. IX. Description of the invention: 1 The technical field to which the invention belongs y ^ This is a method of recording and recording In particular, it relates to a two-channel thin film transistor and a method of manufacturing the same. Jr prior art] The heart actively raises the xenon excitation light display to drive the organic r body with a thin film transistor to display the kneading surface:: for the 'light...polar body' to provide more brightness Figure 1 '_-Gorge type has Jing ^104' ^ 108' • ^ power line 11 〇, an organic light-emitting diode 112 and a capacitor 114 and so on are not repeated. It is worth mentioning that the 'drive transistor 108 has two channels, ^ section read reference Figure 2 彳 1085. The channel 1 〇 84 is located below the gate metal 1083 with an insulating layer 1087 interposed therebetween. It is worth mentioning that the channels log # 5 and 1085 are made of amorphous germanium material to suit the traditional low temperature process. However, 'the performance of organic electroluminescent diodes is also affected because the relative mobility of amorphous germanium is relatively weak and 1 is weak, for example, its electron mobility efficiency may be only one thousandth of that of low temperature polysilicon. . The solution is to add an additional metal 1〇88 and 1〇89 to the $dao should be 4 ends, and ^ metal 1082. It should be emphasized that the source metal 丨〇8丨 and the gold storm must partially overlap the gate metal 1083; the wave metal 1089岑 must have, partially overlap the gate metal simple efficiency. .. ·. ...... - _. ' Metal l〇8l· and bungee metal thin is a fine 3 stencil pattern to achieve overlapping t kitchen design should have stricter requirements. SUMMARY OF THE INVENTION The object of the present invention is to produce a two-channel thin film transistor in a relatively simplified manner, wherein the rain channel of the thin film transistor is a polysilicon channel. .,, '...., .· '.'., ... The thin film transistor of the present invention comprises a first polycrystalline dream layer, a first layer; an insulating layer, a gate each genus, > $Insulation layer, a second polycrystalline dream layer and a metal layer. The first insulating layer is located above the first polycrystalline chopping layer. The interposing electrode is located above the first “insulating layer. The second insulating layer is located above the gate metal and the first insulating layer. The overlapping portion of the first insulating layer and the second insulating layer has two contact holes respectively corresponding to At the two ends of the first polysilicon layer, the second polycrystalline dream layer is located above the second insulating layer. And, the gold 1285655
，移除一部 興孔。以及， 一多晶砍層及 成一第二多晶發層於該第二絕緣層上方。然後, remove a hole. And a polycrystalline chop layer and a second polycrystalline layer above the second insulating layer. then
_上巧重，本聲明較習知技術少一道光罩^另 於採钱晶梦層作為通道，因此源極金屬及沒極金屬不須 _择金屬部分重疊’可以降取光罩圖案较計上之要求。 ._ - · . .* 餘處合圖示詳述本發明「薄膜電晶體及其製造方法」， 並列舉較佳實施例說明如下“ ； '. .. ....-- ·.. . 请參:照圖3，係為本發明之薄膜電晶體。薄膜電晶體 300包繁^ 與一第一多蟲矽層遍與一第^ 3〇2央i於第一多晶梦層卿輿第二多晶砍層剔之間。 第一多晶♦層麵包括兩摻雜區3·及3〇84及一通道區 3086 ’啤於閘極金屬302下方罐以絕緣層312與閘極f 屬302相搞。第二多晶矽層31〇包括兩摻雜區31〇2及力 及一通道區3106，位於閘極金屬302上方，以絕緣層314 與閘極金屬 3〇2 相隔 : 二接觸孔316及318分別位於閘極金屬302兩側，並 貫穿絕緣層314與312而曝露第一多晶矽層308的摻雜區 3082及3084。源極金屬306形成於接觸孔316中，以接解 於第一多晶矽層3〇8的摻雜區3〇82，以及接觸於第二多晶 梦層310的摻雜區31〇2。沒極金屬3〇4形成接觸孔318中， 以接觸於第一多晶矽層308的摻雜區3084，以及接觸於第 二多晶石夕層310的摻雜區3104。 時，源極金屬306係電性連接至一有機發光二極體4〇〇。 由於第一多晶參層30义及第二多晶矽層31〇為上下重疊， 」因此並不佔用額外的面板面積而避免減小開口率 ... ：'；' *·-.'. .... •值得一提的是，源極金屬如6與接雜區3082之間，或 束波極金屬304與摻雜區3084之間儀直接接觸，不需增設 傷夕卜的▲屬層與閘極▲屬3〇2保赞重叠来促進電子移動。 篇因在於，第一多晶珍層3〇㈣ :晶梦吟墀道。由码可知，本發明之薄膜電晶體在製造土較 習知轉術少一道光旱。詳細的製程步驟敘述如下。· 示意圖。如圖Μ感 護薄膜電晶體_不受其他電路元件干擾 或其他薄膜電晶體的嚅^ 3〇5於絕參層3〇3上方祕將第 接著，形成絕緣層3!2於第一非晶矽層聰 極金屬302製作於絕緣層312上方，並重叠於第一非晶發 層305。然後，形成絕緣層314覆蓋於閘極金孱3〇2 土方^^^ 以及，形成一第二非晶矽層307於絕緣層314上方，並重 1296855 疊於閘極金屬302。此處絕緣層312及314之用途在於分 隔閘極金屬302輿第一非晶梦層305及第二非晶矽! 307被結晶化以形成第一多晶矽層3〇8及笫二多晶矽層 程是快速熱退火製程(rapid thermal anneal，RTA)的一種，其_ On the weight, this statement is less than a mask of conventional technology ^ Another channel is used as a channel for the money crystal layer, so the source metal and the electrodeless metal do not need to overlap the metal part to reduce the mask pattern. Requirements. ._ - · . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Please refer to: according to Figure 3, is the thin film transistor of the present invention. The thin film transistor 300 package is complicated with a first multi-worm layer and a third layer of the first polycrystalline dream layer The second polycrystalline layer is between the layers. The first polycrystalline layer includes two doped regions 3· and 3〇84 and a channel region 3086'. The beer is under the gate metal 302 with the insulating layer 312 and the gate f The second polysilicon layer 31 includes two doped regions 31〇2 and a force and a channel region 3106, which are located above the gate metal 302, separated by an insulating layer 314 from the gate metal 3〇2: The holes 316 and 318 are respectively located on opposite sides of the gate metal 302 and penetrate the insulating layers 314 and 312 to expose the doped regions 3082 and 3084 of the first polysilicon layer 308. The source metal 306 is formed in the contact hole 316 to be connected. Dissolving the doped region 3〇82 of the first polysilicon layer 3〇8, and contacting the doped region 31〇2 of the second polycrystalline dream layer 310. The electrodeless metal 3〇4 is formed in the contact hole 318 to Contact first The doped region 3084 of the germanium layer 308 and the doped region 3104 contacting the second polycrystalline layer 310. The source metal 306 is electrically connected to an organic light emitting diode 4〇〇. A polycrystalline layer 30 and a second polysilicon layer 31 are overlapped one on top of the other, so that no additional panel area is occupied to avoid reducing the aperture ratio... :';' *·-.'.. .. • It is worth mentioning that the source metal, such as between 6 and the junction region 3082, or between the beam-wave metal 304 and the doped region 3084, is in direct contact with the ▲ layer and The gate ▲ is a 3 〇 2 赞 重叠 overlay to promote electronic movement. The reason is that the first polycrystalline layer 3 (4): Jingmeng Road. It can be seen from the code that the thin film transistor of the present invention has less light and drought than the conventional art in the manufacture of soil. The detailed process steps are described below. · Schematic. As shown in Fig. Μ 薄膜 薄膜 电 电 不受 不受 不受 不受 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 其他 Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ The germanium layer of the smart metal 302 is formed over the insulating layer 312 and overlaps the first amorphous layer 305. Then, an insulating layer 314 is formed to cover the gate metal 孱 2 〇 2 ^ ^ ^ and a second amorphous germanium layer 307 is formed over the insulating layer 314 , and the 1296855 is stacked on the gate metal 302 . Here, the insulating layers 312 and 314 are used to separate the gate metal 302, the first amorphous layer 305 and the second amorphous layer 307! 307 are crystallized to form the first polysilicon layer 3〇8 and the second polysilicon layer. Process is a kind of rapid thermal anneal (RTA), which
(CVD)来沉積多晶赛 : ^ W '.. 、 - ' * .... -. -· · - . - ^ .... . . ； - . '.'- . :-- •； ^ ® ^ 309覆蓋一部分的第二多晶矽層31〇。由於第二多晶梦層 ^ ^與第一多晶砍展 蓋了 β分的第一多晶矽層3〇}。接著，施以離子佈填程 __第^晶_ _ 學募的部分形成摻雜區3082、3084、3102及加 丨 f二多晶矽層》1化位於表面’所以分二次實施不同深度的 : 離 ^如圖4D ’移除光阻層3〇9後，原本被光阻層3〇9所覆 蓋而未摻雜的區域即作為通道區3〇86及31〇6。 如圖4E’移除一部分絕緣層312與絕緣層314以形成 兩接觸孔316及318於第二多晶矽層310兩侧，並對應於 第一多晶矽層308的摻雜區3082及3084 ^ 如圖4F，形成一金屬層於第二多晶矽層31Ό之上^认 及每個接觸孔316及318與第一多晶矽層308的曝露表面 上。接著移除第二多晶矽層310通道區3106上方之該金屬 層以定義源極金屬306及沒極金屬304。如此一來，源極 金屬306與汲極金屬304均同時接觸於第一多晶梦層3呢 與第二多晶矽層310。至此 構已製作完成。: 32〇 ,並於純化層32〇本方形成一通孔322。一透呀電 形成於純化層320上方’並藉由通孔322接觸於源極金屬 306。一覆蓋層324形成於透明電極402與純化層 以定義一發光區410及，非發光氣· 再將有機發光二極體400的各種有機層4〇4形 極402及覆蓋層324表面。 請參照圖5 ,係為本發明之第二實施例。相較於圖3 , 主要差異點在於第二多晶矽層之形成位置。本實施例中， 薄膜體5〇0霞二多晶到· 與师金屬504之 率。在製程方面’除了源極金氣寫^ -多晶補5】0的形成次序不同於圖3所示之薄膜電晶體 300 ’其餘步驟均可通用。 在以上兩貝加例中，非晶矽層的結晶化步驟不限於採 甩快速熱退火製， 1296855 · 嗰非晶矽層不限於同時結晶化 值得一提的是，源極金屬與汲極金屬兩者與閘極金屬之間 不限於保持重疊或不重疊。因此，在源極金屬、沒極金屬 及閘極傘屬所用的光罩圖案設計上可以較為靈活。 ^^上所述，本發明至少有如下之優點: :ι·較習知技術少一道光罩。丨 .1 ... 1源極金屬及汲極金屬所用的光罩圖案不須配合間 ψ - ：：··'^：/' -；：,；；.'；,. 木發明技藝精#所為之等效實施或變更，均應包含於本案 之專利範圍中。: . V【《 Α簡單說明八丨 邊線齡 --:...:..， -...'. "" ^ - * ^·:.. .' ..' ."" · ' - :· :' \ ;. ' -. . : . ' . r ^ 離2係為圓1的驅動電晶 . ；； V：.：. .V'\. .· .''^.；^ ·.；,' .. ;^.;/;/ν/^';-：·'；：： '；Λ；--^ I ;；,；； .： :;：；.； V\： .；^ ； 3係根據本發明第實施例之雙填薄薄膜電晶體; .,....' . / , .. ., . - ；.". ；'-'；,；；；；.；' ,.-：'.·.. ·,.；：. ·," ；；...；.·：..,：；_. ；:,·.'.;^ ^- ；：：'.；''." "'*' ' : '； ·:.'. >'Λ·' ； ；'.'.' ：' ' ；·.·\ ·: ' '-： - ;; :. ·' ^ .-' '' 【主要元件符號說明】 .... ’.. ..... .....’ 100 畫素單元 第一多晶矽層 11 1296855 102 掃描線 104 資料線 106 開關電晶體 108 驅動電晶體 1081 源極金屬 1082 沒極金屬 1083 閘極金屬 1084 通道 1085 通道 1086 絕緣層 1087 絕緣層 1088 _ 1089 :金屬 110 電源線: 112 有機發光二極體 114 電容 300 薄膜電惠體 301 基板 302 閘極金屬 303 絕緣層 304 汲極金屬 305 第一非晶石夕層 306 源極金屬 307 第二非晶矽層 3082 摻雜區 3084 摻雜區 3086 通道區 309 光阻層 310 第二多晶石夕層 3102 摻雜區 3104 摻雜區 3106 312 絕緣層 314 ’絕緣層 316 接觸孔 318 接觸孔 320 純化層 322 通孔 324 覆蓉層 400 有機發光二極體 402 透明電極 404 有機層 410 發光區 420 非發光區 500, 薄膜電晶體 504 汲極金屬 506 源極金屬 510 第二多晶矽層 12(CVD) to deposit polycrystals: ^ W '.. , - ' * .... -. -· · - . - ^ .... . . . - . '.'- . :-- •; ^ ® ^ 309 covers a portion of the second polysilicon layer 31〇. Since the second polycrystalline dream layer ^ ^ and the first polycrystalline cut cover the first polycrystalline germanium layer of β points. Then, the portion of the doped regions 3082, 3084, 3102 and the doped f-polysilicon layer formed by the ion cloth filling process is applied to the surface, so that the different depths are implemented twice: After removing the photoresist layer 3〇9 as shown in FIG. 4D, the undoped regions originally covered by the photoresist layer 3〇9 serve as the channel regions 3〇86 and 31〇6. A portion of the insulating layer 312 and the insulating layer 314 are removed as shown in FIG. 4E to form two contact holes 316 and 318 on both sides of the second polysilicon layer 310, and correspond to the doped regions 3082 and 3084 of the first polysilicon layer 308. As shown in FIG. 4F, a metal layer is formed on the exposed surface of each of the contact holes 316 and 318 and the first polysilicon layer 308 over the second polysilicon layer 31. The metal layer over the channel region 3106 of the second polysilicon layer 310 is then removed to define the source metal 306 and the gate metal 304. As a result, the source metal 306 and the drain metal 304 are simultaneously in contact with the first polysilicon layer 3 and the second polysilicon layer 310. So far, the structure has been completed. : 32 〇 , and a through hole 322 is formed in the purification layer 32 〇. A dielectric layer is formed over the purification layer 320 and contacts the source metal 306 via the via 322. A cover layer 324 is formed on the transparent electrode 402 and the purification layer to define a light-emitting region 410 and a non-light-emitting gas. The organic layers 4 and 4 of the organic light-emitting diode 400 and the surface of the cover layer 324 are further disposed. Please refer to FIG. 5, which is a second embodiment of the present invention. Compared with FIG. 3, the main difference lies in the formation position of the second polysilicon layer. In this embodiment, the film body 5 〇 0 Xia di crystal to · the ratio of the teacher metal 504. In the process, the order of formation except for the source gold gas write-polymorph 5 is different from that of the thin film transistor 300 shown in Fig. 3. In the above two additions, the crystallization step of the amorphous germanium layer is not limited to the rapid thermal annealing of the pick, 1296855 · The amorphous germanium layer is not limited to simultaneous crystallization. It is worth mentioning that the source metal and the germanium metal The two are not limited to remain overlapping or non-overlapping with the gate metal. Therefore, the reticle pattern design used in the source metal, the electrodeless metal, and the gate umbrella can be more flexible. As described above, the present invention has at least the following advantages: ι. A mask is less than conventional techniques.丨.1 ... 1 The mask pattern used for the source metal and the bungee metal does not need to match the ψ - ::··'^:/' -;:,;;.';,. Equivalent implementations or changes shall be included in the scope of the patent in this case. : . V [" Α 说明 说明 丨 - - - - -:::.., -...'. "" ^ - * ^·:.. .' ..' ."" · ' - :· : ' \ ;. ' -. . : . ' . r ^ Drives the crystal from the 2 series as a circle 1. ;; V:.:. .V'\. . . . . ;^ ·.;,' .. ;^.;/;/ν/^';-:·';:: ';Λ;--^ I ;;,;; .: :;:;.; V \: .; ^; 3 is a double-filled thin film transistor according to the first embodiment of the present invention; ., . . . , , . . . , . - ;.". ;'-';,; ;;;.;' ,.-:'.·.. ·,.;:. ·,";;...;.·:..,:;_.;:,·.'.;^^-;::'.;''.""'*' ' : '; ·:.'. >'Λ·' ; ;'.'.' :' ' ;···\ ·: ' '-: - ;; :. · ' ^ .-' '' [Main component symbol description] .... '.. ..... .....' 100 pixel unit first polysilicon Layer 11 1296855 102 Scanning line 104 Data line 106 Switching transistor 108 Driving transistor 1081 Source metal 1082 Gate metal 1083 Gate metal 1084 Channel 1085 Channel 1086 Insulation 1087 Insulation 1088 _ 1089 : Metal 110 Power cord: 112 Organic hair Photodiode 114 Capacitor 300 Thin film electrical body 301 Substrate 302 Gate metal 303 Insulation layer 304 Deuterium metal 305 First amorphous layer 306 Source metal 307 Second amorphous layer 3082 Doped region 3084 Doped region 3086 channel region 309 photoresist layer 310 second polycrystalline layer 3102 doped region 3104 doped region 3106 312 insulating layer 314 'insulating layer 316 contact hole 318 contact hole 320 purification layer 322 through hole 324 overlying layer 400 organic light Diode 402 Transparent Electrode 404 Organic Layer 410 Light Emitting Area 420 Non-Light Emitting Area 500, Thin Film Transistor 504 Deuterium Metal 506 Source Metal 510 Second Polycrystalline Layer 12