^ 1295875 — ---- ， 九、發明說明： 頁 【發明所屬之技術領域】 本發明係有關一種電壓倍增電路，尤其有關於一種低 耗損且可程式調整輸出電壓之倍增電路。 - 【先前技術】 ， 直流電（Dc)為電子設備最常使用之電壓源，為了適用 於不同驅動電壓之電子設備（或電子元件），一般會使用 DODC轉換器來改變電壓之大小。請參閱「第】圖」所示， 攀其為一般習用之DC-DC電壓轉換器，其包含一降壓器 l(bandgap)、一電壓幫浦2(pumping CKT)與一穩壓電路 3(regulator)，使用者可依據所需之電壓供應去選擇元件 之特性；假設使用者需要7· 2V之輸出電壓v〇ut，且具有 2·4ν〜3·6ν的系統電壓Vcc，則其可以選擇丨以的降壓器 1與6倍之電壓幫浦2,該系統電壓Vcc先經過降壓器f 之降壓形成1·2ν後，再經過電壓幫浦2之6倍加壓即可 •形成7· 2V之輸出電壓V〇ut，最後再經過該穩壓電路3之 穩壓，即可提供所需之7·2ν穩定之輸出電壓v〇ut，若客 戶不在意些微之電壓變動，則該穩壓電路3亦可不使用。 前述之電壓轉換器，其經過降壓器1之降壓，再利用 高倍數之電壓幫浦2加壓，因此其能量耗損相當嚴重，因 此請參閱「第2圖」所示，目前已發展出直接使用系統電 壓Vcc作為電壓幫浦2之來源電壓的運作方式，同樣假設 使用者需要7· 2v之輪出電壓v〇ut且具有2· 4v〜3· 6 v的 系統電壓Vcc ,則其只需要使用3倍之電壓幫浦2，再經 5 1295875 l-- > 年月日修正替換頁 。 過穩壓電路3之降壓與穩壓，即可提供所需7. 2v穩定之 β 輸出電壓Vout，據此其可改善電壓幫浦2之運作效率，並 降低整體能量之耗損。 又如系統電壓Vcc的工作電壓較廣時，但又需直接使 . 用系統電壓Vcc作為電壓幫浦2之來源電壓的運作方式 時，如假設需要5· Ον之輸出電壓Vout，但具有2· Ον〜3· 6v 的系統電壓Vcc時，則當系統電壓Vcc=3. 0〜3. 6v時，使 用2倍之電壓幫浦2 ;當系統電壓Vcc=2.0〜2·5ν時，使用 ® 3倍之電壓幫浦2 ;當系統電壓Vcc=2· 5〜3· Ον時，則電壓 幫浦2在2、3倍間切換，再藉由穩壓電路3之降壓與穩 壓將輸出電壓Vout穩定在5. Ον，此一運作方式雖可適用 於具較廣之系統電壓Vcc，然當系統電壓Vcc在2. 5〜3. Ον 時，電壓幫浦2會在2、3倍之間切換，而嚴重影響其電 壓之轉換效率。 顯然前述之DC-DC電壓轉換器，其雖可依據使用者之 φ 需求供給電壓，然其在電壓轉換之過程卻不可避免需要經 過降壓，以供給負載所需之電壓，其會造成不必要之能量 損耗。 【發明内容】 爰是，本發明之主要目的係在提供一種低耗損之電壓 倍增電路。 本發明之次要目的係提供一種可程式調整輸出電壓 之電壓倍增電路。 6 1295875 _ 本發明係一種可程式調整輸出電壓之電壓倍增電 一一 路，其包含一電壓幫浦（pumping CKT)、一時脈產生器（CLK generator)與一比較器（comparator)，該電壓幫浦具有 一輸入端、一控制端與一輸出端；該時脈產生器與該電 壓幫浦之控制端連接，其產生時脈訊號控制該電壓幫浦之 動作，讓該電壓幫浦之輸入端的輸入電壓，藉由該電壓幫 浦之加壓於該輸出端產生輸出電壓；該比較器具有二輸入 | 端與一輸出端，該比較器之輸出端與該時脈產生器連結， 忒比較器之一輸入端與該電壓幫浦之輸出端連結，該比較 器之另一輸入端輸入一參考電壓，據此當該電壓幫浦之輸 出知的輸出電壓低於該參考電壓時，利用該比較器啟動該 知脈產生器驅動該電壓幫浦進行加壓動作，直到該電壓幫 浦之輪出端的輸出電壓高於該參考電壓時，再利用該比較 器關閉該時脈產生器，因此吾人只要程控該參考電壓，即 可控制該電壓幫浦之輸出端的輪出電壓以供一負載使用。 I 此外為避免該電壓幫浦關關次數過於頻繁而導致效 ，損失與減少壽命’由該電壓幫浦之輸出端 壓，其可先經過-分壓電路產生-第一回授電壓鱼一2 =杈電壓’再經過-通道多卫器（multiplexer)之輔助 二與該比較器連接’據此當該第一回授電壓低於該參考 2時，利用該比較器啟㈣時脈產生器驅動該電壓幫浦 仃加歷動作，直到該第一回授電壓高於該參考電壓時， 利用該比較器關閉該時脈產生器，據此其可減少該電壓 7 1295875 ; 幫浦關關之頻率。 |邊ri · f燦正替換頁j 【實施方式】 兹有關本發明之詳細内容及技術說明，現配合圖式說 明如下： 請參閱「第3圖」所示，其為本發明之第一實施例， 本發明之電壓倍增電路，其包含一電壓幫浦10、一時脈產 生器20與一比較器3〇。 該電壓幫浦10具有一輸入端l〇a、一控制端l〇c與一 _輸出端l〇b。 該時脈產生器20與該電壓幫浦10之控制端10c連 接，其產生時脈訊號控制該電壓幫浦10的啟動或停止， 該電壓幫浦10之輸入端l〇a的輸入電壓Vcc，藉由該電壓 幫浦10之加壓於該電壓幫浦10之該輸出端10b產生輪出 電壓Vout。 該比較器30具有二輸入端30a與一輸出端30b，該比 較器30之輸出端30b與該時脈產生器20連結’該比較器 _ 30之一輸入端30a與該電壓幫浦1〇之輸出端10b連結， 該比較器30之另一輸入端3〇a則輸入一參考電壓Vref。 電路啟動時’該時脈產生器2〇會驅動遠電壓幫浦1 〇 不斷的加壓，以加壓該電壓幫浦10之輸出端1〇b的輪出 電壓Vout，而該電壓幫浦10之輸出端10b的輸出電壓V〇ut 不斷回授至該比較器3〇，直到當該電壓幫浦10之輪出端 10b的輸出電壓Vout高於該參考電壓Vref時，利用謗比 8 1295875 赢Ο雙繼頁 較器30產生訊铁β 壓/唬關閉該時脈產生器20,以停止驅動該電 的輸出電動作’此時該電壓幫浦10之輸出端i〇b ._ out會被一負載（圖未示）消耗而不斷降低， ::該電壓幫浦10之輸出端i〇b的輸出電壓V⑽t低於 時脈產:ref時，再利用該比較器3°產生訊號啟動該 y " 〇驅動該電壓幫浦10進行加壓動作，進而形 Vre/盾動作趣路’因此吾人只要程控該參考電壓^ 1295875 — ---- , IX. INSTRUCTIONS: PAGE TECHNICAL FIELD The present invention relates to a voltage multiplying circuit, and more particularly to a multiplying circuit with low loss and programmable output voltage. - [Prior Art], DC (Dc) is the most commonly used voltage source for electronic devices. In order to be suitable for electronic devices (or electronic components) with different driving voltages, DODC converters are generally used to change the voltage. Please refer to the "Picture" diagram, which is a commonly used DC-DC voltage converter, which includes a bucker l (bandgap), a voltage pump 2 (pumping CKT) and a voltage regulator circuit 3 ( Regulator), the user can select the characteristics of the component according to the required voltage supply; if the user needs the output voltage v〇ut of 7·2V and has the system voltage Vcc of 2·4ν~3·6ν, it can be selected降压 降压 降压 1 1 1 1 1 1 1 1 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压 降压7·2V output voltage V〇ut, and finally through the voltage regulator circuit 3 voltage regulation, can provide the required 7·2ν stable output voltage v〇ut, if the customer does not care about the slight voltage changes, then The voltage stabilizing circuit 3 can also be omitted. The voltage converter described above is stepped down by the buck 1 and then pressurized by the high-voltage voltage pump 2, so that the energy consumption is quite serious, so as shown in "Fig. 2", it has been developed. The system voltage Vcc is directly used as the source voltage of the voltage pump 2, and it is also assumed that the user needs the voltage of 7.2V and the system voltage Vcc of 2·4v~3·6 v, then only Need to use 3 times the voltage of the pump 2, and then 5 1295875 l-- > year and month to correct the replacement page. By stepping down and regulating the voltage regulator circuit 3, it can provide the required 7.2V stable β output voltage Vout, which can improve the operating efficiency of the voltage pump 2 and reduce the overall energy consumption. For example, when the operating voltage of the system voltage Vcc is wide, but it is necessary to directly use the system voltage Vcc as the source voltage of the voltage pump 2, if it is assumed that the output voltage Vout of 5·Ον is required, but has 2· When the system voltage Vcc is Ον~3·6v, when the system voltage Vcc=3. 0~3. 6v, use 2 times the voltage of the pump 2; when the system voltage Vcc=2.0~2·5ν, use the ® 3 Double voltage pump 2; when the system voltage Vcc=2· 5~3· Ον, the voltage pump 2 switches between 2 and 3 times, and then the output voltage is regulated by the step-down and voltage regulation of the voltage regulator circuit 3. Vout is stable at 5. Ον, although this mode of operation can be applied to a wide system voltage Vcc, when the system voltage Vcc is 2. 5~3. Ον, the voltage pump 2 will be between 2 and 3 times Switching, which seriously affects the conversion efficiency of its voltage. Obviously, the aforementioned DC-DC voltage converter can supply voltage according to the user's φ demand, but in the process of voltage conversion, it is inevitable that it needs to be stepped down to supply the voltage required by the load, which will cause unnecessary Energy loss. SUMMARY OF THE INVENTION The main object of the present invention is to provide a low-loss voltage multiplying circuit. A secondary object of the present invention is to provide a voltage multiplying circuit that can programmatically adjust the output voltage. 6 1295875 _ The present invention is a voltage multiplying circuit that can programmatically adjust an output voltage, and includes a pumping CKT, a CLK generator, and a comparator. The pump has an input end, a control end and an output end; the clock generator is connected to the control end of the voltage pump, and generates a clock signal to control the action of the voltage pump, so that the voltage is applied to the input end of the pump An input voltage is generated by the voltage pump to generate an output voltage at the output end; the comparator has a two-input terminal and an output terminal, the output end of the comparator is coupled to the clock generator, and the comparator One input terminal is connected to the output end of the voltage pump, and the other input end of the comparator inputs a reference voltage, according to which the comparison is made when the output voltage of the output of the voltage pump is lower than the reference voltage Starting the pulse generator to drive the voltage pump to perform a pressurization operation until the output voltage of the voltage output of the voltage pump is higher than the reference voltage, and then using the comparator to turn off the pulse generator The generator, so as long as we control the reference voltage, we can control the output voltage of the output of the voltage pump for a load. In addition, in order to avoid the frequency of the voltage switch being too frequent, the loss and the reduction of the life are caused by the output of the voltage pump, which can be generated by the voltage divider circuit first - the first feedback voltage 2 = 杈 voltage 're-pass-channel multiplexer (secondary multiplexer) is connected to the comparator 'According to this, when the first feedback voltage is lower than the reference 2, the comparator is used to start (four) clock generator Driving the voltage boosting action until the first feedback voltage is higher than the reference voltage, using the comparator to turn off the clock generator, thereby reducing the voltage 7 1295875; frequency. [Embodiment] The details and technical description of the present invention will now be described with reference to the following drawings: Please refer to "Fig. 3", which is the first embodiment of the present invention. For example, the voltage multiplying circuit of the present invention comprises a voltage pump 10, a clock generator 20 and a comparator 3. The voltage pump 10 has an input terminal l〇a, a control terminal l〇c and an _output terminal l〇b. The clock generator 20 is connected to the control terminal 10c of the voltage pump 10, and generates a clock signal to control the start or stop of the voltage pump 10, and the input voltage Vcc of the input terminal l〇a of the voltage pump 10, The output voltage 10out is generated at the output terminal 10b of the voltage pump 10 by the voltage boosting of the voltage pump 10. The comparator 30 has two input terminals 30a and an output terminal 30b. The output terminal 30b of the comparator 30 is coupled to the clock generator 20, and the input terminal 30a of the comparator _30 and the voltage pump 1 The output terminal 10b is connected, and the other input terminal 3〇a of the comparator 30 is input with a reference voltage Vref. When the circuit is started, the clock generator 2〇 drives the remote voltage pump 1 〇 to continuously pressurize to pressurize the voltage Vout of the output terminal 1〇b of the voltage pump 10, and the voltage pump 10 The output voltage V〇ut of the output terminal 10b is continuously fed back to the comparator 3〇 until the output voltage Vout of the wheel terminal 10b of the voltage pump 10 is higher than the reference voltage Vref, and the ratio is won by using the ratio 8 1295875 The dual-pager comparator 30 generates a signal voltage β/唬 to turn off the clock generator 20 to stop driving the output operation of the power. At this time, the output terminal i〇b._out of the voltage pump 10 is A load (not shown) consumes and continues to decrease. :: The output voltage V(10)t of the output terminal i〇b of the voltage pump 10 is lower than the clock production: ref, and the comparator is used to generate a signal by 3° to start the y. " 〇 drive the voltage pump 10 to pressurize the action, and then shape the Vre / shield action circuit 'so we only need to program the reference voltage
17可控制該電壓幫浦10之輸出端l〇b的輸出電壓 V_以供該負载（圖未示）使用。 ^ 月再參閱「第4圖」所示，其為本發明之第二實施例， 本餐明之倍增電路，其包含一時脈產生器20、-電壓幫浦 1〇、—通道多工器40、一比較器30與一分壓電路50。 該時脈產生器20與該電壓幫浦1〇之控制端10c連 接其產生時脈訊號控制該電壓幫浦10的啟動或停止， 該電壓幫浦10之該輸入端10a之輸入電壓Vcc，藉由該電 壓幫浦10之加壓於該電壓幫浦1〇之該輸出端10b產生輸 出電壓V〇ut。 該電壓幫浦10具有一輸入端l〇a、一控制端l〇c與一 輸出端1 〇b。 該時脈產生器20與該電壓幫浦10之控制端l〇c連 接’其產生不連續之時脈訊號藉以控制該電壓幫浦1〇的 啟動或停止，該電壓幫浦1〇之該輸入端10a之輸入電壓 Vcc ’藉由該電壓幫浦10之倍壓電路使該電壓幫浦10之 9 129587517 can control the output voltage V_ of the output terminal l〇b of the voltage pump 10 for use by the load (not shown). ^ Month, as shown in FIG. 4, which is a second embodiment of the present invention, the multiplication circuit of the present invention includes a clock generator 20, a voltage pump 1 , a channel multiplexer 40, A comparator 30 and a voltage dividing circuit 50. The clock generator 20 is connected to the control terminal 10c of the voltage pump 1 to generate a clock signal to control the start or stop of the voltage pump 10, and the input voltage Vcc of the input terminal 10a of the voltage pump 10 is borrowed. The output voltage V〇ut is generated by the output terminal 10b of the voltage pump 10 which is pressurized by the voltage pump 10. The voltage pump 10 has an input terminal l〇a, a control terminal l〇c and an output terminal 1 〇b. The clock generator 20 is connected to the control terminal l〇c of the voltage pump 10, which generates a discontinuous clock signal to control the start or stop of the voltage pump 1〇, and the input of the voltage pump 1 The input voltage Vcc ' of the terminal 10a is made by the voltage multiplying circuit of the voltage pump 10 to make the voltage pump 10 9 1295875
輸出端l〇b產生輸出電壓Vout ° 該比較器30具有二輸入端30a與一輸出端30b，該比 較器30之輸出端30b與該時脈產生器20連結，該比較器 30之一輸入端3〇a輸入一參考電壓Vref。 該通道多工器40具有一輸出端40b、一選擇端40c、 一第一輸入端40al與^一第二輸入端40a2 ’该通道多工器 40之輸出端40b與該比較器30之另一輸入端30a連接， 該通道多工器40之選擇端40c與該比較器30之輸出端30b 馨連接。 該分壓電路50具有一輸入端50a與一輸出端50b，其 輸入端50a到輸出端50b依序串連有一第一電阻1^、一第The output terminal 10b generates an output voltage Vout °. The comparator 30 has two input terminals 30a and an output terminal 30b. The output terminal 30b of the comparator 30 is coupled to the clock generator 20, and one input terminal of the comparator 30 3〇a inputs a reference voltage Vref. The channel multiplexer 40 has an output terminal 40b, a selection terminal 40c, a first input terminal 40al and a second input terminal 40a2'. The output terminal 40b of the channel multiplexer 40 and the other of the comparators 30 The input terminal 30a is connected, and the selection terminal 40c of the channel multiplexer 40 is singly connected to the output terminal 30b of the comparator 30. The voltage dividing circuit 50 has an input terminal 50a and an output terminal 50b, and an input terminal 50a to an output terminal 50b are sequentially connected in series with a first resistor 1^, a first
一連接點A、一第三電阻rc、一第二連接點B與一第二電 阻Rb，該分壓電路50之輸入端5〇a與該電壓幫浦1〇之輸 出端10b連接，該第一連接點A與該通道多工器4〇之該 第一輸入端40al連接，該第二連接點B與該第二輸入端 40a2連接，該分壓電路5〇之輸出端5〇b則接地。 Μ丹-併㈣15圖」所示，其為本發明該電壓幫 浦10之輸出端通的輸出電壓Vout、電壓幫浦10與時脈 =生器20之時序圖’如圖所示’其時間區間可分為Ti區 間（起始區間）、Ta區間與几區間；首先為Ti區間與Ta ^ ]電路啟動日守’該時脈產生器會驅動該電壓幫 ^斷的加壓，以增加該電壓幫浦H)之輸出端的輪 出電壓W，而該輸出端⑽的輪出電壓_經過料 1295875 9| lift正替換頁 壓電路50於該第1接點A產生-第-回授電壓= 於該第-連接點B產生第二回授電壓Vref2，該第一回授 電壓Vrefl與該第二回_電壓以必係與該輪出端議的 輸出電壓V〇Ut、該第-電阻Ra、該第二電阻Rb與該第三 電阻Rc具有： 之關係a connection point A, a third resistor rc, a second connection point B and a second resistor Rb, the input terminal 5〇a of the voltage dividing circuit 50 is connected to the output terminal 10b of the voltage pump 1〇, The first connection point A is connected to the first input end 40al of the channel multiplexer 4A, the second connection point B is connected to the second input end 40a2, and the output end of the voltage dividing circuit 5〇 is 5〇b Then ground. Μ丹-和(四)15图”, which is the output voltage Vout of the output terminal of the voltage pump 10 of the present invention, the timing diagram of the voltage pump 10 and the clock=the generator 20 is as shown in the figure The interval can be divided into Ti interval (starting interval), Ta interval and several intervals; firstly, the Ti interval and the Ta ^ ] circuit start the day guard 'the clock generator will drive the voltage to help the pressure to increase the The output voltage of the output of the voltage pump H), and the output voltage of the output terminal (10) _ passing through the material 1295875 9 | lift is replacing the page voltage circuit 50 at the first contact A to generate - the first feedback voltage = generating a second feedback voltage Vref2 at the first connection point B, the first feedback voltage Vref1 and the second return voltage are required to be related to the output voltage V〇Ut of the wheel, the first resistance Ra, the second resistor Rb and the third resistor Rc have:
Kef^V〇ut(R^R^^ 一開始該通道多A ϋ 40#、選擇該第二輸人端40a2為 通路’讓該第二回授電壓Vref2不斷回授至該比較器30， 直到當該第二回授電壓Vref2高於該參考電壓Vref時， 即利用該比較器30產生訊號關閉該時脈產生器2〇，進而 停止該電壓幫浦10之動作，且該比較器3〇同時產生訊號 改變該通道多工器40之通路，選擇該第一輸入端40al為 Φ 通路，此時該比較器30之輸入端30a係改為輸入該第一 回授電壓Vrefl ’然由於此時該第二回授電壓Vref2係小 於該第一回授電壓Vrefl，因此當該通道多工器40改為選 擇該第一輸入端40al為通路時，並不會使該比較器30的 狀態改變而產生時脈訊號。 接著為Tb區間，隨時間之經過該電壓幫浦1〇之輸出 端10b的輸出電壓vout會被負載（圖未示）消耗而不斷降 低，相對的該第一回授電壓Vrefl亦會不斷降低，直到當 1295875 I---—i . 9~|五f|正替M| 〇 該第一回授電壓Vrefl低於該參考電壓Vref時，此時該 . 比較器30即會產生訊號啟動該時脈產生器20驅動該電壓 幫浦10進行加壓動作，並同時改變該通道多工器40之通 路，使其選擇該第二輸入端40a2為通路，同樣的此時第 二回授電壓Vref2小於該第一回授電壓Vrefl，此時改變 該通道多工器40選擇該第一輸入端40al為通路，並不會 使該比較器30的狀態改變；如上所述，Ta區間與Tb區間 會不斷重複，即形成一循環動作。且可使該電壓幫浦10 ® 之輸出端的輸出電壓Vout保持在 之間。 因此吾人只要程控該參考電壓Vref、該第一電阻Ra、 該第二電阻Rb或該第三電阻Rc，即可控制該電壓幫浦10 之輸出端10b的輸出電壓Vout以供該負載（圖未示）使用。Kef^V〇ut (R^R^^ initially starts the channel A A 40#, selects the second input terminal 40a2 as a path 'to let the second feedback voltage Vref2 be continuously fed back to the comparator 30 until When the second feedback voltage Vref2 is higher than the reference voltage Vref, the comparator 30 generates a signal to turn off the clock generator 2〇, thereby stopping the operation of the voltage pump 10, and the comparator 3〇 simultaneously The signal is changed to change the path of the channel multiplexer 40, and the first input terminal 40a is selected as the Φ path. At this time, the input end 30a of the comparator 30 is changed to input the first feedback voltage Vrefl ' The second feedback voltage Vref2 is smaller than the first feedback voltage Vref1. Therefore, when the channel multiplexer 40 selects the first input terminal 40al as a path, the state of the comparator 30 is not changed. The clock signal is followed by the Tb interval, and the output voltage vout of the output terminal 10b of the voltage pump 1 随 is continuously reduced by the load (not shown), and the first feedback voltage Vrefl is also decreased. Will continue to decrease until 1295875 I----i. 9~|five|| When the first feedback voltage Vref1 is lower than the reference voltage Vref, the comparator 30 generates a signal to activate the clock generator 20 to drive the voltage pump 10 to perform a pressurization operation, and simultaneously change the channel. The path of the multiplexer 40 is such that the second input terminal 40a2 is selected as a path. Similarly, the second feedback voltage Vref2 is smaller than the first feedback voltage Vref1, and the channel multiplexer 40 is changed to select the first An input terminal 40al is a path and does not change the state of the comparator 30; as described above, the Ta interval and the Tb interval are repeated, that is, a cyclic action is formed, and the output of the voltage pump 10 ® can be made. The output voltage Vout is maintained between. Therefore, as long as the program controls the reference voltage Vref, the first resistor Ra, the second resistor Rb or the third resistor Rc, the output voltage of the output terminal 10b of the voltage pump 10 can be controlled. Vout is used for this load (not shown).
此外，如「第6圖」與「第7圖」所示，前述之第一 實施例與第二實施例，皆可在該電壓幫浦10之輸出端10b 後加裝一穩壓電路60(regulator)，該穩壓電路60係由比 較器、電晶體Q與電阻Rl、R2所構成，其可藉由調整電 阻R1、R2之大小，對輸出電壓Vout作最後之穩壓與降壓， 其可以提供負載（圖未示）更穩定之電壓供給；而第二實施 例中之第一電阻Ra、該第二電阻Rb與該第三電阻Rc，其 係可以採用半導體作成可程控調整之可變電阻，藉此調整 該第三電阻Rc，即可調整該電壓幫浦10之輸出端10b的 輸出電壓Vout之振盪幅度，而調整該第一電阻Ra與該第 12 1295875 二電阻Rb，則可改變該電缝 電編，因而可以符!二10之輸出端 整之需求。付5不同負載之需求，且達到程控調 如上所述’本發明不需經過降屢之程序 壓提供所需之輪出電-供負载 ρτ倍〜電 之能量損耗，且i更可以盘因而可以減少不必要 以改變輸出電屢 私控改變可變電阻之電阻值，藉 本發明之較佳實施例而已，並非用來限定 ί變化L:!、’即凡依本發明申請專利範圍所做的均 【圖式簡單說明】 . 蛊 第1圖，係習知DC〜DC電壓轉換器方塊圖。 第2圖，係另一習知DC-DC電壓轉換器方塊圖。 2發明第—實施例之DC'DC電壓轉換器方塊圖。 ί ^ t明第二實施例之DC—此電壓轉換器方塊圖。 弟5圖，係本發明第二實施例之時序圖。 第6圖，係本發明第一實施例加裝髓電路之方塊圖。 第7圖一係本發明第二實施例加裝穩壓電路之方塊圖。 【主要元件符號說明】 習知 降壓器 電壓幫浦 穩壓電路 Vout :輸出電壓 13 1295875 iMil™ v Vcc :系統電壓 . 本發明 A:第一連接點 B :第二連接點 Ra :第一電阻 Rb :第二電阻 Rc ··第三電阻 Vcc :輸入電壓 ® Vout :輸出電壓 Vref :參考電壓 Vrefl :第一回授電壓 Vref2 ··第二回授電壓 10 :電壓幫浦 10a :輸入端 10b :輸出端 φ 10c :控制端 20 :時脈產生器 30 :比較器 30a ·輸入端 30b :輸出端 40 :通道多工器 40al :第一輸入端 40a2 ·弟二輸入端 ‘1295875 9氣也1曰#正替換頁 。 40b ·輸出端 . 40c :選擇端 50 :分壓電路 50a :輸入端 50b :輸出端 60 :穩壓電路In addition, as shown in FIG. 6 and FIG. 7 , in the first embodiment and the second embodiment, a voltage stabilizing circuit 60 can be added after the output end 10 b of the voltage pump 10 ( The regulator circuit 60 is composed of a comparator, a transistor Q and resistors R1 and R2, which can adjust the voltages R1 and R2 to perform final voltage regulation and voltage reduction on the output voltage Vout. A voltage supply of a load (not shown) may be provided. The first resistor Ra, the second resistor Rb and the third resistor Rc in the second embodiment may be programmable by a semiconductor. The resistor, thereby adjusting the third resistor Rc, can adjust the oscillation amplitude of the output voltage Vout of the output terminal 10b of the voltage pump 10, and adjusting the first resistor Ra and the 12th 1295875 resistor Rb can be changed. The electric seam is electrically braided, so it can be used! Pay 5 different load requirements, and achieve the program control adjustment as described above. 'The present invention does not need to provide the required round-out power for the voltage of the load ρτ times to the electric energy loss, and the i can be more discable. Reducing the need to change the resistance value of the variable resistor by changing the output power, by the preferred embodiment of the present invention, is not intended to limit the variation of L:!, 'that is, according to the scope of the patent application of the present invention. [Simplified description of the diagram] . 蛊 Figure 1, is a block diagram of the conventional DC ~ DC voltage converter. Figure 2 is a block diagram of another conventional DC-DC voltage converter. 2 Block diagram of a DC'DC voltage converter of the first embodiment. ί ^ t illustrate the DC of the second embodiment - this voltage converter block diagram. Figure 5 is a timing chart of the second embodiment of the present invention. Figure 6 is a block diagram showing the installation of a medullary circuit in the first embodiment of the present invention. Fig. 7 is a block diagram showing the installation of a voltage stabilizing circuit in the second embodiment of the present invention. [Main component symbol description] Conventional buck voltage pump regulator circuit Vout: output voltage 13 1295875 iMilTM v Vcc: system voltage. The present invention A: first connection point B: second connection point Ra: first resistance Rb: second resistor Rc · · third resistor Vcc : input voltage ® Vout : output voltage Vref : reference voltage Vrefl : first feedback voltage Vref2 · · second feedback voltage 10 : voltage pump 10a : input terminal 10b : Output terminal φ 10c : control terminal 20 : clock generator 30 : comparator 30a · input terminal 30b : output terminal 40 : channel multiplexer 40al : first input terminal 40a2 · brother two input terminal '1295875 9 gas is also 1 曰#正换页. 40b · Output terminal 40c : Select terminal 50 : Voltage divider circuit 50a : Input terminal 50b : Output terminal 60 : Voltage regulator circuit
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