TWI295772B - System for monitoring and analyzing data - Google Patents

Description

1295772 IX. Description of invention:

L Inventor's Technical Field] I Related Application Cross-Reference This application is related to the following co-designated pending patent applications, title 5: “System and Method for Quality Inspection Data Capture” (Lawyer Memorandum 200314251- No. 1); "System and Method for Controlling Data Capture" (Lawyer's Memorandum No. 200314252-1); "System and Method for Generating a Triggering Provincial L Number" (Lawyer's Memorandum No. 200314512-1), all of which At the same time, it is proposed and incorporated into the reference. 10 FIELD OF THE INVENTION The present invention is a data analysis system and method. [Prior Art] BACKGROUND OF THE INVENTION When a higher level circuit integrated body is implemented on a single integrated circuit chip or a group of chips, 5 is related to monitoring or analyzing the internal operation of a wafer or related to the internal operation of the chip set. Increased complexity. One that assists in monitoring and analyzing aspects of the operation is set to a logic analyzer. A logic analyzer can be of any of several types, ranging from a simple PC plug-in card to a complex workbench mainframe that receives many high-performance insertion functions. 20 SUMMARY OF THE INVENTION The present invention is a system comprising: a monitoring system that monitors data provided on a bus and provides at least one signal as at least some of the data provided on the bus a function, a measure of performance of the at least some of the data adjusted based on the at least one signal; and a 1295772 analysis system, wherein the at least one figure simply describes the operation to perform the data on the bus The logical analysis of a signal ~, Yan Xu. Figure 1 illustrates an embodiment of a system for analyzing data. Figure 2 illustrates an embodiment of a monitoring system. Figure 3 illustrates an embodiment of the _ knife analysis system.

〇 Figure 7 illustrates an example of a computer system that can implement one or more embodiments of a logic analyzer. Figure 8 is a flow chart illustrating an embodiment of a method of analyzing an acquisition. [Embodiment] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 shows an example of a system that can be used to analyze data provided on a bus 12 for data acquisition or storage. System 10 includes a monitoring system 14 that provides one or more signals 16 through an analysis system 18 as a function of the data on bus bar 12. The monitoring system 14 also provides one or more other output signals 20 that indicate the performance of the data on the busbar 12. The monitoring system 14 can adjust the output signal 20 in response to the corresponding signal 16 provided to the analysis system such that at least some of the output signals 2 are associated with the signal 16. For example, the 16 signal may correspond to the enable signal, and the output signal 2 may correspond to an individual counter value (e.g., a multi-bit signal) that is incremented or added in response to the enable signal 16. The analysis system performs 25 lines of logic analysis on the data on the bus as a function of the signal 16 provided by the monitoring system 14. When 1295772 is used herein, the terms "," and "," and "," are used interchangeably to identify one or more information bits that can communicate from one element to other elements and communicate between the elements. By way of further example, the monitoring system 14 can include a plurality of plans 5 and/or configurations to determine whether one or more predefined performance conditions have been met based on the data propagated on the bus bar 12. For example, monitoring system 14 can be programmed to implement arithmetic operations, logic operations, and matching operations on a subset of the data on bus bar 12, as well as combinations thereof. Performance conditions can be planned and defined by writing to a related memory (not shown). The monitoring system 14 can provide one or more signals 16 as a corresponding multi-bit signal indicating the result of each performance condition monitored by the monitoring system. For example, the monitoring system 14 can set one of the corresponding bits in the signal 16 for each clock cycle to indicate that each of the conditions on the bus 12 is met. The analysis system 18 is configured to perform logic analysis associated with the signal 16 and to provide one or more trigger signals to control data capture from the busbar 12. For example, the analysis system 18 implements a state machine (e.g., Mealy or Moore) that transitions between states based on the performance conditions implemented by the monitoring system 14. Thus, when the performance condition is met, (1) the monitoring system 14 can incrementally count or track the system in response to the signal 16, thus adjusting the indication of the individual performance corresponding to the counter value 2, and (1) the individual signal 16 can be clocked. The cycle is set to enable logical analysis to be performed by the analysis system 18. Analysis system 18 can provide one or more trigger signals based on signal 16. By way of example, system 10, including monitoring system 14 and analysis system 18, can be implemented as hardware within a computer system. The analysis system 18 can be configured with two 7 1295772 program (PROG) vectors (e.g., through system addressable memory) that define the state and a set of possible state transitions associated with the analysis function being implemented. The analysis system 18 can also utilize the status branch to provide additional state transitions that can be based on the signal 16 and based on the current state of the state machine 5 implemented by the analysis system 18. The trigger signal can also be used to define a capture period for storing data from the busbar 12 (e.g., the trace data) based on the analysis of the data performed by the analysis system 1$ based on the number 16. For example, bus bar 12 receives congratulations from one or more of the integrated circuit chips or from anywhere within the associated device in which system 10 is implemented (e.g., a computer system). For example, bus bar 12 can operate as a synchronous bus bar structure configured to propagate multi-bit data from one or more predetermined locations in an integrated circuit in which system 1 is implemented. Additionally or alternatively, the bus bar 12 can receive data from other integrated circuits communicatively coupled to the bus bar 12, such as in a computer system, and from a combination of locations within the same integrated circuit. data. Those skilled in the art will appreciate and appreciate that many different methods and feed structures can be used to drive the busbar 12 with data. < An example of a feed structure (e.g., interface) for providing data to busbar 12 includes a bus interface module. These and other feed structures can obtain data from a computer system, such as from other bus structures (e.g., processor busses, PCI busses, etc.) or memory, and provide information to busbars 12. In a multi-processor, such as a multi-cell computer system, bus bar 12 may also include data from other cell boards, such as a latch structure coupled to a sink 1295772 stream 12 via a communication ground. In such larger systems, a plurality of systems 10 are implemented by a computer system, including one or more of such systems on a single integrated circuit. The busbar 12 can therefore be referred to herein as an observable bus or a debug bus, depending on the surrounding environment of the system 10. Figure 2 illustrates an example of a monitoring system 50 that can be used to monitor performance characteristics associated with data on a bus bar 52, such as an observable or debug bus. Monitoring system 50 can be implemented as part of a logic analyzer implemented in a computer system. The performance monitoring system 50 includes a plurality of subsystems (PMON/COUNTER 〇 and 卩)\4€^/(:0111^1 ugly 1 to ? 01^/(201^丁丑11州) 54, where; ^ is a positive number and N+1 marks the number of PMON/COUNTERS 54. PMON/COUNTERS 54 generally drives an output confluence 15 corresponding to one of the multi-bit output signals indicated on the TRIG_OUT-LIST 56. Output bus 56 may thus include N+1 bits, one bit associated with each PMON/COUNTERS 54. Each PMON/COUNTERS 54 may be implemented as a programmable J logic configuration, such as a programmable Logic device (PLD), a field programmable gate array, other hardware or a combination of hardware and software. Each 20 PM〇N/COUNTER 54 can be planned to implement one of the data on busbar 52. The operation or function of the partial or sub-range is selected. For example, each PMON/COUNTER 54 can implement a matching function with one or more selected data (e.g., up to all data) bits from the bus bar 52. PMON/COUNTERS 54 can also implement logic functions (such as inversion, 1295772 AND, OR, XOR, NOR, AND , a combination of XNOR and other logic functions and functions), arithmetic functions (eg, addition, subtraction, multiplication, division, etc.), and combinations of logical and arithmetic functions on one or more of the bits on bus 52. The address memory 58 is operatively associated with each of the 5 PMON/COUNTERS 54 to plan a desired operation or function to be performed associated with the data on the bus 52. The system addressable memory 58 can be stored by a system processor 70. Access and access by a related diagnostic tool (not shown), or other device capable of writing to the system addressable memory 58. The data plan in the 疋 疋 体 58 58 58 The specific operation or function performed by the individual 10 PMON/COUNTERS 54. In the example of Figure 2, PMON/COUNTER 0 is illustrated as including a status block 60 and a counter 62. The status block 60 is implemented on the bus 52. A performance condition on one or more of the selected bits, the condition may include performing an operation or function on the material, such as an arithmetic function, a logical function number 15, or a combination of logic and arithmetic functions. COUNTER 0 The particular logic and/or arithmetic functions performed may be planned based on a PROGJPMON-0 signal from the system addressable memory 58. The PR〇GJPM〇N_〇 signal may also be created on the data from the bus 52 to be implemented. The performance status 'such as by identifying individual addresses for such data. 20 For example, the PROG-PMON-0 signal may include one or more bits that set performance conditions (eg, logic function ports/or arithmetic functions) that are performed by the status block from the selection data from the bus bar 52. . For example, the status block 60 can include a status register having one bit associated with each bit on the bus 52. By setting the bit in the status register, 10 1295772, if one or more bits match the data on the bus 52, the status block can provide a consistent signal. The status block 6 provides a status signal (PM 〇 N 〇) 64 to the counter 62 based on the application of the function or operation of the data. The counter 62 can add a corresponding value to the counter or additionally increase the counter value based on the output material. When the performance conditions are met, the status block 60 sets its output 64 (e.g., a logic high for a clock period) corresponding to PMON ,, such as a pair or eve k-cycle. The status block 60 can perform performance conditions on each clock cycle or on other selected time intervals. For example, if the performance condition is met on the day of the circumstance, the status block 6〇 can maintain the PM0 〇 in the set state on the plurality of clock cycles. Alternatively, the status block 6〇 can trigger the PMON 0 output signal. Pm〇n 〇 corresponds to one of the output bus rows % that form TRIG-OUT-LIST. The output status signal PMON 0 also adjusts the performance measurements associated with the data being monitored by the status block. In the example of Figure 2, the counter 72 is based on I5 PMON 0 and adjusts its counter value based on whether the performance condition achieved by the status block 6 is in the - in the clock cycle. The counter (4) provides a PCOUNT signal, # having a measure indicating the performance monitored by the individual performance monitoring subsystem. For example, the pc 〇 UNT signal may have a value indicating the number of performance conditions achieved by the status block 60, such as during - having been captured or over a plurality of periods. Counter 62 can be reset when needed. For the purpose of simplification, it will be understood that each can be similarly configured as shown and described in relation to pm〇N/COUNTER 但, but other PMON/COUNTER 1 to PM〇N/c〇UNTER N The internal content 1295772 has been omitted from Figure 2. That is, each PMON/COUNTER 54 can be scheduled and/or configured to perform individual performance conditions that drive the associated counters based on whether or not the conditions are met. Each time a counter is adjusted based on a performance condition, a 1^^^ output from the individual PMON/COUNTER 54 is also set in the TRIGJ3UTJLIST on the bus 56 (e.g., for a clock cycle). Each of the N bits associated with the TRIG-OUTJLIST signal on the bus bar 56 is thus provided and on the bus bar 52 in accordance with the performance conditions achieved by the status block in each PMON/COUNTERS 54. One of the data selects some of the relevant performance. While 10 PMON/COUNTERS 54 has been described as programmable, it is also contemplated that one or more PMON/COUNTERS 54 can be hardwired for a fixed performance monitoring condition. System 50 can also include other general counters 66 that increment a counter value with each clock cycle (or at some other periodic interval) to provide a 15 reference COUNT signal. The value of counter 66 can be related to the counter from

The PC0UNT signals of 62 (and counters to other PMON/COUNTERS 54) are compared or evaluated to determine the frequency of individual performance conditions achieved by the status block 6 (and other PMON/COUNTERS 54 status blocks). Instructions. For example, processor 70 can use a counter to simultaneously execute instructions corresponding to a diagnostic tool. The value of counter 66 can also be used to control PMON/COUNTERS 54. Figure 3 illustrates an example of an analysis system 100 that can be used to logically analyze data that is provided on a multi-bit observable or debug bus. The analysis system 1 uses a memory 1 〇 2 that stores a mask 12 1295772 data 104 that defines one or more conditions for controlling the transition of a state. The memory 102 can also include status data 106 that defines the state and transition between the available states. For example, memory 1〇2 can be any type of system addressable memory (eg, a register array, such as a control and status buffer) that can be written, such as from an analysis implemented therein. One of the system systems of the computer system. Memory 1〇2 can also be read to drive state transitions based on TRIG-OUTJLIST. The analysis system 100 is a state machine 107. The transition between the plurality of available states is based on TRIG-OUT-LIST, which describes the performance characteristics of the data on the bus. Those skilled in the art will understand and appreciate the many different ways in which the analysis system 100 can be implemented to analyze the performance information provided in the TRIG-OUT-LIST signal. The analysis system 1 can include one or more status elements 108 that control the state machine 1〇7 transition from a current state (CURR-STATE) to a state of the next state. 15 CURR—STATE can include one or more bits (e.g., a three-bit value) that determines how the data being propagated on the bus (e.g., the debug bus) will be analyzed and captured. The sequence of possible states, the transition between states, and the functions performed by each of the conditional elements 108 can be planned as state transition vectors defined by the masking material 104 and the state data 106 in the memory 1〇2.

2. In the example of Figure 3, state element 108 is represented as CONDITION 1, CONDITION 2, and CONDITION Q, where Q is a positive integer (Q > 1) that labels a plurality of status branches that can be implemented for each state. And functions. For example, status element 108 corresponds to a status logic and status branch executed on TRIG_OUTJLIST to control state transitions of state machine 107. Status component] 3 1295772 108 uses a comparison block (for example, a comparison circuit) H〇 to implement their individual functions on the TRIG_OUT LIST based on the mask data 1 〇 4 read from the memory 〇2 . For example, the comparison block 11 of each status element 108 can implement a bit mask (or match) associated with the energy status data represented by TRIG-OUTJLIST. The comparison block 110 is thus matched based on a mask vector stored as a mask data 104 in each cycle. The vector in the mask data 1〇4 may be different for each comparison block 110. The mask data 104 can further be used to fix or mask the data during a capture period that can vary over a capture period 10, such as by utilizing different masking data for some or all of the available states. When the mask data for a given status element 108 matches TRIG_OUTJLIST, the status element provides a corresponding output to a selector 112 indicating that the status has been met (e.g., the vector is enabled). Each status element 108 provides an output to the selector 112. The selector 112 15 operates to identify the NEXT STATE of the state machine based on the output from the status element 1〇8. The status element 108 can be used as a layered element for controlling state transitions. For example, the status component 108 can function as a priority encoder that implements state transitions based on CURR-STATE and based on TRIG-0UT-LIST. As a status data 106 priority encoder, the selector 112 can set the next state based on which status element 108 is enabled and assigned to the priority of the individual status element 108. Thus, the status element 1 可 8 can operate as a separate status branch, which can be used to implement a predefined state transition of the state machine with respect to the TRIG_OUT_LIS T associated with the corresponding mask data 104 associated with each status branch. (eg pre-planned as status data 14 1295772 106). The selector 112 can receive an indication of the next state from the enabled status component 1 或者 8 or read data from the memory 102, indicated by the dashed line 112. By way of further example, Table I below provides a truth table representation of the possible state transitions that can be implemented by the status component 108 based on the results of the comparisons performed by the individual comparison blocks 110. The items in Table I correspond, for example, to the output of the three status elements log shown in Figure 3. For example, CONDITION 1 corresponds to a first or highest priority condition (eg, one, if, status), CONDITION 2 corresponds to a high priority condition (eg, one, otherwise if) and CONDITION Q corresponds to a minimum Priority status (e.g., 10 other) otherwise "state". The value of the output of each individual status element 108 thus indicates whether an individual vector (stored in mask data 104) is enabled (marked by a logic "1"). Or being turned off (by a logic, 〇,, annotated), such as by comparing the TRIG-OUT-LIST with the corresponding mask data 丨04 by the comparison block 110. In Table I, the letter ''X' is labeled one The "not important" state of 15 is associated with the individual output of the status element 108. When no conditions are met (e.g., all conditions are equal to 〇), selector 112 maintains its current condition. Those skilled in the art will appreciate and appreciate that many of the different ways in which the functions shown in Table I can be implemented to implement a state machine in a computer system, including hardware and/or software, are included in Based on this guidance.

20 Table I

Condition 1 Status 2 Status Q Result 0 0 0 Load CURR STATE 0 0 1 Load CONDITION Q NEXT STATE 0 1 X Load CONDITION 2 NEXT STATE 1 XX Load CONDITION 1 NEXT STATE 15 1295772 Selector 112 provides NEXTS TAT E information A status register 114 is provided. The status register 114 thus provides an indication of the current status as a CURR-STATE signal. As noted above, CURR_STATE can be used to select the next available state from the status data 106 and (optionally) redefine the conditional element 1 〇 8 for the current state of the state machine 107. System 100 can also include an occurrence system 116 operative to cause one or more of the status elements (e.g., CONDITION 1) 108 to be made prior to switching selector 112 to the next state of one of the status elements. Multiple matches or occurrences. For purposes of illustration, the example of Figure 3 assumes that the generation system 116 is only applied to CONDITION 1, although it may also be linked to other conditions of the analysis system 1 to utilize the occurrence requirements. The generation system 116 thus provides an enable signal 117 to the selector 112 indicating whether the status component (e.g., CONDITION 1) 108 has met a predefined number of occurrences. Therefore, the selector H2 can be selected to be assigned to the next state of CONDITION 1 only when, for example, the enable signal 117 indicates that the number of occurrences has been met. As an example, the generation system 116 includes a counter 118 that operates to count when the comparison block 11 of CONDITION 1 indicates that the corresponding mask vector is met. Counter 118 may, for example, track the number of occurrences during capture, or the number of occurrences of CURR-STATE. Memory 102 can provide a 20 value (0CC-VAL) to generation system 116. The value of OCC_VAL is defined by the number of times one or more occurrences of the mask data vector enable selector 112 associated with CONDITION 1 are required to load a state vector associated with CONDITION 1. The same or different occurrence values can be planned for different states of the state machine. The generation system 116 compares the OCC-VAL with respect to the value 16 1295772 provided by the counter 118 and provides an enable signal to the selector 112 on a comparison basis. The enable signal is masked to conceal a state vector associated with CONDITION 1 until the output of counter 118 conforms to OCC_VAL. Thus, until the occurrence requirements associated with CONDITION 1 have been met, the state below the state machine will correspond to one of the state vectors associated with one of the other status elements 108. Analysis system 100 also includes a trigger generator 120. Trigger generator 120 operates to generate TRIGGER 10 based on a CURR-STATE associated with a predefined FINAL STATE that can be stored in memory 102. Trigger generator 120 may also include additional logic to force the trigger generator to provide a TRIGGER number. Those skilled in the art will understand and appreciate the many different ways in which a TRIGGER signal can be generated, such as based on desired performance characteristics and design requirements. The system 100 can also include a delay system 122 operative to generate a TRIG-DELAY signal based on a 15 TRIGGER signal and a STOR-QUAL signal. As an example, delay system 122 includes logic to AND the TRIGGER signal with the inverted version of the TRIG-DELAY signal and the ST0R-QUAL signal. A counter 124 is enabled based on the output of the logic to increment its value, provided that the TRIGJDELAY 20 signal is not asserted and the ST0R-QUAL and TRIGGER signals are asserted (e. g., corresponding to a qualified trigger event). Delay system 122 compares the output of counter 124 with respect to a predefined counter value indicated on P〇ST__STORE. The POSTJSTORE value can be a predefined 17 1295772 value read from the corresponding system addressable memory 102 that is used to implement a desired trigger delay. The p〇ST_ST〇RE value can be planned, such as for a given capture period, with a defined trigger delay value, which sets a data capture point relative to a corresponding trigger event (eg, when a TRIGGER signal is presented) . 5 For example, a corresponding data capture system can capture a set of data stored in a capture buffer prior to a trigger event based on a minimum POST-ST0RE value (eg, P〇STST〇RE=〇). In such a scenario, the data capture system will shut down and stop storing data from the bus at a trigger event. Alternatively, the p〇ST-ST〇RE value can be set based on a maximum of 10 POST-STORE values to cause the data capture system to store all of the data after a trigger event. In this latter scenario, the capture buffer will fill the capture buffer with data from the bus at or after the start of a trigger event. Depending on the size of the counter 124, a POST-STORE value can also be set to store future data, such as by 15 reading data from the data capture system over multiple cycles after the trigger event and storing the data in memory. in. Another alternative is to store a set of data in a _capture window (or multiple windows) based on the P0STJST0RE value, which is located in any one or more of the uranium data capture schemes. Thus, the trig_delay message can be provided to a data capture system, along with a st〇r-qual signal, 20 to control the operation of the tributary capture system, such as described herein. Figure 4 illustrates an example of a logic analyzer 150. System 150 is used to retrieve data from a data bus 152. The bus bar 152 can receive data, for example, from one or more sources in an integrated circuit chip, or from anywhere in a related device or system, including the 18 1295772 body circuit from among other systems 15 . Those who are familiar with the art will understand and appreciate the shirts that can be used to move the bus 152 (4) and the county. A monitoring pure 154 interface monitor is provided for the secondary material on the S stream I52. The monitoring system 154 can include a plurality of monitors/counters that are scheduled and/or configured to determine whether a particular sex condition has been met based on the material being propagated on the bank 152. For example, monitoring system 154 can be configured to: arithmetic operations, logical operations, and matching knowledge, and combinations thereof, related to a subset of the data on bus 152. The monitoring system 15 provides a pair of multi-bit outputs (TRIG_OUT-LIST) indicating the results of each of the monitored performance conditions. The monitoring system 154 may, for example, present an output bit corresponding to one of the TIRG_OUT-LISTs for each clock cycle, indicating that one of the pre-determined subsets of one or all of the data bus 152 has been met. . The performance 15 condition can be planned and defined by writing to an associated memory 156. The associated memory 156 can be one or more system addressable memory blocks (e.g., an array of control and status registers) that can be scheduled by one or more planning (INPUT) signals. The ΙΝρυτ signal can be used to set the desired logic, matching and/or arithmetic operations to be performed by the monitoring system 154. The memory 156 can provide (e.g., the monitoring system readable) pR〇G-mon signal to each of the performance conditions monitored by the monitoring system 154. There may be blocks separate from one of the memories 156 that are associated with each performance condition that each monitoring system 154 is to evaluate. For example, corresponding blocks in memory 156 may be planned by an internal processor (e.g., via system addressable memory) or from an external device or system tool by writing to memory 156. Monitor the pre-determined address location of the individual performance monitoring circuits of 19 1295772 糸 154. The monitoring system 154 provides a TRIG-OUT- LIST signal to a quality inspection system 160 and to an analysis system 152. The TRIG_OUT_LIST signal can be provided as data on a multi-bit bus that includes individual outputs of the parent performance conditions monitored by the monitoring system 154 5 . For example, when a particular condition is met by the monitoring system 154, a bit (or a plurality of bits) corresponding to one of the TRIG-OUT-LISTs may be presented by the system 154 for a clock cycle. The performance status can be determined by writing to a related memory 156. Correlation memory 156 can be one or more system addressable memory blocks (e.g., an array of control and sinister registers) that can be scheduled by one or more planning (INPUT) signals. The INPUT signal can be used to set the desired logic, matching and/or arithmetic operations to be performed by the monitoring system 154. The memory 156 can provide (e.g., the monitoring system can read) the PROG-ΜΟΝ signal to plan 15 each of the performance conditions monitored by the monitoring system 154. There may be a separate block of memory 156 associated with planning the performance conditions that each monitoring system 154 is to evaluate. For example, the corresponding block in memory 156 can be written by an internal processor |J (e.g., via system addressable memory) or from an external device or system tool by writing to advance in memory 156. The determined address location, 20 is assigned to the individual performance monitoring circuitry of the monitoring system 154. Monitoring system 154 provides a TRIG-OUT JLIST signal to a quality inspection system 160 and to an analysis system 162. The TRIG_OUT_LIST signal can be provided as data on a multi-bit bus that includes individual outputs for each of the performance conditions monitored by the monitoring system 154. For example, when the particular condition implemented by the monitoring system 154 is met, the system 154 can determine a bit corresponding to one of the TRIG-OUTJJST (or several bits) for a clock cycle. The assertion of the corresponding bit in the TRIG-OUT-LIST signal may correspond to an increment-corresponding counter or some other amount of performance adjusted in an individual performance monitoring 5 circuit of the monitoring system 154. Thus, in this manner, the multi-bit output TiaG-OUT_LIST provides an indication of whether a particular condition is met in the data provided on the bus 152. Those skilled in the art will appreciate and appreciate that the monitoring system 154 can be programmed and configured to monitor any one or more of the conditions associated with the data on the bus 152. The Q-check logic 160 performs the matching and QA functions associated with the TRIG-OUT-LIST provided by the monitoring system 154. The QA system 160 provides a ST0R-QUAL signal to an associated data capture system 164 to identify if the data should be captured from the data bus 152. For example, the quality inspection system 160 can be programmed via a PROG-SQ signal, such as performing a quality check logic or matching function on a selected group or subgroup of 15 TRIG-0UT-LIST data. For example, the matching function implements a matchable masking function that determines whether data should be captured from the data bus at each clock cycle based on the result of the variable represented by TRIG_0UT-LIST §fl. As such, the matching function can provide an ST0R-QUAL signal to identify one or more patterns associated with the results of the performance conditions monitored by the monitoring system 154. The analysis system 162 is configured to perform internal logic analysis associated with the performance monitor TRIG-OUT-LIST data and provides a plurality of TRIGGER signals to control a capture period for capturing data from the bus 152. For example, the analysis system 160 can be implemented as a _ state machine (e.g., Mealy or Moore) that transitions between states based on performance conditions implemented by the monitoring system 154. As described herein, the individual data in the TRIG-OUT-LIST can be presented to the 5-clock cycle based on what logic analysis is performed by the analysis system 162 when the performance of the person is assessed. The analysis system 162 can provide one or more TRIGGER signals to the data capture system i64. The one or more TRIGGER signals can also be provided by Ding Xing 0 011 Ding 1 1 15 Ding Signal and 5 Ding 011 - (511 8 1 ^ Signals). Can be provided to the quality check logic block 158, as mentioned above. 10 The analysis system 162 can be configured as a vector (PROG-TRIG) (eg, planned by system addressable memory), which defines a group Possible conditions and state transitions associated with the analysis function being implemented. The analysis system 62 can also be based, for example, on the TRIG-OUT-LIST data and based on the current state of the machine being implemented by the analysis system 162. Usage status branch 15. Analysis system 162 can also control how data capture system 162 captures data associated with a triggering event. In a further example, analysis system 162 can be programmed (e.g., via a PROGJTRIG signal) to adjust with a trigger point. Timing of related data capture, such as when a TRIGGER signal is asserted. For example, the PROGJTRIG 20 signal can be used to set one or more items in system addressable memory (eg a register array or other memory to set a trigger delay value that is used to define a buffer before a trigger event occurs, or within a window that includes a trigger event Whether to store the data, the window can be changed, for example, based on the size of the buffer used by the data capture system 22 64 1 295772 or the size of the memory used to store the buffer used to store the data from the bus 152. The event or condition may occur when the analysis system 16 2 converts to the state of one or more programmable analysis systems that are designed to cause the 5 TRIGGER signal to be presented. For example, the state machine may include a FInaL STATE 'which enables the analysis system 162. A trigger signal is provided. Additionally, a predetermined number of occurrences of one or more occurrences of the condition may be requested prior to transitioning to a state under the condition. The data capture system 164 operates at least in part to Based on the 10 STOR-QUAL signal of the QC logic and based on the TRIGGER signal provided by the analysis system 162 To store data from bus 152. Data capture system 164 includes control logic that can be set to define the amount of data to be stored, the type of data to be stored, and how the data will be related to 1111 (3 (:^11 signal) For example, the control logic of the data capture system 164 can include a configuration to activate the data capture system 164 to store a set of data from the bus 152 in response to the hardware configuration of the STOR-QUAL signal and the TRIGGER signal. In a further example, the analysis system 162 can provide the partner signal as including a trigger signal and a trigger delay signal. A trigger delay signal 20 identifying the value of a particular number of bits before or after a trigger condition occurs is stored in data capture system 164. Data capture system 164 can provide its corresponding output signal (OUT) to associated memory, such as system addressable memory, which can be read by a system processor. Those skilled in the art will appreciate that many different parts of the system 150 can be used to input planning data and to output data from the system 15 1295755 different 31 type C memory structures (eg, scratchpad RAM' The reservoir and, (9), the quality inspection system 158, the transfer 150, including the monitoring system... 77 analysis system 162 and data capture system 164 (or at least part of it) can be cautious silver % ^ m, 4 main 5 10 15 a see as - application of the integrated circuit (ASI (> asic, is the integrated logic analyzer inside the m system. sT ° brothers quality inspection system 2GG - examples, which include multiple separations. For example , sub-electric_ can be a Bolin sub-circuit, a Boolean sub-circuit 0, a Boolean sub-circuit 1 to a Boolean sub-circuit P, where P is a positive integer and W represents the number of sub-circuits. Each sub-circuit operates to provide a corresponding The quality inspection signal, the basin is indicated on m, Q and Qp, as a function of the corresponding input sfl number, as the deduction - from nr \ ^ day is not on P0 to PN, which marks the number of quotes. The same or different. The signal Ρ0-ΡΝ can be defined for execution by each sub-circuit 202. The purpose of the forest operation is to use a variable. As described herein, the input signal PG leads to the quality inspection system 200 to indicate the value (10) of the individual performance conditions of the material on a related elevator row, such as one or more. Bits. It will be appreciated that the same signal P0_PN - or a plurality of - can be checked by more than one sub-circuit 202. This provides a possible cloth that can be executed by the quality check corresponding to the set of variables of «Ρ0-ΡΝ An increase of 20 sets of forest operations. For example, because more than one signal (for example, the call is provided to a different sub-circuit, individual Boolean operations can be performed simultaneously on the signal and the complement of the magnetic (or reverse) Because these signals only occur as a single input to the quality inspection system 200, the Boolean operation can be performed on each signal or on the complement (reverse) of the signal. 24 1295772 By way of example, Each sub-circuit 2〇2 can perform a corresponding Boolean operation by performing a match between the predefined bedding and the variables defined by the input signals supplied to the individual sub-circuits. Thus, the quality inspection signals qaqj to QP As per The sub-circuits vary in number 5 of the Boolean operation function performed on the individual variables. An accumulator 204 accumulates the quality inspection signals Q0, Q1 to QP to provide a corresponding cumulative product detection signal, which is indicated on the QUAL. It can be a single digit or a multi-bit value, which is changed based on individual quality inspection signals q〇, qi to QP. The memory 206 can also be provided to set or configure the quality inspection system. For example, memory 206 can be implemented as a system addressable memory (eg, an array of control and status registers). Memory 2〇6 can be programmed to set logic data 208' defined by subcircuit 2布2 is a Boolean operation performed on an individual variable defined by the corresponding input signal p〇_pN. For example, logical data 2〇8 may correspond to a vector of logic values used to mask the individual input signals 15 provided to each of the sub-circuits 2 〇 2 . The logic 208 can be configured to determine whether the value of the individual input signal matches a predetermined logical value of the logical data stored in the memory 2〇6. The memory 206 can also include enable data 21A to selectively enable each of the plurality of sub-circuits 202. The enabling data 21 can thus be set for each sub-circuit 20 202 to enable or disable the sub-circuit to control whether or not to perform a predetermined cloth associated with a subset of some or all of the input signals p〇_PN. Lin operation. The Boolean operation implemented by sub-circuit 202 can be used to fix a data capture period by planning logic data 208 and enabling data 2 to capture data capture over multiple cycles. Alternatively, memory 2〇6 can be re-planned during a capture period to change the Boolean operation performed by sub-circuit 202 over time. If the logical data 208 or the enabling data 210 is to be re-planned during a capture period, the program should be configured to accommodate the time to re-program the memory 206. 5 Memory 2〇6 can be programmed by, for example, using a system processor to address the corresponding memory address locations associated with logic data 208 or enabling data 210 to be scheduled. Those skilled in the art will recognize and appreciate other ways to plan memory 206, which may include, but is not limited to, configuration tools (eg, by a communication to a serial or JTAG interface of memory), or by Other 10 configuration tools or run scans. Figure 6 illustrates an example of a data capture system 250 that can be used to store data from a data bus (e.g., an observation or debug bus) 252. The data on bus 252 can be logically split to assist in storing different portions of the data. In the case of an 80-bit debug bus 252, the bus 15 may include bits [39: 0], while other portions of the bus may include bits [79: 40]. Each of the busbar sections can include any number of bits, and the vine row can be divided into any component parts that can include the same or different number of bits. The data capture system 250 provides the corresponding output from the busbar 252. A resource (e.g., a single or multi-bit data stream) 254, which may be provided to one of the associated memory 256 addressable memory ranges. Memory 256 can be implemented as a system addressable memory, such as a scratchpad memory, or other type of system memory in a computer system in which data capture system 250 is implemented. The data in memory 256 can also be read from and stored in a non-volatile storage device (not shown), such as, for example, FLASH memory, EEPROM or a hard disk drive. At least a portion of the data capture system 250 provides output data 254 based on a TRIG_DELAY signal (which determines how the data is correlated with a trigger event) and the STOR_QUAL signal. 5 Data capture system 250 includes control logic 258 that operates to control associated capture memory 260 to capture or read data from bus 252. Control logic 258 may include, for example, the configuration of the gates and other circuitry associated with capturing the tribute from busbar 252. In the manner of Joe, the control logic 258 can include a counter 262 that operates to control which data is read from the bus 252 and which data is written to the capture memory 260. Counter 262 can be implemented, for example, as a multi-bit counter (e.g., an 11-bit counter) that maintains a count value that controls what data is to be captured from data bus 252. Different portions of multi-bit counter 252 can be used to control different aspects of system 250. For example, a set of bits (e.g., least significant bits) from counter 260 may define the selected data on bus bar 252 to be captured by a memory module (e.g., buffer) 270 in capture memory 260. The address. Control logic 25 8 provides an address (ADDR) signal to capture memory 260 that defines the address of the corresponding data to be captured from a portion of bus 252 associated with memory module 270. 20 other sets of bits from counter 262 may be provided to a demultiplexer (DE-MUX) 268 which provides a set of output signals based on a set of counter bits from control logic 258. The multiplexer 268 operates to drive a corresponding portion of the capture memory 260 to store selected data from the data bus 252 in the associated memory module 270. For example, the demultiplexer 27 1295772 268 provides a consistent energy signal to one or more memory modules 270 based on control inputs from the control logic 258 that correspond to one or more bits from the counter 262 (eg, A portion of the largest significant bit) to selectively enable the memory module. When counter 262 is incremented, demultiplexer 268 will enable each memory module 270 in a sequence of five. The enabled memory module 270 is enabled to read data from the bus 252 and is used to store the data in the memory module based on the address (ADDR) input. As noted above, counter 260 can provide an ADDR input, such as corresponding to a set of minimum significance bits, which is sufficient to encode the amount of data that is propagated on bus 252. The hexon board set 270 provides a corresponding multi-bit input to output multiplexer (MUX) 272. The multiplexer 272 can also be controlled by a control signal from the control logic, such as corresponding to some counter data, which corresponds to one or more bits from the counter 262 (eg, one of the most significant bits) . Control logic 258 can provide the same or different control signals to multiplexers 272, 15 and demultiplexer 268. Multiplexer 272 provides an output data signal 254 based on which memory modules 270 are enabled during a given clock cycle. The output data signal 254 can thus be written to the system addressable memory 256 and accessed via an associated processor for further analysis or for other functions within the computer system (eg, error control) ). A bead control block 264 can be programmed via a DEPTH signal (e.g., stored in an associated system addressable memory) to control the capture depth. The capture depth can, for example, set which portion of the bus bar 260 will store the data for each storage event. For example, in a meta-stream, the capture depth can be set to 8 bits (and it is possible to set which 28 1295772) to capture for each eligible storage event. By planning the dEPTH signal to a value, the data capture system 250 can be selectively configured to operate in a first mode that stores less data, but at a deeper extent on a bus, by The way to capture from a larger portion of the bus (eg, the entire bus 5) 252. In a second mode, data capture system 250 can store more data samples in memory 256, but for a smaller portion of bus 252 (e.g., half). The amount of data normally stored will vary depending on the size of the memory 256 with respect to the depth of capture. Those skilled in the art will appreciate and appreciate that other depths of capture may be implemented by depth control block 264. The control logic 258 can also include a delay block 260 that controls when data is to be captured in relation to a trigger delay (TRIG-DELAY) signal. For example, control logic 258 receives a TRIGJDELAY signal from an associated delay system (eg, 'delay system 222 of FIG. 6'). The TRIGJ3ELAY signal can be a unit value that identifies a predetermined number of storage events (eg, 15 ST〇R). -QUAL signal based) When the trigger signal associated with an assertion has occurred. The TRIGJDELAY signal can be a multi-bit signal. The associated delay system provides a TRIG-DELAY signal to control the data to be stored in relation to a trigger event. Width, such as described above in connection with Figure 6. For example, a planable associated delay system can be implemented to implement a storage window from a bus 252 after a trigger event or overlap with a trigger event prior to a trigger event. As a result of the above, a triggering event may occur in response to entering a final trigger state machine, such as in response to one or more conditions of uploading seven data in the bus 252. Thus, the data capture system 250 Operation to capture and store data from the data bus 252 in response to the 29 1295772 STOR-QUAL signal, as long as TRIG- The DELAY signal is not asserted. For example, when the TRIG-DEL AY signal is asserted, the control logic 25 can control the system 250 to shut down and stop storing data from the bus 252, effectively stopping a capture period. Figure 7 illustrates a block diagram An example of a computer system is illustrated, 5 which may be implemented by one or more logic analyzers, such as those shown and described herein (e.g., Figures 1-6). The computer system 300 of Figure 7 is illustrated as a distribution. A memory multiprocessor system, although a single processor system may also utilize a logic analyzer. System 300 includes a plurality of cells 302 respectively indicated on CELL 1, CELL 2 to CELL, where Μ is greater than or equal to one. An integer number of the number of labeled cells. A parent cell 302, which can be implemented as a cell, is communicatively coupled to other cells via an interconnect 304 such as a backplane or latch structure. 304 can be implemented as an application specific integrated circuit (asic). In the example of Fig. 7, logic analyzer 306 is implemented in interconnect 3〇4; that is, a logic analyzer is in a first interconnect and two The logic analyzer is in the other 15 interconnects. Familiar Those skilled in the art will appreciate and appreciate that any number one or more of the logic analyzers can be implemented within interconnect 304 and in other circuits, including on integrated circuits in cell 302 or I/O subsystem 308. By way of example, each logic analyzer 306 is surfaced to a bus structure (eg, a bus pool) that can come from component 20 and other busbars associated with one or more cells 3〇2. The data of the structure is driven. Additionally, as will be apparent herein, each logic analyzer 306 can include addressable memory within system 300 that can be read by components on any associated cell 302 or Write. By way of further example, an I/O (input/output) subsystem 3〇8 is associated with each cell 302. The I/O subsystem 308 can provide an interface or way #30 1295772 to access an associated bus structure (e.g., a PCI bus structure) or other device coupled to the corresponding bus structure, such as through a corresponding switch. Connector (not shown). Those skilled in the art will appreciate and appreciate that a variety of different types of I/C) devices 308' can be accessed or accessed through the I/O subsystem 308. In addition, the 'interconnect 304 including a logic analyzer 306 can be coupled to other interconnects' which includes two logic analyzers to access other cell-based φ architectures, which include one or more other cells (not display). Other cell basis configurations can be similarly configured as shown and described in FIG. However, those skilled in the art will understand and appreciate that the system 300 can be implemented with any number of cells, any number or plurality of implemented logic analyzers. For the sake of simplicity, only the internal content is displayed for CELL 1, although the skilled person knows and appreciates that each of his cell 302 can be seen in a six-person manner. Alternatively, different configurations may be implemented in relation to different cells 302. Φ to CELL 1, the CELL 1 includes a cell controller 310 coupled to a cell memory subsystem 312 to a related buffer channel 3 / buffer network 314 may comprise a column of rows (eg An input queue and an output queue are provided to provide a smart buffer of requirements and responses between the memory subsystem 3 i 2 and the controller 3. One or more central processing units (c) connected to the system 310 to access the memory subsystem 312. Each ye may include an associated cache H (not shown) for storing data for cpu local storage. Access to the 5 Replica Subsystem 312 is not required. In the configuration shown in Figure 7, the CPU 316 and the 1/〇 Subsystem 3〇6 can each be considered to operate through the control 31 1295772 system. The device 310 accesses the memory access device of the data in the memory subsystem 312. The controller 310 can include a firmware, a configuration and status register (CSR), and a memory for accessing the memory subsystem. The access queue of data in 312. Memory subsystem 312 can include any number of one or more memory modules including one or more DIMM or SIMM memory devices.

10 15

20 When the data is accessed by CPU 316 and/or I/O subsystem 306, the controller or other structure can drive some or all of the selected data to the observation sink associated with one or more logic analyzers 306. row. The logic analyzer 3〇6, in turn, monitors the performance of the data on the associated observation bus, analyzes the data based on the performance-related performance, and captures the data based on the quality of the bus. The logic analyzer is further achievable - a state machine that includes one or more conditions that control how state transitions have been performed during data capture, as described herein. It will be further appreciated that the data can be initialized and controlled by the instructions executable by the computer executing in one or more CPUs 3i6 - or during the data capture period of the plurality of logic analyzers 306. Alternatively or additionally, the capture period can be initiated and controlled by a tool or a diagnostic aid. A guard or a diagnostician can be internally executed in the -CPU 316, or externally made into a thin section of the system. Those skilled in the art will understand and appreciate the many different implementations of logical analysis that can be used in computer systems to tuck in other types of complex electrical and computer systems (such as routers and other communication devices). Based on the guidance included. In view of the foregoing structural and functional characteristics, the specific method will be referred to in Figures 5 and 6. It should be understood that the action described in the 'description' may occur in a different order and/or concurrent with other actions in its 32 1295772. Furthermore, 'Asian Africa requires all the features described to implement a method. It should be further understood that the following method can be implemented in a hardware (such as a logic gate, such as a transistor, a digital signal processor, or an application-specific integrated circuit), and software 5 (for example, executing on one or more processors) In the executable instructions), or in any combination of hardware and software. Figure 8 illustrates an example of a method 300. The method 300 includes generating at least one of aiU tigers as indicated on 31 相关 associated with at least one performance condition associated with a corresponding material on a bus. An indication of the performance of the corresponding 1 mussel material is adjusted based on at least one signal. At 320, a trigger signal is provided as a function of at least one of the signals. At 330, the data from the bus is captured based on the trigger signal. What has been described above is an example of the invention. It is to be understood that it is not possible to describe a conceivable combination of elements or methods for the purpose of the present invention. It is to be understood that a person skilled in the art will appreciate that many further combinations and modifications of the invention are possible. For example, any number of one or more logic analysis systems can be implemented in an existing ASIC, and any number of such ASICs can be integrated into a computer system. Accordingly, the present invention is intended to embrace such modifications, modifications, and variations thereof. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates an embodiment of a system for analyzing data. Figure 2 illustrates an embodiment of a monitoring system. Figure 3 illustrates an embodiment of an analysis system. 33 1295772 Figure 4 illustrates an embodiment of a logic analyzer. Figure 5 illustrates an embodiment of a quality inspection system. Figure 6 illustrates an embodiment of a data capture system. Figure 7 illustrates an example of a computer system that can implement one or more embodiments of a logic analyzer. Figure 8 is a flow chart illustrating an embodiment of a method of analyzing an acquisition. [Main component symbol description]

10...system 107...state machine 12...busbar 108...status component 14···monitoring system 110···comparison block 16...signal 112...selector 18...analysis system 114...state register 20...output signal 116 ...generation system 50...monitoring system 117···enable signal 52...bus bar 118...counter 54...counter 120...trigger generator 56...output bus bar 122...delay system 58...system addressable memory 124...counter 62 ...counter 150...logic analyzer 64...status signal 152...busbar 70...processor 154···monitor 100···analysis system 156...memory 102···memory 158...logic block 104...mask Data 160...Quality check logic 106··Status data 162...Analysis system 34 1295772 164...Data capture system 264··200···Quality inspection system 266·. 202···Sub-circuit 268" 204...Accumulator 270" 206···Memory 300·· 208...Logic 302·. 210···Enable 304·250···Data Capture System 306·252... Bus 308·254... Data 310·256···Memory 312 · 258... System logic 314 · 260 316 · · · · capture memory depth 262 ... counter • • • demultiplexer delay memory module • •• • computer system cells membered " interconnection

••Logic Analyzer ••I/O Subsystem ••Controller ••Memory ••Buffer •CPU

35

Claims (1)

X. Patent application scope: Application No. 94143869 Application for revision of patent scope 96.10 15 1 · A system for monitoring and analyzing data, comprising: a monitoring system for monitoring data provided on a bus, and Providing at least one signal as a function of at least some of the information provided on the bus, a measure of performance of the at least some of the data adjusted based on the at least one signal; and an analysis system operative to perform The logical analysis of the data on the bus is used as a function of at least one signal. 2. The system of claim 1, wherein the analysis system provides at least one trigger signal that varies as a function of the at least one signal to control capture of data provided on the bus. 3. The system of claim 2, wherein the monitoring system provides the at least one tiger as a plurality of signals as a function of corresponding data provided on the bus, the analysis system executing the plurality of Signal related logic analysis to provide the trigger signal. 4. The system of claim 3, further comprising a data capture system operative to store data from the bus based on the trigger signal. 5. The system of claim 4, wherein the analysis system further comprises a trigger delay system, which provides a trigger delay signal based on the trigger signal and a product detection signal, and is defined according to the trigger delay signal A capture period. 6. The system of claim 5, further comprising: a quality inspection system, wherein the product inspection signal is provided as a function of at least one of the quality inspection conditions associated with at least one of the plurality of signals, The data capture system is configured to store data from the bus based on at least one of the product detection signal and the trigger delay signal. 7. The system of claim 2, wherein the monitoring system further comprises a plurality of performance monitoring subsystems, each of the plurality of performance monitoring subsystems presenting at least a portion of the data provided on the busbar The data is related to the relationship and provides a (four) status _ as a function of the material on the bus, the analysis purely performs logic analysis as a function of individual status signals, and its towel health monitoring subsystem Each of the further steps includes a counter associated with a counter value based on the basis of the job (4), each of the values of the plurality of performance monitoring subsystems being provided by each of the plurality of performance monitoring subsystems A measure of the performance of monitoring. 8. The system of claim 1, wherein the analysis system advances into a state; the brother το's implementation-trigger state machine, the trigger. The machine m is based on a signal to transition from a current state to one of a plurality of available states. 9. The system of claim 8, wherein the at least one of the status elements achieves a match associated with the at least one signal based on the current state of the state machine. 10. The system of claim 8, wherein the step comprises a generation system in which a plurality of filaments occur, and the towel is converted to a plurality of states in which the plurality of conditional conditions have been given. One of the previous ones must meet one of the more 1,295,772 status elements, wherein the occurrence system further includes a counter that provides one of a plurality of occurrences that have met a condition associated with one of the status machines of the state machine, when the indication occurs When the value of the number reaches a predefined value, the state machine enables a transition from the current state to one of the plurality of states of the five status branches. 38