1295424 九、發明說明： 【發明所屬之技術領域】 一種辅助基本輸入輸出系統(BI0S)除錯之方法，特別是指 一種利用互補金屬氧化物半導體(complementary Metal_〇xide1295424 IX. Description of the invention: [Technical field to which the invention pertains] A method of assisting the basic input/output system (BI0S) for debugging, in particular, a method of using a complementary metal oxide semiconductor (complementary metal oxide semiconductor)
Semiconductor Random Access Memory)記憶體輔助 BIOS 除錯 卡以運用於BIOS除錯之方法。 【先前技術】 φ 在習知之技藝中，m〇S研發階段最常用的方式即是將一 BIOS除錯卡女插於主機板上以顯示除錯碼，若是測試期間發 生問題，研發人員可透過除錯碼以了解問題的可能來源，進一 _ 步追查的核心所在。 如第1圖所示’其為先前BIOS除錯之流程圖，其步驟包 含： 提供一主機板(步驟S101)，其主機板具有一記憶體單元， 此記憶體單元係為-可程式可抹寫之記憶體，如：一電子可抹 馨寫程式化唯讀記憶體（Electrically & E聰ble Pr〇grammableSemiconductor Random Access Memory) The memory-assisted BIOS debug card is used for BIOS debugging. [Prior Art] φ In the traditional technique, the most common way to develop the m〇S is to insert a BIOS debug card on the motherboard to display the debug code. If there is a problem during the test, the developer can Debugging the code to understand the possible source of the problem, the core of the further tracing. As shown in FIG. 1 , which is a flowchart of the previous BIOS debug, the steps include: providing a motherboard (step S101), the motherboard has a memory unit, and the memory unit is - programmable Write memory, such as: an electronic can be written to write stylized read-only memory (Electrically & E Cong ble Pr〇grammable
Read Only Memory ; EEPR0M)或一可抹寫程式化唯讀記憶體 (Erasable Programmable Read Only Memory ; EPROM)； 提供- BIOS除錯卡，安插於主機板上(步驟§1〇2广其 BIOS除錯卡具有-顯示單元及—職用mQs，會在開機之後 寫入主機板之記憶體單元；以及 執行-開機階段工作並顯不除錯碼(步驟s i 〇 3)，在寫入測 式用之BIOS至記憶體單兀後，被寫入記憶體單元之Bi〇s會 輸出-除錯碼至mos除錯卡以顯示單元顯示，並執行與除錯 1295424 馬才、子應之㈤機階段工作，使測試人員了解目前測試情況。 判斷是否完成開機階段工作(步驟S104)，若為是，則結束 BIOS除錯卫作(步驟Sl()5)，若為否，則_執行—開機階段 工作亚顯示除錯竭㈣(步驟_)，赠重侧示錯誤之開機 ^又工作所對應之除錯碼，使職人員了解問題所在。 =是，若執行開機階段工作時發生異常狀況，如：當機以 致於而要手動重新開機，自動關機或自動重新開機等情況發 ，除錯碼會被消除而無法使測試人員知道錯誤的來源以至於 播法了解其問題之_所在，進而增加BIOS除錯流程的複雜 【發明内容】 有鑑於上述之缺失’本發明之目的在提供—種職除截 之方法/、可避免在BIOS除錯流程之中，除錯碼因異常當相 以致於而要手動重新職、自動職或自動重新開機等情況兩 /肖失進而使別式人員無法取得前次除錯流程之除錯碼。 基於上述目的’本發明提供—種以互補金屬氧化物半導靡 (CMOS)記憶體辅助基本輸人輸料統(刪)除錯之方法，係 提供-主機板與-BI0S除錯卡，此域板具有-記憶體單 兀’其為—可程式可抹寫記憶體，以及-CMOS記,_，益 具有一即時碼攔位、—錯誤碼欄位及-«完纽元，i CMOS __為—互補金騎化物半導魏機存取記憶體 (CMOS RAM)，其湘錢板之_電池供電赠其在關機之時 仍可儲存資料’再將-刪除錯卡安插於主機板上，其腦 1295424 除錯卡具有一顯示單元及一測試用m〇s，此測試用B腦备 在開機時先寫入主機板之記憶體單元以形成一主機板Βΐ〇/ 其用以控制主機板之電路及存取CMOS記憶體。 主機板BIOS在進行偵錯過程之中會執行一開機階段工 =，並將對應開機階段讀之-除錯碼在進行開機階段工作之 前儲存於即時碼攔位中以及輸出至BI〇s除錯卡以顯示單元顯 示其除錯碼，使測試人員了解現在所進行的開機階段工作，並 • 且於開機階段工作完成之後設定開機完成位元以表示開機運 作正常結束，並無異常情況發生。若是開機階段工作發生異常 狀況如BIOS資料設計錯誤時，則開機完成位元不會被設定以 表不開機並未完整運行，並且會重複顯示與其相對應之除錯 碼。然而，就算發生比較嚴重的情況如當機以致於需要手動重 新開機、異常自動關機或自動重新開機等情況，因利用CM〇s 記憶體之資料儲存特性，除錯碼不會隨著關機而消失。 不論前次開機是否運作完整，每次開機時BI〇s會檢測開 • 機完成位元是否被設定，其用以判斷前次的開機是否運作完 整，若是前次開機運作不完整，BI〇S會將即時碼攔位之數值 存入錯誤碼攔位，並於開機完成之後將錯誤碼攔位之儲存值輪 出至BIOS除錯卡以顯示單元顯示，以使測試人員能進一步了 解前次開機發生異常情況之問題所在。 因此利用此一 CMOS記憶體在關機之時仍可儲存資料之 特性，即使BIOS除錯流程中有不正常之自動關機情況發生， 儲存於CMOS記憶體之資料不會因此消失，測試人員可於再 次開機經由CMOS記憶體取得前次開機之除錯碼，大幅降低 1295424 BIOS除錯的複雜度。 為使對本㈣之目的’實作方法及其舰有進—步的了 解，茲配合圖示詳細說明如下·· 【實施方式】 請參照第2圖，其為本發明BI〇s除錯卡與CM〇s記憶體 之關係示意圖，其包含一主機板2〇〇，其具有一 cm〇s記憶體 響220及一記憶體單元210，此CMOS記憶體具有一即時碼攔位 22卜用以在BI0S除錯流程中儲存一除錯碼，一開機完成位 元223 ’在BIOS除錯流程中用以判定前次開機是否成功，及 一錯誤碼攔位222，在前次開機不成功時儲存即時碼攔位之一 數值；以及一 BIOS除錯卡1〇〇，此BI0S除錯卡1〇〇安插於 主機板200上，其包含一測試用BI〇SU〇及一顯示單元12〇， 其用以顯示除錯碼。 其中，測試用BIOS110會在除錯流程開始時先寫入記憶 馨 體單元210，以控制主機板2〇〇之電路與存取CM〇s記憶體 220 ’此CMOS記憶體220係為一互補金屬氧化物半導體隨 機存取記憶體（Complementary Metal-Oxide Semiconductor Random Access Memory，CMOS RAM)，其為利用主機板 200之一電池供電以維持資料儲存之一小量記憶體單元； 而記憶體單元210係為一電子可抹寫程式化唯讀記憶體 (Electrically & Erasable Programmable Read Only Memory » EEPROM)或一可抹寫程式化唯讀記憶體(Erasable pr〇grammabie Readonly Memory，EPROM)，以及顯示單元係為一液晶螢幕或是 1295424 七段顯示器。 請參照第3圖，其係為本發明BI0S除錯流程圖，其步驟 包含： 提供一具有一 CMOS記憶體之主機板（步驟S3〇1)， 係誕（、主機板20〇,其具有一 CMOS記憶體220,此CMOS 記憶體220具有複數個資料攔位，至少包含一即時碼棚位 221，一錯誤碼攔位222及一開機完成位元223。 提供一 BIOS除錯卡，安插於主機板上（步驟§3〇2)， 將BIOS除錯卡1〇〇安插於主機板2〇〇上，此bi〇s除錯 卡100具有一顯示單元120以及一測試用BI〇S11〇，此測 試用BIOS110之資料會先寫入記憶體單元21〇以形成一主 機板BIOS，用以控制主機板2〇〇之電路及存取cM〇s記 憶體220。 檢查開機完成位元是否已設定（步驟S303)，主機板 =I〇S會經由檢查開機完成位元的設定與否，判斷前次開機 是否完成，若為否，即主機板BI〇s會將即時碼攔位221 =數值儲存於錯誤碼_ 222巾（㈣S3()4)而後清除開機 το成位7L(步驟S3G5)，若為是，則主機板BI〇s直接清除 開機完成位元（步驟S3〇5)。 么儲存一除錯碼並執行一開機階段工作（步驟 S306)，主 機:反B^)S會先執行開機階段工作，並在其開機階段工作 執行之如先儲存對應開機階段工作之除錯碼於即時碼攔 位221中，同時輸出至BI0S除錯卡1〇〇以顯示單元12〇 顯示其除錯>6馬。 1295424 判斷是否完成開機階段工作（步驟S307)，在完成開機 階段工作後，主機板BIOS會判斷開機階段工作是否完整 的運行結束；若為否，則進行儲存一除錯碼並執行一開機 階段工作步驟（步驟S306)，顯示錯誤之開機階段工作所對應 之除錯碼’使測試人員了解問題所在；若為是，則設定開機 完成位元（步驟S308)，以表示開機階段工作已被完整的運 行則無發生錯誤。 響最後，顯示錯誤碼欄位之數值（步驟S3〇9)，主機板 BIOS會輸出錯誤瑪搁位222之數值至bios除錯卡1〇〇， 並以顯示單元120顯示，此錯誤碼攔位222之數值即為前 次開機失敗或當機時最後儲存之除錯瑪。 由上述可知，測試人員在BIOS除錯流程中可直接從 BIOS除錯卡之顯示單元立即取得除錯碼，即使在除錯流程 中發生異常當機或自動關機，仍可利用CM〇s記憶體儲存 資料的特性於再次開機之後取得前次開機時最後儲存的除 _ 錯碼，使測試人員知道發生異常狀況的地方，進而追查問 題的來源所在。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍 内，當可作各種之更動和潤飾，因此本發明之保護範圍當後附 之申請專利範圍所界定者為準。 、 1295424 【圖式簡單說明】 第1圖係先前BIOS除錯之流程圖； 第2圖係為本發明BI〇s除錯卡與cm〇s記憶體之關係示音 圖；以及 、思Read Only Memory; EEPR0M) or Erasable Programmable Read Only Memory (EPROM); Provide - BIOS debug card, install on the motherboard (step §1〇2 wide its BIOS debug) The card has a - display unit and a job mQs, which will be written to the memory unit of the motherboard after booting; and the execution-boot phase works and displays the error code (step si 〇 3), and is used in the write test. After BIOS to memory unit, Bi〇s written to the memory unit will output - debug code to mos debug card to display unit display, and execute and debug 1295424 To make the tester understand the current test situation. Determine whether the boot phase work is completed (step S104), if yes, end the BIOS debug (step S1 () 5), if not, then _ execute - boot phase work In addition to the staggered (four) (step _), the weight on the side shows the wrong boot ^ and the corresponding debug code, so that the staff know the problem. = Yes, if the abnormal state occurs during the boot phase, such as: It’s time to reboot manually, since When the power is turned off or automatically restarted, the debug code will be eliminated and the tester will not be able to know the source of the error so that the broadcast method can understand the problem, and thus increase the complexity of the BIOS debug process. The lack of 'the purpose of the present invention is to provide - the method of cutting off the job / can avoid the BIOS debugging process, the debug code is due to abnormality, and must be manually re-employed, automatic or automatic reboot, etc. The situation two/discontinued causes the other person to fail to obtain the debug code of the previous debug process. Based on the above purpose, the present invention provides a complementary metal oxide semiconductor (CMOS) memory to assist the basic input and output. The system (deletion) debugging method is provided - the motherboard and the -BI0S debugging card, the domain board has - memory single 兀 ', which is - programmable rewritable memory, and - CMOS record, _, benefit With a real-time code block, - error code field and - «complete NZD, i CMOS __ is - complementary gold riding semi-guided Wei machine access memory (CMOS RAM), its Xiang Qian board _ battery power to give it The data can still be stored at the time of shutdown. The debug card is inserted on the motherboard, and the brain 1295424 debug card has a display unit and a test m〇s. This test uses the B brain to write the memory unit of the motherboard first to form a motherboard. Βΐ〇 / It is used to control the circuit of the motherboard and access the CMOS memory. The motherboard BIOS will perform a boot phase during the debugging process, and will read the debug phase corresponding to the boot phase. Before the stage work, it is stored in the real-time code block and output to the BI〇s debug card to display the debug code of the display unit, so that the tester can understand the current start-up phase work, and • set after the work in the boot phase is completed. The boot completion bit is used to indicate that the boot operation is normally completed, and no abnormality occurs. If an abnormal situation occurs during the startup phase, such as when the BIOS data is incorrectly designed, the boot completion bit will not be set to indicate that the boot is not fully operational, and the corresponding debug code will be displayed repeatedly. However, even if a serious situation occurs, such as a crash, such as manual restart, abnormal automatic shutdown or automatic restart, the debug code will not disappear with the shutdown due to the data storage characteristics of the CM〇s memory. . Regardless of whether the previous boot is fully operational, BI〇s will detect whether the open bit is set each time it is turned on. It is used to judge whether the previous boot is fully operational. If the previous boot operation is incomplete, BI〇S The value of the real code block is stored in the error code block, and after the boot is completed, the stored value of the error code block is rotated to the BIOS debug card to display the unit display, so that the tester can further understand the previous boot. The problem with an abnormal situation. Therefore, the CMOS memory can still store the characteristics of the data at the time of shutdown, even if there is an abnormal automatic shutdown in the BIOS debug process, the data stored in the CMOS memory will not disappear, and the tester can again Booting through the CMOS memory to obtain the debug code of the previous boot, greatly reducing the complexity of the 1295424 BIOS debug. In order to understand the purpose of this (4), the implementation method and the ship's understanding, the following is a detailed description of the following: [Embodiment] Please refer to Figure 2, which is the BI〇s debugging card of the present invention. CM〇s memory relationship diagram, comprising a motherboard 2〇〇, having a cm〇s memory ring 220 and a memory unit 210, the CMOS memory has a real code block 22 for In the BI0S debugging process, a debug code is stored, and a boot completion bit 223' is used in the BIOS debug process to determine whether the previous boot is successful, and an error code block 222 is stored in the instant when the previous boot is unsuccessful. One of the code block values; and a BIOS debug card 1〇〇, the BI0S debug card 1 is inserted on the motherboard 200, which includes a test BI〇SU〇 and a display unit 12〇, To display the debug code. The test BIOS 110 first writes the memory scent unit 210 at the beginning of the debugging process to control the circuit of the motherboard 2 and access the CM 〇 memory 220. The CMOS memory 220 is a complementary metal. a semiconductor semiconductor random access memory (CMOS RAM), which is a small amount of memory cells that are powered by one of the motherboards 200 to maintain data storage; and the memory unit 210 is Electro Scientific & Erasable Programmable Read Only Memory (EEPROM) or Erasable pr〇grammabie Read Only Memory (EPROM), and display unit It is a LCD screen or a 1295424 seven-segment display. Please refer to FIG. 3 , which is a BI0S debugging flowchart of the present invention, the steps of which include: providing a motherboard with a CMOS memory (step S3〇1), and the motherboard (the motherboard 20〇, which has a The CMOS memory 220 has a plurality of data blocks, and includes at least one real code booth 221, an error code block 222 and a boot completion bit 223. A BIOS debug card is provided, and is inserted in the host. On the board (step §3〇2), the BIOS debug card 1 is inserted on the motherboard 2, the bi〇s debug card 100 has a display unit 120 and a test BI〇S11〇, The data of the test BIOS 110 is first written into the memory unit 21 to form a motherboard BIOS for controlling the circuit of the motherboard 2 and accessing the cM〇s memory 220. Check whether the boot completion bit has been set ( Step S303), the motherboard=I〇S will determine whether the previous boot is completed by checking whether the boot completion bit is set or not. If not, the motherboard BI〇s will store the real code block 221=value. Error code _ 222 towel ((4) S3 () 4) and then clear boot το into position 7L (step S3G5) If yes, the motherboard BI〇s directly clears the boot completion bit (step S3〇5). If a debug code is stored and a boot phase operation is performed (step S306), the host: anti B^)S is executed first. During the booting phase, and during the booting phase, the debug code corresponding to the booting phase is stored in the real-time code block 221, and simultaneously output to the BI0S debug card 1〇〇 to display the unit 12〇 to display its debugging. >6 horses. 1295424 determines whether the booting phase is completed (step S307). After the booting phase is completed, the motherboard BIOS determines whether the booting operation is complete or not; if not, storing a debug code and performing a booting phase Step (step S306), displaying the error decoding code corresponding to the operation of the faulty booting stage, so that the tester knows the problem; if yes, setting the booting completion bit (step S308), indicating that the booting phase has been completed. No errors occurred during the operation. Finally, the value of the error code field is displayed (step S3〇9), and the motherboard BIOS outputs the value of the error bar 222 to the bios debug card 1〇〇, and displays it by the display unit 120, and the error code is blocked. The value of 222 is the last time the power is turned on or the last time it is stored. It can be seen from the above that the tester can directly obtain the debug code from the display unit of the BIOS debug card in the BIOS debug process, and can still use the CM〇s memory even if an abnormal crash or automatic shutdown occurs during the debug process. The characteristics of the stored data are obtained after the power is turned on again, and the last stored _ error code is saved, so that the tester knows where the abnormal situation occurs, and then traces the source of the problem. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 1295424 [Simple diagram of the diagram] Figure 1 is a flowchart of the previous BIOS debug; Figure 2 is a diagram of the relationship between the BI〇s debug card and the cm〇s memory of the present invention;
第3圖係本發明m〇s除錯之流程圖。 【主要元件符號說明】 步驟S101 提供一主機板 步驟S102 提供一 BIOS除錯卡，安插於主機板上 步驟S103 執行一開機階段工作並顯示除錯碼 步驟S104 判斷是否完成開機階段工作 步驟S105 結束BIOS除錯工作 100 BIOS除錯卡 110 測試用BIOS 120 顯示單元 200 主機板 210 記憶體單元 220 CMOS記憶體 221 即時碼攔位 222 錯誤碼欄位 223 開機完成位元 步驟S301 提供一具有一 CMOS記憶體之主機板 步驟S302 提供一 BIOS除錯卡，安插於主機板 步驟S303 檢查開機完成位元是否已設定 11 1295424 步驟S304 將即時碼欄位之數值儲存於錯誤碼欄位中 步驟S305 清除開機完成位元 步驟S306 儲存一除錯碼並執行一開機階段工作 步驟S307 判斷是否完成開機階段工作 步驟S308 設定開機完成位元 步驟S309 顯示錯誤碼欄位之數值 12Figure 3 is a flow chart of the m〇s debugging of the present invention. [Main component symbol description] Step S101 provides a motherboard step S102 provides a BIOS debug card, is inserted on the motherboard, step S103 performs a boot phase operation and displays a debug code step S104, determines whether the boot phase is completed, and the step S105 ends the BIOS. Wrong Work 100 BIOS Debug Card 110 Test BIOS 120 Display Unit 200 Motherboard 210 Memory Unit 220 CMOS Memory 221 Instant Code Block 222 Error Code Field 223 Boot Complete Bit Step S301 provides a CMOS memory The motherboard step S302 provides a BIOS debug card, and is inserted into the motherboard. Step S303 Check whether the boot completion bit has been set. 11 1295424 Step S304 Store the value of the instant code field in the error code field. Step S305 Clear the boot completion bit. The step S306 stores a debug code and executes a boot phase. The step S307 determines whether the boot phase is completed. Step S308 sets the boot completion bit. Step S309 displays the value of the error code field.