1294029 九、發明說明： 【發明所屬之技術領域】 本案係關於一種溫度感測電路及方法，特別是關於一種應用於 積體電路(ic)的溫度感測電路及方法。 【先前技術】 "人類日常生活中常常運用到溫度資料，例如空調系統、冰箱及 消防器材等。用來感測溫度的元件有多種，它可能是利用電阻的變 化、電動勢的產生、顏色的改變或體積的改變等各種方式來表現溫1294029 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a temperature sensing circuit and method, and more particularly to a temperature sensing circuit and method applied to an integrated circuit (ic). [Prior Art] " Temperature data such as air conditioning systems, refrigerators, and fire-fighting equipment are often used in human daily life. There are many types of components used to sense temperature. It may be used to express temperature by various changes in resistance, generation of electromotive force, change in color, or change in volume.
度的變化，而半導體材料其導電性受溫度的影響很大，因此以半導 體材料所構成的積體電路(1C)之導電性也會受到溫度的影響，由此 可利用積體電路特性隨溫度來改變的方式以製造感溫用^積體電 路。 、 A 肌销旭电格尸；r使用之溫度感測器，許多採用全客戶設計，較 常見之架動溫度❹彳器、參麵f路及類比至触轉換器(adc) 兀組成；其巾，溫度❹m通常是以特殊製程之垂直式雙極 互補式金氧半(CM〇s)製程之寄生性基底或水平式 ritic substrate or lateral bipolar 要生 將溫度感測器與參考‘‘ 由於溫度感測器在將溫度轉換至電壓戎帝、、* 甘t 線皆存在有相當曲率的問題，為了減^^二；；；：其^奐特性曲 的電路來做校正而造成晶#面似功 需要額外 量範圍超過觸輸出位元數^測 5 1294029 或偏流皆需元件尺寸與偏壓 :皆需花相當之時間與人力重新^整^電 程一微5或轉 電路或系統^之整合至為不和因此2=於超大型積體 缺失’，為發展本案之主_如何改善上述習知手段之 究，ΐΐίί ’ i案發明人鑑於上述習用技術之缺失，經来心之研 ;=_捨_，終麟_之『全數位溫度；= 【發明内容】 度的提出—種全數位溫度感測電路及方法，將溫 的=化，二再據以轉換為對應之數位值 路it 翏考源，使轉及校正變得簡單，進而縮小電 路所佔用的體積，並減少功率的消耗。 —it另Γ構?為··提出—種全數位溫度感測電路及方法，以 心憤g、正反11及比健的鮮化與模組化結構，達 念^触準化誠組化全客戶方式輯，可節省試 乂、=與人力，十分有利於A型積體電路與系統⑼整合此 数位溫度感測電路。 ，豕上，構想，本案之全數位溫度感測電路包括一溫度脈鐘遮 ^峨轉換單元及—計數器；射，溫度脈鐘鮮訊號轉換單元接 一，始步階訊號，並據以產生一脈鐘遮罩訊號，脈鐘遮罩訊號的 ，罩寬度隨溫度的改變而改變;計數器根據―第—參考脈鐘，用以 軲換脈鐘遮罩訊號的遮罩寬度成一對應之數位值。 μ ^為了根據溫度的變化產生脈鐘遮罩訊號，溫度脈鐘遮罩訊號轉 換單元包括一全數位延遲單元及一互斥或閘；其中，全數位延遲單 妾收啟始步階訊號，在經過一傳輸延遲時間後，輸出一結束步階 ❿號’結束步階訊號的延遲時間長度隨溫度的改變而改變；互斥或 1294029 ，係運算啟始步階訊號與結束步階訊號，據以輸出脈鐘 ϊίϊί度鮮減的鮮寬朗胁絲步階城的傳輪延 單元度f鐘遮罩訊號轉換單元之―較佳實施例中，全數位延遲 早凡係為一數位延遲線。 鐘鱗減觀單元之—她實施射，全數位 Ιΐί ί循環式延遲單元、—循環計數器及—脈數比較器； r^i- ’ ^魏式延群元接收啟始步階訊號，並據以產生一循環 心Η’/ΐ喊衝的週期隨溫度的改變而改變；循環計數11用以計^ 誠，並魅—脈波計數值；脈數妹_先設定_ 步i訊t數，用⑽祕波計數值與預設循環次數，並產生結束 =錄鐘鮮訊號轉換單元之—較佳實施例中，全數位 =括-數位循環式延遲單元、—循環計數器及—正反器；並 L it循環式延遲單元接收啟始步階峨，並據以產生一循環 H 的週麟溫度的改變而改變；彳練計數器具有複數個 最^用循環脈衝之週期數；正反器肋檢測循環計數器之 取阿位兀的轉悲，並產生結束步階訊號。 較佳者，上述之數位循環式延遲單元包括—@定 1位延舰：射，岐脈賊生雜倾始步階 ^及 =脈鐘，並據以產生-寬度固定脈衝；數位延遲線用以延遲^ ^疋脈衝-延遲時間並回授至目定脈衝產生器，據以輸出^ 衝’，Μ衝的週期對應於該延遲時間，並隨溫度的改變而改^。 較佳者，上述之固定脈衝產生器包括一第一正反器、一 反器'-寬度計數器、-寬度比較器及一或閘；其中一正^哭 ，收循環脈衝，肋檢賴環脈_上升緣；第二正反雜二 j訊號’用以制啟始步階訊號的上升緣；寬度計數器接收第二 乡考脈鐘，用以計數第二參考脈鐘的週期數，並產生 fii度比較器預先設定—預設寬度數值，肋比較寬度計iii 預设見度數值’並產生-清除致能峨；或_以產生寬度固定^ 7 1294029 全紐輯單元31在_單的情形下 ’當全數位延遲單元31係為數位延遲、線311睥 ιΓιί^Sckms Tmask * ί ^ίίίίϊΐ^ΐ 遮罩訊號^s 產生有足_罩寬度Tmask的脈鐘 一 闕第二圖’其為本案所提出之 〇 t ；ί1：ί 比較^314數ΪΪ壞ί延遲Ϊ元312、—循環計數器313及 以產生」循====== ^匕，314第一輸入端Ρ電連接於猶 j ❿ 脈波植值與預設循環次數一致時，產生結束步階訊號^田 請，參閱第四圖，其為本案所提出之溫度 】 =之第三較佳實關之電路魏方顧。在細财==^ 遲早元31包括-數位循環式延遲單幻12The degree of change, and the conductivity of the semiconductor material is greatly affected by the temperature, so the conductivity of the integrated circuit (1C) composed of the semiconductor material is also affected by the temperature, thereby making it possible to utilize the integrated circuit characteristics with temperature. The way to change is to manufacture a temperature sensing circuit. , A muscle sales Asahi corpse; r temperature sensor used, many of the use of customer-wide design, more common frame temperature device, parametric f-channel and analog-to-touch converter (adc) ;; Towels, temperature ❹m is usually a special process of vertical bipolar complementary MOS (s) process parasitic substrate or horizontal ritic substrate or lateral bipolar to generate temperature sensor with reference '' due to temperature The sensor converts the temperature to the voltage, and the *t Gan line has the problem of considerable curvature. In order to reduce the ^^2;;;: the circuit of the characteristic curve is corrected to cause the crystal surface The amount of power required to exceed the number of touch output bits is measured. 5 1294029 or the bias current requires component size and bias voltage: it takes a considerable amount of time and manpower to rectify the whole process, or the circuit or system is integrated into No and therefore 2 = in the absence of super large accumulations, in order to develop the main method of the case _ how to improve the above-mentioned conventional means, 发明ίί 'i case inventors in view of the lack of the above-mentioned conventional techniques, the study of the heart; = _ _, the end of the _ "all digital temperature; = [invention Contents] The introduction of the degree - the full digital temperature sensing circuit and method, the temperature = the second, and then converted into the corresponding digital value path it 翏 test source, making the turn and correction become simple, and thus reduce the circuit Take up the volume and reduce power consumption. -it another structure? For the ····························································································· The all-customer mode can save trials, = and manpower, and is very beneficial to the A-type integrated circuit and system (9) to integrate this digital temperature sensing circuit. , 豕,, conception, the full digital temperature sensing circuit of the present case includes a temperature pulse clock blocking conversion unit and a counter; the radiation, the temperature pulse clock fresh signal conversion unit is connected to the first step signal, and accordingly generates a The pulse clock mask signal, the pulse clock mask signal, the width of the mask changes with the change of temperature; the counter is used to change the mask width of the pulse mask signal into a corresponding digit value according to the "first" reference clock. ^ ^ In order to generate a pulse mask signal according to the change of temperature, the temperature pulse mask signal conversion unit comprises a full digital delay unit and a mutual repulsion or gate; wherein, the full digital delay unit receives the start step signal, After a transmission delay time, the length of the delay time of the output end step apostrophe 'end step signal changes with the change of temperature; mutual exclusion or 1294029, is the operation start step signal and the end step signal, according to The output pulse clock ϊ ϊ ϊ 鲜 鲜 鲜 鲜 鲜 鲜 鲜 的 丝 的 的 的 的 的 f f f f f f f f f f f f f f f f ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― The bell scale reduction unit - she performs the shot, all digits Ιΐ ί cyclic loop delay unit, - loop counter and - pulse number comparator; r ^ i - ' ^ Wei type extended group element receives the start step signal, and accordingly The cycle of a cycle of heart Η ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The secret wave count value and the preset number of cycles, and the end = recorded clock fresh signal conversion unit - in the preferred embodiment, the full digit = bracket-digit cyclic delay unit, - loop counter and - flip-flop; and L The iterative delay unit receives the start step 峨 and changes according to the change of the cycle temperature of the cycle H; the training counter has a plurality of cycles of the most used cycle pulses; the positive and negative rib detection cycle counter Take a bit of sorrow and turn to the end of the step signal. Preferably, the above-mentioned digital cyclic delay unit comprises -@定一位延船:射,岐脉脉生杂杂开始 step^ and =脉钟, and according to the generation of -width fixed pulse; digital delay line By delaying the ^^疋 pulse-delay time and feeding it back to the target pulse generator, according to the output, the period of the buffer corresponds to the delay time and is changed with the change of temperature. Preferably, the fixed pulse generator comprises a first flip-flop, a counter--width counter, a width comparator and a sluice; one of which is crying, receiving a loop pulse, and rib detecting the loop _ rising edge; the second positive and negative hybrid two j signal ' is used to make the rising edge of the start step signal; the width counter receives the second town clock, used to count the number of cycles of the second reference clock, and generate fii Degree comparator preset - preset width value, rib comparison width meter iii preset visibility value 'and generate - clear enable 峨; or _ to produce width fixed ^ 7 1294029 full comma unit 31 in _ single case 'When the full digit delay unit 31 is a digital delay, line 311睥ιΓιί^Sckms Tmask * ί ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^提出1; ί1: ί Compare ^314 number ΪΪ bad ί delay 312 312, - loop counter 313 and to generate "circle ====== ^ 匕, 314 first input terminal Ρ electrically connected to the j ❿ When the pulse wave planting value is consistent with the preset cycle number, the end step signal is generated. FIG four, which raised the temperature of the case of the third preferred real] = OFF circuit of Gu, Wei Fang. In fine money ==^ sooner or later Yuan 31 includes - digital cyclic delay single magic 12
Sst，域以產生一循環脈衝Scps，循㈡ ； mmnME sis 312 ’具—有複數個位凡’用以計數循環脈衝㈣之週期數；f 3一 15之貝料輸入端D §免定為高準位，脈鐘輸入端CLK電 =;元，當猶環計數器313之最高位元轉態時， 接著介紹產生卿崎Seps之電路，賴續參閱第五圖，其 1294029 為本案所提出之數位循環式延遽I开 :’數位循環式延遲單元j五圖 3121 ;其中，_脈衝產生器3122之第_:輸 產ί 疋Swidp;數位延遲線3121電連接於固定“ ί f定脈衝Swidp 一延遲時間並回授至固 °σ 3122，使再二人觸發產生寬度固定脈衝Swidp並進行延遲，攄 ，，環脈衝Scps ’猶環脈衝Seps的週期對應於延 ^Sst, the domain to generate a cyclic pulse Scps, according to (2); mmnME sis 312 'has - there are multiple bits of the number of cycles used to count the cyclic pulse (four); f 3-15 of the input of the material D § exempt Level, pulse clock input CLK == yuan, when the highest bit of the utah counter 313 is turned, then introduce the circuit that produces the Kiyosaki Seps, see the fifth picture, its 1294029 is the number proposed in this case The cyclic delay I open: 'digital cyclic delay unit j five figure 3121; wherein, the _ pulse generator 3122 of the _: transmission ί 疋 Swidp; the digital delay line 3121 is electrically connected to the fixed " ί f fixed pulse Swidp one The delay time is fed back to the fixed value σ 3122, so that the two people trigger to generate the width fixed pulse Swidp and delay, 摅,, the ring pulse Scps 'the cycle of the sigma pulse Seps corresponds to the delay ^
隨溫度的改變而改變。 J X 接著介紹纽寬度目鎌衝Swidp H請輔參閱第六 圖，其為本案所提出之@定脈衝產生器之電路魏方塊圖〔在第^ 圖1，固定脈衝產生器3122包括一第一正反器31221、一第二^ 反器31222、一或閘31223、一寬度計數器31224及一寬度比較器 31225 ;其中，第一正反器31221之資料輸入端D設定為高準位， 脈鐘輸^端CLK接收循環脈衝Scps，用以檢測循環脈衝Scps的上 升緣；第二正反器31222之資料輸入端d設定為高準位，脈鐘輸 入端CLK接收啟始步階訊號Sstart，用以檢測啟始步階訊號Sstart 的上升緣，或閘31223之第一輸入端電連接於第一正反器31221， 第二輸入端電連接於第二正反器31222，輸出端電連接於寬度計數 态31224之清除輸入端CLR，當第一正反器31221接收循環脈衝 Scps的上升緣或第二正反器31222接收啟始步階訊號Sstart的上升 緣，使或閘31223輸出轉態為高準位，解除寬度計數器31224之清 除輸入端CLR之清除功能，讓寬度計數器31224開始計數；寬度 計數器31224之脈鐘輸入端CLK接收第二參考脈鐘Sclk2,用以計 數第二參考脈鐘Sclk2的週期數，並產生一寬度計數值；寬度比較 器31225之第一輸入端P電連接於寬度計數器31224，第二輸入端 Q設定一預設寬度數值Μ，輸出端同時電連接於第一正反器31221 之清除輸入端CLR、第二正反器31222之清除輸入端CLR與寬度 計數器31224之致能輸入端ΕΝ，用以比較寬度計數值與預設寬度 11It changes with the change of temperature. JX then introduces the Width of the Swidp H. Please refer to the sixth figure, which is the circuit block diagram of the @定脉器器 proposed in this case. [In Figure 1, the fixed pulse generator 3122 includes a first positive The inverter 31221, a second inverter 31222, a gate 31223, a width counter 31224 and a width comparator 31225; wherein the data input terminal D of the first flip-flop 31221 is set to a high level, the pulse clock is input The terminal CLK receives the cyclic pulse Scps for detecting the rising edge of the cyclic pulse Scps; the data input terminal d of the second flip-flop 31222 is set to a high level, and the clock input terminal CLK receives the start step signal Sstart for Detecting the rising edge of the start step signal Sstart, or the first input of the gate 31223 is electrically connected to the first flip-flop 31221, the second input is electrically connected to the second flip-flop 31222, and the output is electrically connected to the width count The clearing input CLR of the state 31224, when the first flip-flop 31221 receives the rising edge of the cyclic pulse Scps or the second flip-flop 31222 receives the rising edge of the starting step signal Sstart, causing the output of the OR gate 31223 to be converted to a high level Bit, clear the width counter 31224 In addition to the clear function of the input terminal CLR, the width counter 31224 starts counting; the clock input terminal CLK of the width counter 31224 receives the second reference clock clock Sclk2 for counting the number of cycles of the second reference clock clock Sclk2, and generates a width meter The first input terminal P of the width comparator 31225 is electrically connected to the width counter 31224, the second input terminal Q is set to a preset width value Μ, and the output terminal is simultaneously electrically connected to the clear input terminal CLR of the first flip-flop 31221, The clear input terminal CLR of the second flip-flop 31222 and the enable input terminal 宽度 of the width counter 31224 are used to compare the width count value with the preset width 11