9〇7Υ8Γ~~-π 年月日修正本 1293761 九、發明說明： 【發明所屬之技術領域】 本發明係有關-種雜•理方法，特別是有關—種提昇儲存容量及 貝料錯誤容忍度的多重區域陣列之快閃記憶體管理方法。 【先前技術】 按，在現今的日常生活中，電子隨身攜帶產品已成為必須的生活用品 之一’如行動電話或行動助理(PDA)等，而電子隨賴帶產品皆具有快閃記 隐體，以用於存取電話薄、記事本、圖片或簡訊等檔案資料，因此要如何 的作出有_管理熱護，避免重要_案資料受損或遺失。 »、、:而，因此類的電子隨身攜帶產品在操作上皆是制很簡單的方式， 所以此產品的難㈣及觀彼此之間在記紐上有相#強烈軸關性， 因此§檔案讀有破損或遺失時，即可能破壞整個檔案結構，且沒有提供 播案回復之功此’如細者進行檔絲改寫人時，魏電源帽無法繼續 完成修改寫人之作業必須重新修改寫人，但f用無法提供回復修改前資料 之力月t* ¥致檔案儲存的貧料不具有完整性，另外當快閃記憶體進行標案 寫。或進他&抹除日$ ’其彳b費時間較長’對於其減案存取的需求反應 過慢，無法達到即時化健，進而造成對於使用者的檔案存取的反應較慢。 有鑑於此，本發明係針對上述之問題，提出一種多重區域陣列之快閃 記憶體管理方法，叫服傳驗閃記髓管财法之缺點。 【發明内容】，·〜 本發月之主要目的，係在提供_種多重區域陣列之快閃記憶體管理方 法’藉由將磁碟陣列⑽_ant Amy 〇f㈣哪，聊 的技術結合_記憶體，可大幅提高快閃記憶體的讀取速度及錯誤容忍度。 1293761 丨車月日修正本 法ΙΓΓ之另—目的’係在提供—種多重區域_之'_記憶體管理方 …D謝結合修_跡彻婉_義的齡 谷篁° 塊設置-標幟資料，肋區分此記憶區鱗舶的每—記憶區塊，再由一 控制處理器將儲存龍分縣n個片斷資料，接著控制處理器依據此標幡 資料將η個片斷資料分別對應儲存h個記憶區塊内。 根據本發明’-種多魏域_之,_記賴管理方法，此方法係使 用在將—儲_膽—她輸上，崎顺賴組具有至少 一記憶區塊陣列，此記憶區塊陣列具有n個記憶區塊，首先使每一記憶區9〇7Υ8Γ~~-π Year and month revision 1293761 IX. Description of the invention: [Technical field of invention] The present invention relates to a variety of methods, particularly related to improving storage capacity and error tolerance of shellfish Flash memory management method for multiple area arrays. [Prior Art] According to, in today's daily life, electronic carry-on products have become one of the necessary daily necessities, such as mobile phones or mobile assistants (PDAs), and electronically-owned products have flash-flash hidden bodies. It is used to access file data such as phone book, notepad, picture or newsletter. Therefore, how to make a management heat protection to avoid damage or loss of important data. »,,:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, When the reading is damaged or lost, it may destroy the entire file structure, and there is no such thing as providing a reply to the broadcast. If the person is rewriting the person, the Wei Power Cap cannot continue to modify the writing. The author must re-edit the writer. However, f can not provide a reply to the data before the modification of the force month t* ¥ to the file storage of the poor material does not have integrity, in addition, when the flash memory is written to the standard. Or enter him & erasing day $ </ br /> 彳 彳 费 费 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ In view of the above, the present invention is directed to the above problems, and proposes a method for managing a flash memory of a multi-area array, which is called a shortcoming of the method of verifying the flash memory. SUMMARY OF THE INVENTION The main purpose of this month is to provide a flash memory management method for a multi-area array, by combining the disk array (10)_ant Amy 〇f (four), the technology of the chat, the memory, Can greatly improve the reading speed and error tolerance of flash memory. 1293761 丨 月 修正 修正 修正 修正 修正 修正 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的 目的The data, the rib distinguishes each memory block of the memory area, and then a control processor stores the n pieces of information of the Long County, and then the control processor correspondingly stores the n pieces of data according to the standard data. Within a memory block. According to the present invention, a multi-wei domain _ _ _ management method is used in the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Has n memory blocks, first make each memory area
另外，本發明也可將快閃記憶模組劃分成至少一記憶區塊及至少一備 伤區塊’並且由-控做理器將此儲存資料分縣複數片斷資料，最後控 制處理器將每-個片斷資料儲存在記憶區塊巾並同時備份在備份區塊内。 底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明 之目的、技術内容、特點及其所達成之功效。In addition, the present invention can also divide the flash memory module into at least one memory block and at least one prepared block, and the stored data is divided into multiple pieces by the control processor, and finally the control processor will - A piece of data is stored in the memory block and backed up in the backup block at the same time. The purpose, technical contents, features and effects achieved by the present invention will become more apparent from the detailed description of the embodiments and the accompanying drawings.
【實施方式】 本發明係一種多重區域陣列之快閃記憶體管理方法，將應用在磁碟管 理的磁碟陣列（Redundant Array of Inexpensive Drives，RAID)技術使 用在快閃記憶體上，利用控制的方式在快閃記憶體上分割出複數儲存空 間，以取代傳統習知RAID的複數磁碟陣列，並且可使原有快閃記憶體大幅 提昇讀取速度及錯誤容忍度，此外本發明共有三種實施態樣，以下就說明 此三種快閃記憶體管理方法態樣。 請參閱第一圖及第二圖所示，首先係第一種方式的應用，在此實施例 6 1293761 厂m8~、一 年月日修正本 係將將—雌資料12儲存至—_記憶模組14上，而此快閃記憶模組14 具有-記憶區塊陣列16 ’此記憶區塊陣列16具有n個記憶區塊Μ，而在 "此快閃記憶模組12内設有一模組資料，以記錄此記憶區塊陣列14之各項 -訊’此模組f料包含有陣舰型、記憶區塊陣列數目及陣列儲存容量。 進行^驟S1G ’在母-記憶區塊π ^置—標幟資料，此標幟資料包含 此記憶區塊18的儲存容量及解位置，此標_料可提供區分此記憶區塊 陣列16内的每一記憶區塊18的位置及可儲存容量，接著進行步驟犯，由 •—控制處理器20將儲存資料1()分割為η個片斷資料22，再進行步驟su， 此控制處理H 2G _賴配對方式將n個脚諸分聊應儲存至η個記 隐區塊内如第一圖中所不，Α〇的片斷資料對應儲存到仙記憶區塊内，以 此類推。 第-種快閃記憶體實施態樣可將複數的快閃記憶模組14之儲存容量相 加成為-大容量的快閃記憶模組14’且因為儲存資料1()係平均的分佈在所 有的快閃記憶模組14内，可使此快閃記憶模組14的讀取速度大幅提昇， _也就是_記賴組14 _取速麟正比於快閃記賴組14的數目。 接著是第二種快閃記憶體實施態樣，請參閱第三圖及第四圖所示，此 方式同樣係將一儲存資料24儲存至一快閃記憶模組26上，此快閃記憶模 組26劃分成-記憶區塊28及一備份區塊3〇，此快閃記憶模組％上設有一 核』貝料用以3己錄此s己憶區塊28及備份區塊之各項資訊，此模組資料 3有儲存今里及儲存排序，其中此儲存排序係標示對應於快閃記憶模組 26中之存取順序者’第二種實施態樣的第—步驟係由一控制處理器犯 1293761[Embodiment] The present invention relates to a method for managing a flash memory of a multi-area array, which is applied to a flash memory by using a Redundant Array of Inexpensive Drives (RAID) technology. The method divides the plurality of storage spaces on the flash memory to replace the traditional RAID array of the conventional RAID, and can greatly improve the reading speed and the error tolerance of the original flash memory, and the invention has three implementations. In the following, the following three flash memory management methods are described. Please refer to the first figure and the second figure, first of all, the application of the first method, in this embodiment 6 1293761 factory m8~, one year and the next day, the department will store the female data 12 to -_ memory mode On the group 14, the flash memory module 14 has a memory block array 16'. The memory block array 16 has n memory blocks, and a module is disposed in the flash memory module 12. The data is recorded to record the contents of the memory block array 14 - the module contains the ship type, the number of memory block arrays and the array storage capacity. Performing a step S1G 'in the mother-memory block π ^ set - the flag data, the flag data includes the storage capacity and the solution position of the memory block 18, the label can provide a distinction between the memory block array 16 The position of each memory block 18 and the storable capacity are then subjected to the step, and the control processor 20 divides the stored data 1 () into n pieces of data 22, and then performs step su, which controls the processing of H 2G _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The first type of flash memory implementation can add the storage capacity of the plurality of flash memory modules 14 to a large-capacity flash memory module 14' and because the stored data 1() is evenly distributed at all In the flash memory module 14, the reading speed of the flash memory module 14 can be greatly improved, that is, the number of the flash memory group 14 is proportional to the number of the flash memory group 14. Followed by the second flash memory implementation, please refer to the third and fourth figures. This method also stores a stored data 24 onto a flash memory module 26, which is a flash memory module. The group 26 is divided into a memory block 28 and a backup block 3, and the flash memory module has a core % 料 用以 用以 用以 用以 用以 用以 用以 用以 用以 用以 s s s s s s s s Information, the module data 3 has a storage order and a storage order, wherein the storage order indicates that the first step of the second implementation aspect corresponding to the access sequence in the flash memory module 26 is processed by a control. Commitment 1293376
將此儲存資料24分割為複數片斷資料34 ’接著進行步驟幻8，再由控制處 理器32將每4随料财赫在航塊28巾綱時在此備份區 塊30内。 第二種制記實祕樣係贿全性為考量，在傳輸速率上係低於 第-種實施態樣的速率，在儲存資料24存取時，第二種實施態樣的陣列中 的記憶區塊28及備份區塊30會一起處理相同的資料。所以儲存資料％會 有相同的備份，即使有一區塊損壞時，也不會導致資料的流失。但其實第 φ 二種實施態樣與第一種實施態樣的讀取速率並不會相差很多，因為第二種 實施態樣在進行讀取係利用鏡像資料讀取方式從兩者之間取得其中之一的 資料。 接著是第三種實施態樣，請參閱第五圖及第六圖所示，此方式係將上 述第一種實施態樣及第二種實施態樣結合，此方式係將一儲存資料洲儲存 至一快閃圮憶模組38上，此快閃記憶模組38具有二記憶區塊陣列4〇及二 備份區塊42，每一記憶區塊陣列40具有m個記憶區塊44，而在此快閃記 # 憶模組38内設有一模組資料，以記錄此記憶區塊陣列40之各項資訊，此 模組資料包含有陣列類型、記憶區塊陣列數目、陣列儲存容量及陣列序號， 其中此陣列序號係標示對應的記憶區塊陣列4〇於此快閃記憶模組犯中之 存取順序者。 -魏進行步·驟S20，在每-記憶區塊44丨設置一標幟資料，此標織資 • 才斗内包含此記憶區塊44之排序位£及儲纟容量，此標幟資料可提供區分此 記憶區塊_ 40内的每-記憶區塊44的位置及可儲存容量，再進行步驟 1293761 —— 年月日修正本 S22 ’由一控制處理器46將此儲存資料36分割為m個片斷資料仙，再進行 步驟S24，此控制處理器46利用邏輯輯方式將m個片斷資料分別對應儲 • 存至此m個記憶區塊内，進行此步驟S24的同時，即時將儲存在m個記憶 脅 區塊内的m個片斷資料分別備份到備份區塊42内。 此第三種實施態樣係兼具第-種實施態樣及第二種實施態樣的優點， 在安全性及讀取速率上皆可大幅提昇，且所佔用的記憶區塊44及備份區塊 42係與第二種實施態樣相同。 • (Redundant Array of Inexpensive .Drives，刪）的技術結合快閃記憶體，可大幅提高快閃記憶體的讀取速 度及錯誤容忍度’進而提高快閃記憶體在使用上的可靠度，並且利用麵 技術可結合多個，_記髓，可大幅提高侧記憶體的儲存容量。 ▲以上所述係藉由實施例說明本發明之特點，其目的在使熟習該技術者 能暸解本發明之内容並據以實施，而非限定本發明之專利範圍，故，凡其 他未脫離本發明所揭示之精神所完成之等效修飾或修改，仍應包含在以下 Φ 所述之申請專利範圍中。 【圖式簡單說明】 \ 第一圖為本發明快閃記憶體之第-種實施態樣示意圖。 第二圖為本發明·_記憶體之第-種實施態樣流程圖。 第三圖為本發明快閃記憶體之第二種實施態樣示意圖。 第四圖為本發明‘_記鍾之第二種實施態樣流糊。 第五圖為本發明,_記憶體之第三種實祕樣示意圖。 第、圖為本發明快閃記憶體之第三種實祕樣流程圖。The stored data 24 is divided into a plurality of pieces of data 34' and then step Magic 8 is performed, and then the control processor 32 places each of the four items in the backup block 30 at the time of the navigation block 28. The second type of system secrets is considered as a whole, and the transmission rate is lower than the rate of the first embodiment. When the data 24 is accessed, the memory in the array of the second embodiment is stored. Block 28 and backup block 30 will process the same data together. Therefore, the % of stored data will have the same backup, even if there is a block damaged, it will not lead to the loss of data. However, in fact, the read rate of the first embodiment of the first φ is not much different from that of the first embodiment, because the second embodiment is obtained from the reading system by using the mirror data reading method. One of the materials. Following the third embodiment, please refer to the fifth and sixth figures. This method combines the first embodiment and the second embodiment, which stores a storage data. Up to the flash memory module 38, the flash memory module 38 has two memory block arrays 4 and two backup blocks 42, each of the memory block arrays 40 having m memory blocks 44, and The flash memory module 38 has a module data for recording information of the memory block array 40. The module data includes an array type, a memory block array number, an array storage capacity, and an array serial number. The array number indicates that the corresponding memory block array 4 is in the access order of the flash memory module. - Wei proceeds to step S20, and a flag data is set in each memory block 44. The labeling material includes the sorting position of the memory block 44 and the storage capacity, and the flag data can be Providing a distinction between the location and the storable capacity of each memory block 44 in the memory block _ 40, and then performing step 1237761 - the year, month, and day revision S22' is divided by the control processor 46 into the stored data 36 into m The segment data is sent to step S24, and the control processor 46 stores the m pieces of data in the m memory blocks by using the logic mode, and the step S24 is simultaneously stored in the m blocks. The m pieces of data in the memory threat block are backed up to the backup block 42 respectively. The third embodiment has the advantages of the first embodiment and the second embodiment, and can greatly improve the security and the reading rate, and the occupied memory block 44 and the backup area. Block 42 is identical to the second embodiment. • (Redundant Array of Inexpensive .Drives, deleted) technology combined with flash memory, can greatly improve the read speed and error tolerance of flash memory', thereby improving the reliability of flash memory in use, and use The surface technology can be combined with multiple, _ remembering the marrow, which can greatly increase the storage capacity of the side memory. The above description of the present invention is made by way of examples, and the objects of the present invention are understood by those skilled in the art, and are not intended to limit the scope of the invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described in the following Φ. [Simple description of the drawing] \ The first figure is a schematic diagram of the first embodiment of the flash memory of the present invention. The second figure is a flow chart of the first embodiment of the invention. The third figure is a schematic diagram of a second embodiment of the flash memory of the present invention. The fourth figure is the second embodiment of the present invention. The fifth figure is a schematic diagram of the third real secret sample of the memory of the present invention. The first figure is a third real-life flow chart of the flash memory of the present invention.
1293761 【主要元件符號說明】 12 儲存資料 14 快閃記憶模組 16 記憶區塊陣列 18 記憶區塊 20 控制處理器 22 片斷資料 24 儲存資料 26 快閃記憶模組 28 記憶區塊 30 備份區塊 32 控制處理器 34 片斷資料 36 儲存資料 38 快閃記憶模組 40 記憶區塊陣列 42 備份區塊 46控制處理器 44記憶區塊 48片斷資料1293761 [Key component symbol description] 12 Storage data 14 Flash memory module 16 Memory block array 18 Memory block 20 Control processor 22 Clip data 24 Storage data 26 Flash memory module 28 Memory block 30 Backup block 32 Control Processor 34 Clip Data 36 Store Data 38 Flash Memory Module 40 Memory Block Array 42 Backup Block 46 Control Processor 44 Memory Block 48 Clip Data