TWI292621B - Flash memory device and method of manufacture field of the invention - Google Patents

Description

1292621 17067twf.doc/r IX. Description of the Invention: [Technical Field] The present invention relates to a flash memory device and a method of forming the same. [Prior Art] The electrical EEPROM or flash memory has gradually become a substitute for hard disks, so Devices that are small in capacity, low in cost, and reduced in size to achieve miniaturization and speed of processing are sought after. U.S. Patent No. 5,050,125 discloses a non-volatile semiconductor memory having a series of flash memory memory arrays (shown in the cross-sectional view of FIG. 4) of each bit line, memory cell The size and area are defined by the width of the floating gate and the adjacent insulation zone (X direction of Figure 4) and the corresponding control gate and the adjacent insulation zone (Y direction of Figure 4). In other words, the overlapping areas are the floating gate and the control gate. The upper limit of the memory size reduction in each of these patents is approximately 4F2 to 5F2, and F represents the minimum pattern size or line width obtained by lithographic techniques in this patented process, and the minimum pattern size is now approximately 90 nm. And when the minimum width of the control gate and the minimum spacing of the adjacent control gates are both 1F, it is assumed that the minimum width of the floating gate and the minimum spacing of adjacent floating gates in a floating gate array are both about 1F. Therefore, each memory cell occupies at least 2F in the X direction and 2F to 2.5F in the γ direction. Increasing the overall density of the flash memory array is desirable, thus providing a flash memory whose memory cell size is not limited to the minimum line width obtained by the lithographic 1292621 17067 twf.doc/r printing technique. SUMMARY OF THE INVENTION Memory and its formation method, the first memory of the selective lithography process using the minimum line width further includes a gate oxide layer formed on the substrate. a plurality of the first plurality of floating gates having a plurality of second floating gates, wherein the two floating gates are continuously deposited, that is, each of the second floating gates is deposited, 'One> between the predetermined gates; a plurality of spacers, each spacer wall is deposited between each pair of adjacent first and second floating gates; and a plurality of connections

> In the control gate of the gate, the width of the wall and/or the second gate is less than the minimum line width. The above and other features of the present invention will be more fully understood and understood by the following description of the preferred embodiments. [Embodiment] FIG. 1 discloses a semiconductor combination 1G, which has a substrate conductor combination comprising a substrate 12 to constitute a transistor and a connecting member, and may be a ruthenium, osmium, tri-five compound substrate and other achievable An alternative material of the same function; a channel gate oxide layer 14 as a dielectric layer is formed between the substrate 12 and the formed device, and can be formed by chemical vapor deposition (CVD) or thermal growth procedures. Forming, for example, a tantalum oxide layer having a thickness of 50 to 1 Å (A); and a first polysilicon layer 16 formed over the gate gate oxide layer 14, for example by chemical vapor deposition or spin coating Forming method to form. As shown in FIG. 2, the deposited first polysilicon layer 16 is patterned to form 1292621 17067 twf.doc/r, which can be used as the first group of polysilicon gates 18 of the first group of floating gates, and the method can be known. ^1 Jing Hao process. In one embodiment, each polycrystalline gate 18 can be formed in a patterning step using a selective lithography process having a minimum line width (1F).

Figure 2 is a step-by-step disclosure of a spacer material layer 22 comprising a deposited layer of oxygen, tantalum or tantalum nitride to cover the first polysilicon layer 16 and the polysilicon gate 18 after engraving, and partially fill the channel thereof. 19 (the area between the polycrystalline turns 18 in the engraving step) to create a recessed channel 21 in the channel 19. / As shown in FIG. 3, the spacer material layer 22 in the channel 19 is etched to form a first spacer 2, and the first spacer 2 is adjacent to each polysilicon gate 18, and the adjacent first spacer 20 is Channel 24 is separated. An isotropic dry etching process can be used for the spacer material layer 22 to create a first spacer 2, each via 24, and particularly an etch channel 21 until the channel 24 is formed under the gate gate oxide layer 14. When the selected dry etch process is well reacted to the spacer material 22 rather than the polysilicon material, the via 24 formation process does not require a mask. Channel 24 can be narrower than the minimum line width (1F), and in one embodiment, channel 19 between polysilicon gates 18 can be wider than 1F, while channel 24 has a width that approximates width 1F of polysilicon gate 18. In one embodiment, the spacer material 22 comprises a tantalum oxide and a dry etchant comprising CHF3, (Twist and He etch chemistry. In another

In an embodiment, the spacer material 22 may comprise tantalum nitride and the Ar and CF4 etch chemistries are used during the dry etch process. X When the first polysilicon layer 16 is patterned to form a polysilicon gate 18 having a minimum line width, each has a space sufficient to accommodate a channel 24 and a pair of gaps 1292621 17067twf.doc/r

Channels 19 of the wall are formed, and each channel 19 is formed to produce a width greater than the minimum line width by the lithography process. As will be described later, each of the vias is used to form a second set of polycrystalline gates 18a (Fig. 6) between the polycrystalline gates 18. In order to reduce the spacing of the polysilicon gates, the channel 19 can be twice as large as the most enthalpy, and the lithography technique can precisely form the channel 19. In the implementation, the width of each channel 24 is less than or equal to the minimum line width, and #中中为敢小线1 makes it more selective to match the width of the polycrystalline stone gate 18. In one embodiment, the use of a selective dry etching process rather than a flat f process enables the widths of the spacers 2 and 24 to be less than the minimum line, for example, for a 〇 11 micron lithography. The application is the same as the two umbrellas, the width of the idle 18 is 〇·Π micron, the width of the channel 19 is 0.17 ^ micro] the width of the channel 24 is (four) micron, and the width of the channel is 2G for you~ After each channel 24 is formed, its reconstruction is necessary because the pass layer of the portion of the channel 24 is degraded or removed during the formation of the read indentation. In the embodiment, an emulsion (e.g., 40 angstroms) is used to heat a wafer, and oxygen is also in the process - part of the lion and covering the engraved number = 6 . In another embodiment, the wet side is programmed to remove such thin oxides from the surface of the material to eliminate damage to the substrate 12 during the process. Therefore, the gate gate oxide layer = (e.g., by re-growth) above the channel 24. Figure 4 is a front view of the structure shown in Figure 3, also (4) 3 series diagram, l292621 17067twf.doc / r, A 3_3 Lai Xian - recorded on the Qing Cheng's coffee. On the first-polycrystalline stone, 16 is engraved to form a pattern, and the channel ^ and the spacer are formed by the polycrystalline stone 18 and extend over the ridge of the figure. In the 婉蜒 pattern, the first polycrystalline stone adjacent to the locust extension pattern, the periphery of the layer 16 can be used to form a polycrystalline sluice gate of the peripheral transistor, for example, a selection

The electrification crystal is the other mine B used for the integrated circuit logic. As shown in Fig. 5, a second polycrystalline stone layer i6^ is deposited on the _ 曰曰 曰曰 夕 layer 16 after the engraving, and The ports 24 formed between the first spacers 20 are filled to create a second set of floating gates having a plurality of spaced polycrystalline nights 18 & As previously mentioned, in one embodiment, each channel 24 is desirably utilized, and the shadowing process is made equal to the minimum line width and used to form polycrystalline (tetra) 18, such that each additional polysilicon gate 18a that fills the corresponding channel 24 can Use lithography to make it equal to the minimum line width, but because the spacers 2〇 can be narrower than the minimum line width, each region will have more polyliths formed at the same time, making the memory size smaller and the memory device The density increases. As shown in FIG. 6, the second polysilicon layer 16a is selectively etched back to the first polysilicon layer 16, and the oxide layer 26 is also expected to be removed by this etching process, thereby producing a complete pattern. The polycrystalline germanium layer has a plurality of floating gates formed by the polysilicon gates 18 and 18a, and the oxide layer % can be used as a touch end point in the private order. In a uniform example, a gaseous state of the chemical Cb and HBr may be used to act on the polycrystalline spine of the cerium oxide (Si〇2); in addition, a chemical mechanical polishing (CMP) may be used. deal with. Figure 7 is a front elevational view showing a fully engraved polycrystalline layer of a first spacer 2 具有 having a separable polysilicon gate 1292621 17067 twf.doc/r 18 and 18a. Fig. 8 is a cross-sectional view showing the line 8-8 of Fig. 7 formed on the same straight line. As shown in FIG. 8, the first spacer 2 is removed by selective dry buttoning or the like to provide a channel 28 between the polycrystalline gates 18 and 18a, and the transport 28 extends to the gate gate oxide layer. 14. When the first spacer has the same oxide as the oxide layer of the embodiment of Fig. 5, the procedure is to remove the oxide layer 26 and the first spacer 2〇. / The gap 2 is made of nitridde (SiN), and a selective nitrogen wire is removed to remove the first spacer 2 between the polycrystalline gates 18 and 18a. The chemical may contain gaseous " and CF4. After removal of the first-spacer 20, the shallow ion implanted 3G is underneath the channel 12. The ion implantation system is based on a conventional industrial procedure, such as planting N+ ions on a p-type substrate 12, and this is a metal oxide half-field effect transistor that forms a domain. ; MOSFET) remembers the peculiar, shield and immersion areas. In addition, multiple pairs of ions are implanted 3. In a series of 4=: ^2^_ into a sleek, ton for a series of gold-oxygen ΐΓ 阳 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 32 = Recall Figure 14) Charging to open the 曰 substrate under the first spacer: two; two,, the field is on the substrate 12, the stripe field effect can be connected in series with the transistor. 1292621 17067twf.doc/r ^ Figure 9 is not 'channel Μ is then filled by oxidative deposition or nitrite sink to restore the first - -20 on the ion implant 3 ,, where the extended first gap The wall 20 is used to electrically isolate the polycrystalline stone from the evening. f ^ 16 to 32 serially connected ion implanted 3G and corresponding memory electric corona provide a string of crystals, and each pair of ions is implanted 3 〇 and its corresponding electricity is: one is located on the substrate 12 The dielectric trench isolation (STI) region 31 for isolating the respective transistors (continued one = see о 10, which is the profile i of the line formed in Figure 7❺10-10) The skilled person should understand that the fly-ditch isolation area 31 is a 2nd-polycrystal; before the layer 16 is formed, and although the Lang 7 only shows two core trenches, the shallow trenches of thousands of meters Isolation area 31. As shown in FIG. 11, the floating gate polycrystalline stone gate layer (including the first first polycrystalline stone layer 16 and the polycrystalline pins 18 and 18a) is returned to a target thickness to form a polycrystalline dream room. 18' and 18a, the polycrystalline dream layer soup. In one embodiment, the engraving program may be a time-dependent dry side material that uses gaseous CL and HBr to control the thickness of the remaining polysilicon gate, and the first spacer wall 20 protrudes above the floating gate polysilicon gate layer. Then, as shown in FIG. 12, a dielectric layer 32 (for example, a layer of N〇(〇xide/--ide/oxide)) is formed to provide coverage for each of the polycrystalline sluice gates and the 1st. Floating _ electrical isolation. The dielectric layer % is generally expected to allow the channel 35 to remain on each of the first spacers 20 and the floating gate after being deposited. In an embodiment, the 0N0 spacer can be deposited by low pressure chemical vapor deposition (1〇w pressure Chemicai vap〇r dep〇siti〇n; LpcvD) with an oxide layer on the bottom and the top of 1292621 17067twf.doc/r It can be formed by gaseous siH2Cl2 and 〇2, and the 2-shaped nitride layer can be formed by gaseous C12 and N2. The thickness of the oxide layer, the nitride layer and the bottom oxide layer are respectively And 4G angstroms' and this secretity is determined by the deposition process of the material-controlled side layer followed by deposition - the third polycrystalline rhyme 16c for dielectric

^32 is formed as shown in Fig. 13. The third polycrystalline layer 16c is filled with pass = 35 and is separated from the polysilicon gates 18' and 18a by the dielectric layer 32, which repeats the polycrystalline germanium deposition step described above. As shown in Fig. 14, the third polysilicon layer 16c of the dielectric layer 32 is then selectively etched to provide the sacred characters j 34 of the shape channel 35 (as shown in Fig. π). Here, a selective dry etching using a gaseous h-valence or a is employed, and a 〇N〇 layer is used as an etch end point layer.

A fringe field effect is introduced by the fringe field capacitance of the substrate 12 under the first spacer 2, and when the control gate is applied with a bias or one of the floating gates is continuously charged, the substrate The surface may create an inversion layer or channel, like an ion implant 30 to concatenate adjacent memory cells, and the fringe field effect can be used to provide source and drain ion implantation 30. Another option. Therefore, the step of removing the first spacer 20, implanting the ion implantation 3, and restoring the first spacer 20 can be eliminated by the stripe field effect. In addition, the word line 34 is located next to the first spacer 20 covering the word line = and the width of each of the first spacer 2 and QNQ layers is desirably narrower than the lithography process. Minimum line width produced, floating gate 12

1292621 17067twf.doc/r The spacing is the width of the first spacer 20, that is, about 3 angstroms, and the visibility of the gate is narrower than the width of the floating gate, which is approximately = times the thickness of the NQ layer. For example, if the floating gate width is 〇11 μm and the 〇N〇 layer visibility is about 0.G14 μm, then the control gate is approximately G U minus two 0.014, or 0 082 microns. . 15, this front view shows the mask area % to mark the traverse 38 ' thereby providing the character _ 立立's character line 34 ′ in this 巾 pattern towel and ^ reveals the representative by the word line Each of the formed inter-contact contact points 4G is formed by holes, and these electrical contact points 4() are arranged to establish a closed-loop control line for the package I1 and the removable body. In the figure, the line connecting with the corresponding word line 34. Figure I6 shows the channel 42 formed by the ruthenium layer 32 and the bottom polycrystalline layer (10). For example, the channel 42 is formed by the entire structure other than the mask channel 42 to make the channel 42 of the weft layer 32 into a selective side, and then to select the floating gate polygate. Sexual moments. - Fresh secret gold oxygen half-field power (four) Select electricity (four) source or bungee N + ion implant 44 is implanted in the channel 12 under the substrate 12, each word line 34 through the job of selecting electricity A gate control line for a removable read-only memory (not shown), as disclosed in the aforementioned U.S. Patent No. 5,050,125. , μ know that the skilled person should understand that a complete flash memory device can also include riding, (four), reading and writing, _ and other similar circuits that are similar to the conventional 'like the aforementioned US Patent No. 5 The circuit disclosed by Wind No. 125. 1292621 17067twf.doc/r Door tearing, line width (7) is 11.11 microns, and the line widths of polycrystalline stone gates 18 and 18a are respectively equal to less than 曰y. The width of the X direction is about G1H line. An example of the recognition of one, ★ on. ·. 3 micron (ie, the first gap ΙΓ ΙΓ i. If the memory size is about 2.5F in the Y direction, then OU^ has a significant increase due to the size of the memory cell, and the cost is also limited = hair: === The appended claims are defined by the scope of the patent application, and [simplified description of the drawings] ^ Figure 1 to Figure 16 of the formation of the memory array are the schematic diagram of the flash front view and the cross section of the present invention. Description] 3-3, 8-8: section, line 10: semiconductor combination 12: substrate 14: channel gate oxide layer 16: first polysilicon layer 16a · second polycrystalline layer 16b · polycrystalline layer 16c · brother ^ polycrystalline layer 18, 18a ' 18a' : polycrystalline gate 19, 24, 28, 35, 42 · · channel 1292621 17067twf.doc / r 20 : first spacer 21 : recessed channel 22 : spacing Material layer 26: oxide layer 30: ion implantation 31: shallow trench isolation region 32: dielectric layer 34: word line 36: mask region 38: traverse 40: electrical contact 44: source or 汲Extreme N+ ion implantation

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Claims (1)

And the control gates are at least partially deposited on the first floating gates 1292621 17067twf.doc/r. Patent application scope: 1. A flash memory device comprising a first group of floats The gate is a plurality of first floating gates formed on a gate oxide layer formed on a substrate, the first group of floating gates using a selective lithography process having a minimum line width A second set of floating gates includes a plurality of second floating gates, wherein the first floating gates are continuously deposited with the second floating gates, and each of the second floating gates Deposited between each of the first floating gates; a plurality of spacers, each of the spacers being deposited between each adjacent first floating gate and the second floating gate; And a plurality of control gates are coupled to the floating gates, wherein the spacers and/or the second floating gates have a width smaller than the minimum line width. 2. The flash memory device of claim 1, wherein at least some of the control gates have a width less than the minimum line width. 3. The flash memory device of claim 2, wherein the height of one of the spacers is greater than the first floating gate and the second floating gate of the second floating &"Hai Between the upper and the spacers. 4. The flash memory device of claim 3, further comprising: a dielectric layer deposited between the control gates and the floating gates. 5. The flash memory device of claim 1, further comprising: a doping source/drain region, the substrate 16 1292621 17067 twf.doc/r material implanted under the spacers . 6. The flash memory device of claim 1, wherein the first floating gates are spaced apart from each other by a distance less than three times the minimum line width. 7. The flash memory device of claim 1, wherein the width of the second floating gate is the minimum line width, and the width of the spacers is less than the minimum line width. 8. A method of forming a flash memory device, comprising: forming a first on a substrate by a selective lithography process having a minimum line width and depositing on a gate oxide layer a polysilicon layer to form a first group of floating gates including a plurality of first floating gates; depositing a spacer material between the first floating gates; etching a channel a spacer material to form a spacer to abut the first floating gates; and a second polysilicon layer on the substrate and the channel to form a plurality of second floating gates Two sets of floating gates with spacers. 9. The method of forming a flash memory device according to claim 8, wherein the width of the spacers and/or the second floating gates is less than the minimum line width. 10. The method of forming a flash memory device according to claim 9, further comprising: etching a height of one of the first floating gates and the second floating gates to be less than a height of the spacers 17 1292621 17067twf.doc/r • forming a dielectric layer over the spacers and above the floating gates with the respective channels between the spacers and the floating gates; a third polysilicon layer over the substrate to fill the channel between the spacers; and etching the third polysilicon layer to form individual polysilicon gates between the spacers With these floating gates. 11. The flash memory device forming method of claim 10, wherein at least some of the control gates have a width less than the minimum line width. The method of forming a flash memory device according to claim 8, wherein the first floating gates are spaced apart from each other by a distance less than three times the minimum line width. 13. The method of forming a flash memory device according to claim 12, wherein the width of the second floating gate is the minimum line width, and the width of the spacers is smaller than the minimum line width. 14. The flash memory device forming method of claim 8, wherein etching the spacer material comprises an isotropic dry etching process. The method of forming a flash memory device according to claim 8, further comprising: removing the spacers; forming a doping source/drain region adjacent to the first floating gates The substrates of the second floating gates; and the reconstruction of the spacers. 16. The method of forming a flash memory device according to claim 8, further comprising: 18 1292621 17067twf.doc/r re-establishing the gate oxide layer after the etching step to deposit the second polysilicon layer In these channels. 17. A method of forming a flash memory device, comprising: forming a channel gate oxide layer over a substrate; depositing a first layer of polysilicon; using a selective lithography process having a minimum line width The first layer of polycrystalline silicon is formed to form a first group of floating gates including a plurality of first floating gates, wherein the first floating gates are spaced apart from each other by less than three times a distance between the line widths; depositing a layer of spacer material between the substrate and the first floating gates; dry etching the layer of spacer material to form a spacer adjacent to the first floating gates and Adjacent to a corresponding channel between the spacers, wherein a width of the corresponding channel is equal to the minimum line width, and a width of the spacer is less than the minimum line width; depositing a second layer of polysilicon in the corresponding channel between the spacers, Forming a second set of floating gates including a plurality of second floating gates; etching the heights of the first floating gates and the heights of the second floating gates to be smaller than the spacers; depositing a dielectric Layer on the spacer and the same On opposing gates, and left and a control gate corresponding to the channel between the spacers; depositing a third polysilicon layer to fill the channel corresponding to the control gate; and etching back the third layer of polysilicon. 18. The method of forming a flash memory device according to claim 17, wherein the etch back of the third layer of polycrystalline germanium is formed in a pattern, 19