TWI292144B - Liquid crystal display device - Google Patents

Description

1292144 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a liquid crystal display, particularly for improving work efficiency and reducing manufacturing costs. [Prior Art] A normal-thin crystal display (LCD) is used to display a kneading surface by utilizing light transmittance. Call the factory liquid 曰曰 _ To achieve this purpose, such as "The first! As shown in the figure - the matrix 3 liquid helium award board 2 is included in the Japanese 不 不 , , , , 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶m ten / seven 11 poor material driver 4, 4 used · _ this liquid crystal _ board 2 (four) line DL1 to:: Cai 2 contains - thin film transistor m, which is provided in the idle '(10) TFT connection DU ^ heart Technique - she points, sighs the liquid crystal cell 7 connected to the TFT of the film transistor. Shi Tian received a known signal 'thin film transistor TFT start, that is, from the gate line (4) D 5 r a pure pressure VGHL - the halogen signal from the Bessie line D to the liquid daily cell 7. In addition, each 曰 田 / 辱 辱 辱 辱 辱 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰 脰The mouth and the signal are charged in the liquid crystal cell 7. The liquid crystal cell 7 can equally represent a φ6, a wide-grained A-lally, and a branch-to-yangbao. The liquid day and day cells 7 comprise a halogen electrode connected to the common fast pole and have a liquid day #^ > 笮, the liquid crystal cell 7 further comprises a - storage two! >square; among them (4) a transistor. The other > sub-H 5 acts as a charge 1292144 to maintain the sinus signal until the next sinus signal is charged. The storage capacitor is provided between the halogen electrode and the gate line of the previous state. The liquid crystal cell 7 which changes the alignment state of the liquid crystal has dielectric anisotropy, and the light transmittance is controlled in accordance with the pixel signal charging through the thin film transistor TFT, and thus is used as the gray scale level. The timing controller 8 generates the gate control signals (ie, GSP 'GSC and GOE) and the data control signals (ie, SSP, SSC, SOE, and P〇L using the simultaneously generated signals V and 提供 provided by the image card (not displayed). ). Gate control signals (ie, GSp, Gsc, and GOE) are provided to the gate driver 6 to control the gate driver 6, and at the same time, data control signals (ie, SSP, SSC, SOE, and P0L) are provided to the data driver 4 to control the data driver 4. . Further, the timing controller 8 arranges the red (R), green (G), and blue ten) pixel data VDs in a row and supplies them to the data driver 4. The gate driver 6 continuously drives the gate lines GL1 to GLn. To this end, the "gate driver 6" includes a plurality of gate integrated circuits 如 as shown in Fig. 2A. The idle integrated circuit ί continuously drives the gate lines GL1 to GLn to be connected to the control of the timing controller 8. The δ's gate integrated circuit 1Q continuously increases the gate high voltage VGH

The gate line GL1 is supplied to the Ln in response to the idle control signals (i.e., GSP, GSC, and GOE) issued by the timing controller 8. In addition, the gate driver 6 offsets the idle start pulse (10) to generate an offset time in response to the gate offset time GSC. Then, the gate driver 6 provides a high-altitude house to the GL at each level to respond to the listening pulse. In other words, the offset pulse is shifted line by line in every horizontal period, and the intervening body is 1292144.

Any one of the circuits 1 将此 provides this high electric dust VGH to the associated gate line GL in the associated offset pulse. In particular, the gate integrated circuit 1G provides -f electric ink VGL; in the remaining portion, when the gate high voltage VGH is not supplied to the gate line GL1 to 0, the I data buffer 4 supplies the pixel signal to the data line. Each of DU to DLm is recorded in every horizontal period. To achieve this, as shown in Fig. 2B, the data driver 4 includes a plurality of data integrated circuits 16. The data integration (4) provides the 昼素射u to the (4) line Du to. In response to the timing control, 8 issued by the control _ssp, ssc, S_ and P. In particular, (4) Integrated Electrical The gamma voltage generator (without display) converts the halogen data from the timing controller 8 to the analog halogen signal. When the outer shell feeder driver 4 shifts a source start pulse ssp to generate a sample, the return source source offset time is present. Then, the data integrated circuit 16 continuously locks the field VD in response to the specific unit of the sample signal. Then, the data integrator 4 16 converts the locked voxel data VD into an analog pixel signal in the same manner and “j increases, and the sub-line Du to DLm outputs one of the license signals at the source, in the middle. In addition, the vegetative integrated circuit 16 converts the morphological data VD to a positive or negative 钱素金朗应复数控观号 pQL. The spoon person achieves this purpose as shown in the figure * * "3", each data assembly In the circuit 16, the 匕3 is used to collect the subtractive-offset temporary poems, and is used to continuously feed the books, ——/, and VD in response to the sampling signals and synchronously output them. One of the latches 1292144

The portion 36, the wire converts the four-dimensional data VD peak lock portion 36 to one of the pixel voltage signals, the number of conversions (DAC) 38, the slave material _ surface shouts from the DAC 38 to the output one of the output buffers Part 46. In addition, the _ 77 yr 枓 枓 电路 电路 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 A slave 7 I is the controller 20 and the gamma voltage portion % of the positive and negative gamma voltages required to supply the DAC 38. The Tiger Control|§ 20 controls various control signals (ie, SSP, ssc, S0E, qing, p〇L, etc.) from the timing controller 8 and the sinus data to output them to the relevant components. The gamma voltage section 32 subdivides the plurality of input gamma reference cakes from the gamma reference ray generator (without display), and outputs them by each gray scale. And buffer...p 34 contains an offset register for continuous offset from the signal controller 2 - source start pulse chat (4) source sampling time signal SSC and output as - sampling Signal. The check lock unit 36 continuously performs the 昼 资料 资料 V 来自 来自 , , , , , 连续 连续 连续 连续 连续 连续 连续 连续 连续 连续 连续 连续 连续 连续 连续 连续 连续 连续 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 The lock part is composed of i check locks (where the soil is an integer): it locks * 1 pixel poor material VD, and each lock has the same phase as the alizarin data milk: 1 size. In particular, the timing controller 8 divides the pixel data VD into even-numbered densities VDeven and odd-numbered data to reduce the frequency of the transmission and simultaneously rotate it through the transmission-by-transmission line. Here, each of the even-numbered halogen data 1292144 VDeven and the odd-numbered data VDodd f contain the data of the rural (8), green (6), and blue (8). Therefore, the latching portion 36 simultaneously locks the even-numbered pixel data and the odd-numbered data VDodd, which are each of the sampling signals supplied from the signal controller 2. Further, the latch portion 36 simultaneously outputs a latched pixel data VD in response to the source output enable signal sQg from the signal controller 20.

In addition, the latching portion 36 restores the adjusted halogen data milk to reduce the number of transition period bits. The system responds to the data and selects the WuREV in reverse and outputs it. The timing controller 8 adjusts the prime vouchers VD to use the reference value to determine whether the bits should be converted or not to minimize the transition age. Minimizing electromagnetic interference (data) on data transmission is the minimum number of bits from the LOM HIGH or from the coffee to the L〇w transition period. The DAC 38 simultaneously converts the halogen data VD from the latch 36 to positive and negative

Voltage signal to lose it to {. To this end, the DAC % includes a - positive 40 and - negative (N) decoding portion 42 commonly connected to the latch portion %, and a multiplexer (10) term portion 44 for selecting the P decoding portion 4 and N decoding. Department & output signal. The P decoding unit 40 includes n P-demagnetizers for converting n simultaneously input main element data from the latching portion 36 to the positive drawing voltage signal by taking the positive gamma voltage from the (four) electric portion 32. The tampering unit 42 includes ι N decoders for converting the input of the data input lock unit 36 to the negative nucleus voltage signal by utilizing the negative gamma voltage from the gamma electric portion 32. The multiplexer unit 44 includes a multiplex port for selective transmission! > The 4 〇 昼 昼 讯 讯 n n n 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Two-pole control signal ship. 9 1 292 144 姨 刖 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器 缓冲器This output buffer buffers the I status number 'kDAC 38' to provide them to the data line DL1 to call. • The difference in the liquid crystal display is that the output channel of the data transistor 16 includes a data drive _ 4 according to the resolution of the liquid crystal display panel 2. This is because the data transistor 16 has a fixed channel which can be connected to the data line for the resolution of the liquid crystal display panel 2, which is different from the others. Therefore, for each resolution of the liquid crystal display 2, it is necessary to use a non-target data transistor 16 having a different output channel. This will reduce the efficiency of the work and increase the manufacturing costs. , . . In particular, for a liquid crystal display having an extended pattern array (XGA) resolution, 3072 data lines DL_ horizontally cut colors, red, green, and monitors are displayed, which requires four data transistors 16, Each has 768 data output channels. And for the display with the super-increasing shape (four) + (sxga +) display system, the gamma dragon line is called the horizontal recording of the beta color, two, two: Τ ' it requires six data transistors 16, each with 702 : In this example, the remaining 12 data output channels are false lines. For the liquid crystal day and day 3_ data line with the resolution of ^__(WXGA), the _ horizontal 昼素4 color, red, green to; its _ data transistor 16, each with 642 data In the example of rotation, the remaining 12 data output channels are false lines. k As mentioned above, a different data transistor 16 10 1292144 having a specific number of output channels is required for each resolution of the liquid crystal display panel 2 of the prior art. Therefore, the liquid crystal display of the prior art has low efficiency and high manufacturing cost. SUMMARY OF THE INVENTION The problem of the present invention is to provide a liquid crystal display device to solve one or more of the limitations and disadvantages of the related art. The invention provides a crystal display device, which works in a bribe and reduces manufacturing efficiency.

The advantage of this is that it provides a liquid crystal display device based on the analytical sound of the liquid crystal display panel and the ability to control the turn-out channel of the data integrated circuit. X $ 地地 W 'In accordance with the present invention - a liquid crystal display device = package ^ Lin integrated circuit, which has - data wheel out group to provide bedding to the data line and provide - false wheel out channel Group, out = group of round-out channels - channel selector, and installed in the data n / ... have - shell material output pad group connection data round out channel group age selection two butterfly painting Jing borrowed - selected complex =本:::!:之:种_示装置' contains - data line and tool; ^ - false 仏帛,, / 浦 鳞 啤 昼 昼 昼 至 至 至 至 至 作为 作为 作为 作为 作为 作为 作为 作为Two 峨 ^ on the data integrated circuit and installed clothes, with a brother and the second data input 11 1292144 知知娜 connected the first - and second data output channel group, wherein the above pixel information is borrowed It is provided to the data line by channel selection ϋ selecting the wheeling channel. The summary of ^ is explained in detail below for the purposes of demonstration and transfer and further disclosure to the scope of patent application. [Embodiment] The features and implementations of the present invention will be described in detail with reference to the drawings as a preferred embodiment. Figure 4 is a diagram showing a first embodiment of a liquid crystal display according to the present invention. Thus, the fourth embodiment of the present invention can be better than the other embodiments. According to the "figure 4", the liquid crystal display comprises a liquid crystal display panel 102, ... a liquid crystal cell arranged in a matrix shape, and a gate driver 106 for driving the liquid helium-page board 102, the line GL1 To the GLn, and the data driver 1〇4 to drive the data lines DL1 to DLm of the liquid crystal display panel 1() 2, and a timing controller to control the gate driver 106 and the data driver 1〇4. Wherein, the liquid crystal display panel 102 comprises a thin film transistor TFT acting between the gate line <3][^ to GLn and each intersection of the data lines, and a liquid crystal cell (without display) connecting the thin film transistor TFT . When a scan signal is supplied, the thin film transistor TFT is turned on, that is, the gate high voltage VGH from the gate line GL supplies the pixel data from the data line DL to the liquid crystal cell. When the gate low voltage VGL is supplied from the gate line GL, the thin film transistor TFT is turned off. The halogen signal remains charged in the liquid crystal cell. 12 1292144 Liquid crystal cell can be expressed as - liquid crystal capacitor. The liquid crystal cell includes a halogen electrode which is concentric with the common electrode and a thin film transistor including the liquid crystal therein. The liquid crystal cells are further provided with a 3'-storage capacitor as a means for maintaining the charging of the pixel signal until the next pixel is de-charged. The storage capacitor is provided between the halogen and the front-state gate line. The liquid cell 7 is changed by the halogen signal charging, and the light transmittance is controlled by the alignment state of the liquid crystal having the μ-package of the liquid crystal through the thin film transistor, thereby improving the degree of gray scale. The timing controller 108 generates a gate control signal (ie, Gsp, GSC, and gamma and data control views _ SSP, ssc, ship, and roL are synchronized signals V and H provided by the image card (not shown). That is, Gsp, GSC, and G〇E) are provided to the gate driver 1〇6 to control the idle driver 1〇6, and at the same time, the data control tigers (ie, SSP, SSC, SOE, and POL) are provided to the data driver 1〇4. The data driver 104 is controlled. Further, the timing controller 1〇8 arranges the pixel data 9 and uses it as the data driver 1〇4. The gate driver 106 continuously drives the side lines GL1 to ❿. For this purpose, the gate The driver 106 includes a plurality of gate integrated circuits (the gate lines GL1 to GLn are not explicitly driven to control the timing control, and the closed circuit circuit continuously provides a gate height _ VG_ between the lines Gu to ❿ in response to The closed control signals of the timing controllers 1〇8 (ie, Gsp, GSC, and (8) are cut. In addition, the gate drive II 106 shifts a start pulse Gsp (four) to the offset time LrSC to generate an offset pulse. Then, the driver 1 〇6 provides a free high power 屙 13 1292144 H = at each level of the weekly shot A this bias The pulse system-line-to-line offset is provided at each and every offset pulse, and the gate circuit provides the gate=species and according to ΓτΤ. The day gate is VGH to the relevant gate line-, the gate integrated circuit provides - the gate is low The voltage is generous to the rest of the idle line. The poor material driver 1〇4 provides the book Xin·= line DU to DLm at one of the time points in each-horizontal period—the purpose of the input, the coffee machine (four) several data integration Circuit. Each data integrated circuit ΐ6 is installed in a capital

Tape package (TCP) 11 (). The data integrated circuit ιΐ6 is connected to the data lines DL1 to DLm through the data 、, the dry file 114 and the link 118. The data integrated circuit η ό provides a 昼 讯 signal to the data line Du to the heart in response to the data control signals (ie ssp, SSC, New, and POL) from the timing controller (10). Further, the data integrated circuit 116 converts the pixel signal from the timing controller 1〇8 to analogy using a gamma voltage generated from a gamma voltage to generate a cry (no display).

Further, it is known that the turtle path 116 is offset from a source start pulse to generate a sample signal in response to the source start pulse SSP. The data integrated circuit 116 then continuously locks the halogen signal VD in response to a particular unit of the sampled signal. Then, the data integration circuit 116 converts the locked pixel signal from one line to the analog elementary signal, and supplies it to the data line DL1 to DLm within the permission interval of the source output permission signal s〇E. In addition, the data integration circuit 116 converts the halogen data to a positive or negative binary signal in response to the plurality of control signals POL. 14 1292144 Meanwhile, in the first embodiment of the liquid crystal display of the present invention, each of the 枓 体 电路 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U Qing 2 in AU for this purpose, for example, every "data integrated circuit ι ΐ 6 contains the first - second. The feet 0ρι and op2 are provided by the first and second channel selectors 四(4) jin; Γ矣 each of the first and second channel selection signals P1 and P2 are selectively connected to the voltage source VCC and the ground voltage source _ to have a 2-bit domain Binary logic value. Therefore, the first and second channel selector signals P1 and P2 provide logic (10), 10 10, and η to the data integrated circuit 116 through the first and second selection pins P1 and 〇P2. Therefore, each area body circuit 116 pre-sets the number of channels according to the resolution of the liquid crystal display panel, wherein the first and the second channel selects ρι and hits through the brothers 44-selection pins OP1 and 〇p2 Provided. According to the resolution of the liquid crystal display panel 1 〇 2, the number of data integrated circuits 116 corresponding to the integrated circuit 116 is described in the following table: Table 1 The number of resolution pixels according to the output of the data integrated circuit Channel data integrated circuit quantity data line--__ brake line 600CH 618CH 630CH 642CH 3072 768 5.12 4.97 '4.88 4.79 4200 1050 7.00 6.80 6.67 6.54 15 1292144 \JXGA~ WXGA~ wsxgaT' 4800 ~~~~---- 3840 ^—-- 4320 —1-—1200 8.00 7.77 7.62 800 6.40 6.21 6.1〇900 7.20 6.99 6.86 WSXGA 5040 1050 8.40 8.16 —------ 8.00 WUXGA 5760 1200 9.60 9.32 9J4 7.85 8.97 Clothes not. In addition, the exit channel. Therefore, according to the first liquid crystal display of the present invention, the liquid crystal display panel 1〇2 having the resolution of XGA requires five data integrated circuits 116, and each data integrated circuit 116 has 618 data round-out channels. In addition, the remaining 18 data rotation channels are regarded as false lines. A liquid crystal display with SXGA+ resolution requires seven data integrated circuits 116, and each data integrated circuit m has 600 tributary rounds. The liquid crystal display panel 102 having the resolution of the super-enhanced graphics adapter (10) requires eight data integrated circuits 116, and each data integrated circuit (10) has 600 data output channels. The liquid crystal display with the resolution of the brain eight requires six data integrated circuits 116, and each data integrated circuit has (10) data output channels. The liquid crystal display panel 102 having the resolution of the wide screen super-enhanced graphics adapter _(wsxga_) requires seven data integrated circuits ι ΐ 6, and each data integrated circuit m has 630 data round-out channels. A liquid crystal display panel 1 〇 2 having a wide screen super reinforced graphics adapter (WSXGA) requires eight data integrated circuits 116, and each data integrated circuit (10) has 63 data output channels. The liquid crystal display panel with the resolution of the wide 綦 綦 适配器 适配器 adapter (w〇xGA) requires 9 pieces of material to know the rainbow circuit m' and the mother-data integrated circuit (10) has (4) data input. The embodiment configuration data integrated circuit 16 1292144 116 642 sets the number of thieves to _ channels, 618 channels, (four) channels, and ^ channels to respond to the first and second channel selections, thereby causing the crying ^ - the accuracy of the liquid crystal binary method according to the present invention, the data integrated circuit 116 is manufactured to have (4) resource output channels and the number of active wheel-out channels configuring the dragon integrated circuit 116 in response to the first The first selection stylus 2 with the second channel selection pin 与ι and (10) is suitably used for the solution of the liquid transmission plate (10). Further, according to the first embodiment of the liquid crystal display of the present invention, the data integration body Circuit 116 is fabricated with 642 data output channels. As shown in Fig. 5, when each of the first and second channel selection pins 〇ρι and (10) are connected to the ground voltage source _, the first and second channel selection signals π and p2 are supplied to the data product. When the value of the body circuit 116 is (8), the data integrated circuit 116 outputs a pixel voltage signal from the first to the first data channels of the 642 available channels. In addition, the 642th output channel of the first process becomes a false wheel exit channel. As shown in Fig. 6, when the first selection pin 〇ρ is connected to the ground voltage source GND and the second selection pin op: connected to the core vcc, the first and second pass selection signals pi When the value of the slanting integrated circuit 110 provided by P2 is 〇1, the data two-body circuit H6 transmits the pixel voltage signal from the ith to the 618th data of the 642 available channels. In addition, the _th to sixth-like output channels become dummy output channels. As shown in Fig. 7, when the first selection pin (10) is connected to the voltage source να 17 1292144 and the second selection pin 0P2 is connected to the ground voltage source GND, the -, ,,, and the selection signals P1 and 1> 2 is provided to the data integrated circuit n (four) value is 1 day, the data integrated circuit 116 passes through the irth of the 642 available channels to the second material of the second output pixel voltage signal. In addition, the 631th to 642th output channels become false output. Finally, as shown in Figure 8, 'When each of the -first and second channel selection pins (10) and (4) are connected to the voltage source, VCC * provides the first and second channel selection signals P1 and P2 to the data product. When the value of the body circuit 116 is u, the data product body is rotated through the channel from the ith to the 642th wheel of the 642 available channels. In the embodiment of the liquid crystal display according to the present invention, the data plane circuit 116 includes a channel selector 13 〇, and the data stacking channel 116 ^ output channel is configured. The response is provided in the first and second channel selection pins (10) and the 0P2 music-and the second channel selection signals ρι and p2, for example, providing a continuous _ number-offset temporary 134, scaled age 7 Newsletter will turn π to red - shop 136, women's sputum lock part W is converted into a digital analog signal converter (DAQ138, 乂 and receive 4 money pressure signal from say (3) to output - output The buffer 146. The other 'data integrated body_ further includes a signal controller 120 inserted from the timing controller 108 and the control signal, and provides a positive or negative gamma, ', packet 1, and port DAC 138. One of the requirements is a gamma voltage generator 132. 18 1292144 The signal generation benefit 120 controls various signals (ie, SSP, SSC, SOE, qing, and p〇L) from the timing controller 1〇8 and the 昼素 data^ to The wheel is out of the relevant component. In addition, for each grayscale degree, the gamma voltage section 132 The sub-divided into a plurality of gamma reference voltages are input by the gamma reference voltage generator (no display). The pass-through state 130 provides the fourth through the first and second selection pins 〇ρι and 〇1> The forced control signals CS1 to CS4 are sent to the offset register to respond to the first and second channel selection signals P1 and P2. In other words, the channel selector, (10) generates # and has the value GG -_ two channel selection 峨ρι Phase 1 selection signal CS1 with p2 phase, second channel selection signal CS2 with first and second channel selection signals having a value of 〇1, and first and second channel selection with a value of 1〇 The third channel selection signal CS3 associated with pi and P2 is called, and the fourth channel selection signal (10) associated with the first "first transmission selection tigers P1 and Ρ2" having the value η. 偏移s the offset of the temporary private temporary storage unit 434 The register continuously shifts the source from the signal port 120, the start pulse ssp in response to a source sampling time signal and the output sample signal. In this example, the offset register portion 134 is composed of 642 registers. · SR1 to SR642. Such an offset register unit 134 provides the _th, the 61st 8. The first and fourth channel control signals Csi to cS4 from the channel selector 〇3〇 are in response to the first to fourth channel control signals 116 from the channel selector 〇3〇. In other words, when the channel selector 130 provides the first output control signal (3), the offset register portion m continuously shifts a source start from the signal controller 12A to enable the SR1 i SR_ to respond to the source sample. The time signal ssc is output as a sampling signal. In addition, the output of the temporary register ^ is supplied to the first temporary storage SR1 of the lower-state data integrated circuit 116 for the tiger (ie, a carrier signal) (connected with each other) a series of connections). Therefore, the first to the 642th offset register is difficult! The fun signal 2 does not output the sampling signal. Here, if the offset temporary storage is driven symmetrically, it is formed by the * channel, and the false mode can be more beneficial in use. When the channel selector 13 provides the second output control signal (3), the offset temporary storage 134 is continuously offset from the source controller of the signal controller 12 by using the first to the (10) offset. The memory is sent to the lion 8 in response to the source sampling time and the SSC is output as a sampling signal. In addition, the wheel-out signal (ie, the carrier signal) of the 618th register SR618 is supplied to the first-storage register SR of the lower-state data integrated circuit ΐ6. Therefore, the 619th to 642th offset registers are The sampling signals are not output from sR6i9 to SH642. When the island pass selector 130 provides the third output control signal CS3, the offset register unit 134 continuously shifts a source start pulse from the signal controller 12 to the offset to the 63rd offset. The devices SR1 to 63〇 signal the SSC in _ time and output it as a sampling signal. In addition, a round of signal (ie, carrier signal) of the 63rd buffer is provided to the lower-state data integrated circuit (10) 20 1292144. Therefore, the 631th to 642th offset registers are deleted until the sampling signal is rotated. Here, if the offset register is driven symmetrically by left and right, it is formed by not making the interbank channel - the false mode can become more profitable in use. When Tiantong privately selects $13Q to provide the fourth round of control signal (3), the offset temporary storage unit m continuously shifts a source start pulse from the signal controller (10) to use the first-骂642 offset temporary storage (4).丨 s 触 应 应 应 应 取样 取样 取样 取样 取样 旒 旒 旒 旒 旒 旒 旒 旒 旒 旒In addition, the output apostrophe of the 642th register s suspends (ie, the carrier § butterfly is supplied to the first register SR1 of the data-integrated circuit H6 of the lower state). The king lock unit 136 is seamlessly derived from the signal controller. 12 〇 昼 资料 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V To this end, the latch 136 is comprised of up to 642 latches to lock 642 pixel data VDs, and each latch has a size associated with the number of bits of the fancy data VD. In addition, the a-cast controller (10) divides the halogen data W into even-numbered pixels, VDeven and odd-numbered four (4), in order to reduce the transmission frequency and output through the per-transmission line. Here, each of the even-numbered elements VDe stomach and odd-numbered halogen data contains red (R), green (G), and blue (B) pixels. Therefore, the latching portion 136 synchronously locks the even-numbered pixel data VDeven and the odd-numbered gas-depleted material VDodd through the signal controller 12 to supply each sampled signal. Furthermore, the 21 1292144 latching portion 136 synchronously outputs the pixel data VD through a selected number of output channels (600, 618, 630, and 642 data output channels) in response to a source output grant signal SOE from the signal controller 12A. In addition, the latching portion 136 restores the modulated data VD such that the number of transitional bits is reduced in response to the data reverse selection signal REV. The timing controller 8 modulates the pixel data to utilize a reference value that determines whether the bit is inverted or not, and minimizes the number of transition bits. This minimizes electromagnetic interference (EMI) on data transmission, resulting from the minimum number of bits in the transition period from LOW to HIGH or from ffiGH to L〇w. The # DAC 138 outputs the halogen data vd from the latch portion 134 to a positive or negative pixel voltage number. To this end, the DAC 138 includes a positive (p) decoding unit 14A, a negative (N) decoding unit 142 commonly connected to the latch 136, and a positive (P) decoding unit 140 and a negative (9). The output signal-multiplexer of the decoding unit 142 (MIDQ 144. The P decoding unit 140 includes n P decoders, which use the second from the gamma voltage unit 132 to compress and convert the n input pixel data from the latch unit.至正昼=私 [Λ就.ΝDecoding unit 14〇 contains i Ν decoders using positive gamma power from gamma voltages?] Inputs of input data from the lock-up unit (10) synchronously In this example, the multi-jade part m contains at most 642 multiplexes 142 in the selective 攸P decoder 140 to rotate the positive pixel signal or from the N decoder (1) (four) to the prime minister of the self-signal control (10) A plurality of control symbols POL. 22 1292144 The buffer portion 146 includes at most 642 buffers which are connected in series by a voltage follower to respective data lines of the 642 data lines DL1 to DL642. The buffered pixel voltage signal is supplied from the DAC 138 to the data lines DL1 to DL642. The liquid crystal display according to the present invention In the first embodiment, as described in Table i above, the data integrated circuit 具有16 having 600 data output channels is used for the liquid crystal display panel 102 having SXGA+ resolution or UXGA resolution; and the data integration of 618 data output channels The circuit 116 is used for the liquid crystal display panel 102 with XGA resolution resolution; the data integrated circuit 116 having 630 data output channels is used for the liquid crystal display panel 1〇2 with WSXGA resolution; and the data of 642 data output channels The integrated circuit 116 is used for a liquid crystal display panel 1 〇 2 having wxga resolution or resolution or WXGA resolution or gastric GA resolution. As shown in FIG. 10, the first embodiment of the liquid crystal display according to the present invention The data integrated circuit 116 is mounted on the data TCp 11〇. - The bedding TCP 110 provides a wheeled pad connection data printed circuit board (no display) and the shell output pad group 16 () and the fake dragon The output pad is collapsed and connected to the liquid crystal display panel 102. In addition, the sum of the number of pads provided by the data wheel out-welding pad group (10) and the number of pads of the dummy data wheel out-welding group 164 are combined with the data integrated body. The number of output channels of circuit 116夂The data output pad group (10) is connected to the data output channel group of the shell material circuit 116 through the signal line provided on the hybrid Tcp 11G. The data output pad group 16〇23 1292144=the number of pads and the number of pads The second channel selection signals ρι and ?2 have the same number of data rounding channels selected by the data integrated body 6. For example, if the data of the second round is out of the channel, the second and second channel select signals n and p2 = poor materials. Selecting _ data output channels in the round-out channel, as described below, the data wheel-out pad group 160 of the TCP 110 also has 600 output pads. "' The false data output pad group 164 becomes the output channel _ of the remaining data except the first and second channel selection signals Π and P2 selected by the data integrated circuit 116. For example, if the data output channel of the integrated circuit ι6 is selected by the first: and the second channel selection signal P1 and the 642 data output channel, as described below, the data output of the data is 11 The pad group 164 has 42 output pads. As shown in Fig. 11, such a material TCP 11 is adhered to the data pad portion 186, which is provided on the lower substrate of the liquid crystal display panel 1〇2. As shown in FIG. 12, the data pad portion 186 provides a data wheel pad group 180 at the glue output pad of the data 1CP 110 and provides a dummy data input pad group 184 to the data TCP 110. The false data output pads 184 are glued. The number of pins in the data input pad group 180 becomes the same as the data output of the data TCp no: the number of pins of the fcf pad 160 is the same. Each pin of the data input pad group mq is connected to the data line dl through a link 118. According to the first embodiment of the liquid crystal display of the present invention, the data output pad 160 of the data TCp 11 and the data input pad group 18 of the liquid crystal display panel 1 are designed in the same manner as the 24 j292l44, as mentioned above. According to the material 嘱 f product output channel in response to the first and second output channel signal ρι 16 as described above, the root gamma liquid crystal display (four) of the first;; the user said, according to the resolution of the liquid crystal display panel 102, With == table! The output still screams for $--accounting axis ^^, and the second channel selects signals P1 and ρ2, so "the younger brother has a shape-like base circuit such as. Therefore, according to this issue g=ir use only good work __ The present invention is the first embodiment of the liquid crystal display according to the second embodiment of the liquid crystal display according to the present invention, and the liquid crystal display according to the present invention. The σσ罘 is a poor example of the circuit outside the fairy. Therefore, the cup Ming (four) f the same component 'except the data complex

The first-disc A-product circuit 416 of the liquid crystal display of the present month is described by combining the "interpretation σ"-t diagram of the other components in the first example, and the integrated circuit is referred to. The information shown in the picture of Yu Di 4 is replaced. The number 116 will be in the "figure 13" to - reference number Wei take the liquid crystal display according to the present invention contains the first - data round 6 i in the Beca integrated circuit =: provide funding _ heart to the scale _ and the first False output between channel groups 262 = 4 outputs 1292144 This data integrated circuit 416 includes first and second selection pins 0P1 and OP2, which are selected by the first and second channel selection signals ρι and P2, Whether the prime data is supplied to the data lines Du to DLm via the pseudo pure round-out channel group 264 is output from the associated data lines DL1 to DLm. Each of the first and second selection pins 〇ρ and 〇p2 selectively connects a lightning source vcc and a ground voltage source GND to generate a 2-bit binary logic value. So what is the - 第 - and the second channel selection signal ρι? 2 to the first and second selection pins 0P1 and 〇P2 to allow the data integrated circuit 416 to have values of 〇〇, (U, 1 〇, and u. ^ Therefore, the mother-poor integrated circuit 416 is based on the liquid crystal display panel The resolution pre-π of 102 sets the output channel in response to the first and second channel selection signals Ρ1 and Ρ2 provided via the first and second selection pin and 〇p2. The pre-determination is based on the resolution of the liquid crystal display panel The number of data integrated circuits 416 of the data integrated circuit is the same as that of the above table i. According to the second embodiment of the liquid crystal display of the present invention, wherein w~ is not a π 丹丹τ贝炉(四)路416 The channel is set to (four) channels, (10) channels, (10) like = 42 channels - one in response to the first - and the second channel selection message (four) Ming ^ and the secret proof of moving the financial solution. In other words, According to the second embodiment of the April crystal display, the (10) integrated circuit 416 is configured to produce a ❹ / ^ 枓 output channel, and the output channel of the data integrated circuit is called, and the first channel and the channel selection signal _ Ρ 2, _ Display liquid crystal panel 1〇2 26 1292144 kg has resolution. Further, liquid crystal according to the present invention The display is based on the data output circuit of the data integrated circuit: in the embodiment, the wheel is turned on to arrange the data integrated circuit, and the data foot has the same output channel. Included in the fake data soldiers over the invention of the liquid day and day _ the second real off this 'according to the Chu a # 贝针矛矛 circuit 416 in the mother-di brother and the second tilt output channel group Electromagnetic interference on the data of the halogen, I forced, so lower, in addition, the second real circuit 416 of the liquid crystal display according to the present invention is manufactured to have (4) data output channels.] /, the body selection 1 and the fertilizer Grounding voltage source coffee, so that the 4th pass of the election signal P1 and La Didi is called the data integrated circuit 416 round check = ^ ^ road 416 value of 1 times out of the tribute. For example, "14th" The data of the Norwegian-Bei product is converted to the data of the four-dimensional map. The 343th channel group 264 is considered to be false: the second game is freshly collapsed. In addition, the false data output is when wtt 帛 342_ The second W LATi side voltage voltage source VCC, and the first -, and the younger brother select the pin 0P2 to connect the 'footsteps Xingdi two e-body circuit 416 value is m, S ^ "UbPi and P2 provide In the data product r.7_%, the poor material integrated circuit 416 rounds out the Xin Xinyin, qa music 15 picture』, the data, the ... section. Such as 416 rounds of paintings, the source is via 642 27 1292144 In the data output channel, the first to the second - group edited w channel:: a group of 264 contains the first to be regarded as a false line - to the 333: when the first pick 1 pick up the source VCC buy two options, (4) The first and second channels select signals. 1:: The value of the body circuit 416 is 1r^士士士士1, in the case of the 枓 枓 第 第 第 第 , , , , , , , 资料 资料 资料 资料 资料 资料 资料 资料 416 416 416 416 416 For example, the 5th==Drawing material in the data output channel is via the tonne group and (4) to the second channel of the 642th canister==:, and the false data output channel object is included in the channel. Wang Le loses the first = Γ and the second choice pin. P1 * 0P2 is connected to the voltage source VCC, = two. The selection signals P1 and P2 are provided in the thin circuit of the thin circuit, and the maturity integrated circuit is rotated. For example, the data output of the "Fourth (4)" poor material integrated circuit, the first - data output pass 96 "0 and the second data input _ Dao group 262, capital, - fine second age mountain 1...迢 264, via the first to the 642th round of the 642. At the same time, according to the liquid crystal display of the present invention, the first data storage system is mounted on the data card K). The material CP 510 provides a wheel-in solder pad 28 1292144 for connecting the data printed circuit board (without display). The second data wheel is connected to the first data transfer pad group 56G and the second data wheel connected to the liquid crystal display panel. In addition, the data set in the training, the data in the training circuit 416, the fake data wheel out of the welding pad group is regarded as a fake. In other words, the dummy data output pad group 564 in the volume circuit 416 is not coupled to the first and second data wheel pads 560 and 562. The Le-Bei material output pad group 56〇 is provided via the signal line to the data source circuit 416, the first data material, the number of solder pads _ the number of pads and the second, by: . &quot; material input! Search a 罘 弗 弗 通 通 通 通 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择^416第—The number of channels of the data output channel group 260 is the same as that of the temple, if the data is selected by the first fish second data integrated circuit 4]6, 、P1 and P2, _ The channel of the f-wheeling channel group 260 is (4) the out-of-weld material. _=== As described above, the first-face network is once 啕罘1 to ang 300 output pads. The connection pad group 562 is supplied to the data TCP 510 via the _ line to the first block of the integrated circuit 416. The number of the output 塾 group is determined by the number: and (4): as Gu group 262. The first data is selected as the second resource of the data integrated circuit 416;; the rhyme selection signal P1舆P2 and the like. For example, if the second selection signal P1 and the data selected by the number of channels of the 262 channel are selected, the data is rotated by two channels: the channel of 262 is (4) , the wheel _ group 562 of the pad also and if the m is MM 510 on the 7, also have music 300 to 600 output welding 29 1292144 pad. As shown in Fig. 19, such data training is adhered to the data soldering portion 586 to be provided on the lower substrate of the liquid crystal display panel 1〇2. If the data is not as shown in the figure, the data pad portion 586 and the data input pad group mo are raised, and the first data wheel out of the pad group 56 〇 and the second data output pad group 562 Adhesive. The number of pads of the data input pad group 580 is the same as the first data output pad group 56 of the data TCP 510 and the second data wheel pad group Μ2. Each of the data wheel weld pads f 8〇 is connected to the data line via the connection training. According to a second embodiment of the liquid crystal display of the present invention, the data input pad group and the second data wheel output pad group 562 of the data sheet are formed in the same manner as in the above manner. The proposed y changes the data integrated circuit 416 round channel (4) and P2. - phase _ first - and second output Φ as described above 'root county (four) liquid crystal display (four): in fact, according to the liquid crystal display panel his resolution configuration data integrated circuit 4161 response provided in the first and second choice Talk to ορι one; two output channel signal P1 visit. Therefore, all ang _ ΛΛ 而 而 声 声 Φ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 。 。 。 Therefore, the liquid crystal display according to the present invention has the ability to improve operational efficiency and reduce manufacturing cost. Λ &amp;f,]; As shown in the "Phase 21" phase (four) crystal (four) of the second embodiment 30 1292144, the data integrated circuit 416 is installed on the data Tcp 61〇. Once the information · G provides the round of people to refer to the information she (no display), with the ^ loss of the spider pad group 66 〇 with the second data round out welding 塾 and 2 connected liquid plate to move, and paste 峨 664 to provide between the first,: Between the pad groups 660 and 662. In addition, the number of data wheel φ pads on the Beike TCP 610 becomes the same as the number of data output channels of the data integrated circuit 416. , the first - data output pad group _ via the signal line to the data Tcp (10) to = to the fine 416 of the first - capital view secrets. The number of pads of the first data wheel 660 is the same as that of the body circuit 416 selected by the first 盥 盥 10 、 、 、 、 、 、 、 、 、 、 、 、 、 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。. For example, if the channel number of the 260th channel is selected, the brother-transportation selection signals P1 and P2 are selected = the channel of the data output channel group 260 of the integrated circuit 416 is 642 cells = 600 output trees. The reliance channel, as mentioned above, is the data tongs. The solder pads also have _ output pads (ie, the i-th to the 300-output pads). The second data output welding group 662 of the fish pull is provided to the data TCP 610 via the signal line, the number of knowledge points of |JI, 660, and the selection signals P1 and p2 by the first and second channels~&quot;&quot The channel number of the second data output channel group 262 of the % road 416 is searched for - the case is 5 brothers' if the second data output channel group of the selected body circuit 416 is selected by the first and second channels The channel is (4) 31 1292144 2 rounds of data rounding channels, as described above, the data is taken from (10) _ to the _think. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,塾 之 你 资料 资料 资料 资料 资料 资料 资料 资料 资料 资料 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二In the channel ^cT output channel, it is called 峨 峨, as mentioned above, then = 421 Γ 垫 垫 也 也 也 也 也 也 。 。 。 。 。 342 342 342 342 342 342 342 342 342 342 342 = "22nd" and "23""_, (10)_ are attached to the data pad portion 686 on the lower substrate of the LCD panel 1G2. = welding, material Tcp (10) of the first - data output welding earth _ 帛 - shell material wheel into the Tan pad group 680, and adhered to the Zifeng Douding π (10) of the = data output pad group 662 - the second data input welding The pads and h and the dummy roller out pad group _ adhered to the reading TCP (10) are formed by a dummy data input pad group 684 provided between the first and second data input pad groups 68 〇盥 /. ' Yu Bei Yu Xingyue】 into the number of pads 680 of the knowledge pad group 680 becomes the same as the data TCP 610 32 Ϊ 292144 a feed output pad group _ supplement. Each of the first-data input pad groups 680 is connected to the data line DL via a connection 618. The number of pads of the first data wheel pad group 682 becomes the same as the second data output pad group 662 of the data TCP 610. Each of the second data input pad groups 682 is connected to the data line DL via a connection 618. The number of pads of the dummy data input pad group 684 becomes the dummy material output pad group 664 _ with the data TCp 61〇. Each of the pads in the dummy data input pad group is considered to be fake. In other words, the dummy data input pad group 684 is provided between the first and second poor input pad groups 680 and 682 and is not connected to the data line DL. According to a second embodiment of the liquid crystal display of the present invention, the first and second data output pad groups in the data TCp (10) and the first of the liquid crystal display plates 1 and 2 Designed in the same manner as the second data input welding group _ and 682 and the false data input welding group, as mentioned above, it is the first and second data output channels in the phase changing circuit 416. Groups 26〇 and 262 and dummy data are rotated out of channel group Μ4 in response to first and second channel information signals P1 and P2.第 In accordance with the first and second embodiments of the liquid crystal display of the present invention, it is not limited to those which have 642 data wheeling channels in response to the first and second output pinch signals P1(4). _ channel, can also be suitable for (four) Jing fun face gamma 642 output channel of the integrated circuit circuits 116 and 416. 1292144 In addition, the data integrated circuit 116盥•咏b 416's round-out channel is set to respond to the first and second round-out channel signals Pi disk p7 basin, and its sub-Asian and non-limiting to 600, 618, 630 and 642 Data output channels can also be applied to any instance. In other words, the output channels of the data integration channels 116 and 416 are set in response to the first and second output channel signals γ and P2, according to the resolution of the display panel, the number of f-materials Tcp, the data μ ^ degrees 乂 and '丨4 sequence control benefits 1〇8 and the data integration circuit are used to determine the number of data transmission circuits (10) and the number of data transmission lines of the data. Therefore, the number of output channels of the data integrated circuits 116 and 416 set in response to the first and second traffic selection signals P1 and P2 may be 600, 618, 624, 630, 642 '645, 684, 696, 702 or 720, etc. / In addition, S is also limited to the 2-bit binary binary logic value, and may also be the second-order binary number, or the channel of the output channel of the 416. Carry logic value. As described above, according to the liquid crystal display of the present invention, the channel selection signal is used to change the data integrated circuit channel according to the resolution of the liquid crystal display panel. Thus, the resolution of all the liquid crystal display panels is driven by using a heavy-weight private pen path. . In addition, the liquid crystal display according to the present invention comprises a data integrated circuit having a dummy data output channel group provided between the second data channel groups of the first disk, and the island continuously supplies data to the data line, and according to the liquid crystal display panel. The resolution is used to change the volume circuit path by using the selection signal, thereby causing the two data integrations to pull the resolution of all the liquid crystal display panels. 1292144 The display panel, which may use the liquid crystal _ 士士^ thus reduce the number of integrated circuit circuits. As a result, ''each liquid crystal display' can improve operational efficiency and reduce manufacturing costs. = However, the preferred embodiment of the present invention is disclosed above, but it is not intended to limit the use of any two skilled artists. In the case of the invention, the scope of patent protection of the invention is as defined in the context of the company. [Simplified illustration] 21 is a liquid crystal display of the prior art. "Electricity block"; Brother 2 Α diagram" is the idle body of the gate driver containing the conventional technology "『^图" is included in the data drive of the _ surgery: _ body circuit. Department:: a" ~ product side phase 4] The circuit of the first embodiment of the liquid crystal display according to the present invention will be the second, the second, the selection signal (four) road money has _ a simple round-out channel; the sixth picture is based on "fourth" In the first picture, the first invitation is to set up the integrated circuit to have (4) #料^—=Selection Signal No. 7”, which is based on the “No. 4” The wheel selection signal 35 1292144 "Fig. 8" is the first and second according to "Fig. 4" Selecting the signal to set the data output integrated circuit to have 642 data out-of-round channels. · "9th picture" is the 枓 枓 枓 电路 于 『 『 『 『 『 『 『 『 『 『 『 The circuit block diagram of the internal structure; "Fig. 10" is the "data sheet of the fourth picture "11th picture" in the "Fig. 4 crystal display is not on the board;" The tape package is attached to the liquid. Fig. 12 is the data welding of the liquid crystal display panel in the "U". The "Fig. 13" is the second embodiment of the liquid display device according to the present invention: the bulk circuit ; 『 『 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 Figure 15 is based on the "No. 13" towel number - the data output integrated circuit is set to ^ drama "筮 ^ 贝 7 10 output channel; brother 16 map" according to "13th picture" The first ~ invitation number will be the data round out of the integrated power out of the election. "The heart is the (four) micro material out of the wheel; the picture is based on the "picture 13" in the first - fish No. 1 will release the poor material round _ + , 罘 one copper out of the 4 "18th figure ^ 1 out of the round out channel;" is the data according to the second embodiment of the present invention with the tape, j Zhijie 1Γ I3 Figure 蒗 资料 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片 片Package: The picture is the data of the liquid crystal display in the "Fig. 19". The soldering part is set in the liquid =: - Figure: is the second embodiment of the present invention according to "Fig. 13" . ',, ~, the different shape of the data on the shell circuit, the tape roll seal. 苐22 picture" is attached to the liquid crystal display board "21st tape package"; <Bei shake volume" 』 is the data pad part of the liquid crystal display panel in "Fig. 22". _ [Main component symbol description] 2 Array type liquid crystal display panel 4 data driver 6 gate driver 7 liquid crystal cell 8 timing controller Kawasaki integrated circuit % 16 data integrated circuit 20 signal controller 32 gamma voltage portion 34 offset The register unit 36 locks the state digital to analog converter (DAC) 37 1292144 40 positive (P) decoding unit 42 negative (N) decoding unit 44 multiplexer (MUX) unit 46 output buffer unit 102 liquid crystal display Board 104 poor material driver 106 brake driver 108 timing controller 110 data tape package (TCP) 112 data TCP pad 114 data pad 116 data integrated circuit 118 connection 120 signal controller 130 channel selector 132 gamma voltage Generator 134 offset register portion 136 latch portion 138 digital to analog converter (DAC) 140 positive (P) decoding unit 142 negative (N) decoding unit 38 1292144 144 multiplexer (MUX) 146 output buffer 160 Data output pad group 164 fake data output pad group 180 data input pad group 184 false data output pad group 186 data pad portion 260 first data output channel group 262 second data output channel group 264 false output channel group 416 Data integrated circuit 510 data TCP 518 link 560 first data output pad group 562 second data output pad group 564 fake data output pad group 580 data input pad group 586 data pad 610 data TCP 660 first data output pad group 662 second data output Pad group 1292144 664 False data output pad 680 First data input pad group 682 Second data input pad group 684 False data input pad group 686 Data pad part CS1 First channel control signal CS2 Second channel control signal CS3 third. Channel control signal CS4 fourth channel control signal DLl-DLm data line GLl-GLn gate line GND ground voltage source OP1 first selection pin OP2 second selection pin P1 first channel selector signal P2 second channel Selector signal POL Complex control signal SRI 1st offset register SR642 642 offset register SSP Source start pulse ssc Source sampling time signal 40 1292144 SOE source output enable signal REV Reverse select signal TFT thin film Crystal VCC Voltage Source VD Alizarin Data VDeven Even Digital Element VDodd Odd Element Information 41

Claims (1)

^^144, the scope of application for patents · · a type of wafer film, including · · - data integrated circuit, has a Wei round-out channel; out of the blind channel from the blind channel to contact the ground through the use of Pixel data; and release tape 2. Tape and reel package, the output pad associated with the wheel-out channel of the data volume body circuit? ...'This information is as follows:: The wafer polar film described in item 1 of the profit range, including: Out, first, and tiger profit-generating a channel selection signal to select the data # 3.如申;:专用= Lin _ domain selection 峨 to _ Tao. In the middle of the road, the number of money is several rounds. For example, the Shenzhi 1 round-out channel is set to a false round-out channel. Rolling out the wafer film of the wafer, wherein the ribbon group of the tape-and-reel package is connected to the dummy channel. The L-channel and one of the dummy-transmissions. 5. The wafer-layer film of claim 4, wherein the dummy wheel-out pad group is floating. And, the false output is teased with the wafer sheet film as described in claim 4, and the dummy output channel is combined with the dummy output pad group.疋 疋仏 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固 固. The output pad is connected to δ· as described in the second paragraph of the patent application scope, wherein the selection signal generates 42 ^ 292 144, the mouth is generated according to at least one of the shell lines to generate the channel selection signal, and Some of the data integrated circuits related to the resolution required by the kilogram, the width of the tape and reel package mounted on the circuit, and some input lines for the data of the element. The wafer board film of claim 2, wherein the channel selector is a data integration circuit, wherein the selection signal generator comprises: two and a second selection terminal connected to the first voltage source and the a second voltage source for generating the pass-through selection signal and providing the generated channel selection signal to the device. The film of the wafer according to claim 2, wherein the data integrated circuit Included in the offset register portion, continuously providing the sampling signal; a latching portion that locks the pixel data in response to the sampled signal from the offset register portion; 孀-digital to analog conversion Will come from the bolt The data of the part is converted to the analog data; and the buffer is used as a buffer for the halogen data from the digital to analog converter to provide the data to a plurality of data lines. The wafer sheet film according to item 10, wherein the channel selection device selects any one of the I, j, K and L numbers of the data output channel (wherein Ί is an integer less than J, and j is one less than Κ The integer is 一, which is an integer of less than L.) 2. The wafer plate as described in the scope of claim n uses the W, x, Y, and ζ offset registers to the 'mountain, middle The channel selector 4 and the buffer register are integers) and the related signal (where W, X, the material rounds out the channel, the number of times, the number J, the Kth and the Jth, ... A tribute drives the integrator 3 · If Shen Shen directly sees one of the next states. 'The patent 槐 槐 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 The material output through the chip, comprising: a data integrated circuit comprising a plurality of wheels - a second output a track area; if the pass is divided into a first-and-=-then, which is selected from the first and the second:_out channel groups, the second output channel area is provided to provide the pixel data; and the volume: volume The strip type film, as described in the application of the second item of the second output channel area, includes: The shout generator 'generates the channel's channel to select the first-fish ^-secret output channel group to provide the channel to select the position to select the channel to select state 0 i6+ as claimed in the patent 丨 4 item, the lang film, ★ Non-selected round out = road is the false return of the fabric road _ road and (four) material - 舆 two out of the channel area. Side 44 I292l44 (10), (four) tape and tape package, 莆,, 3 L3 read scale The group connects the first-and the first-out dry-passing pair of false soldering rafts to connect the false wheel-out channel. Staying and losing 8· As described in the scope of the patent scope of the application, the sheet film of the dummy material group is floating, wherein the dummy wheel is out of the channel film of the channel Given - fixed band anti-square; the false output channel and the false pad group. The wafer film according to item 15 of the invention, wherein the selection signal is generated according to at least one of the data lines to generate the channel selection signal, and the resolution of the (four) phase _, data Integral================================================================================================= The selection signal generator comprises: = and the - terminal - the connection is connected to the first source and the second circuit selection signal and the generated channel selection signal, the channel 22, the axis 14, the accretion The electric-offset temporary turn portion is provided with the sampling signal; the lock detecting portion locks the halogen data in response to the m shift register portion