1291790 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種防呆裝置，尤指一種可保護電子裝置之電源輸出防 呆裝置。 【先前技術】 請參閱中華民國專利公告第414339號，習知電源供應器係包含有至少 一個電源模組及一控制電路，各電源模組係相互並聯，且每一電源模組至 少包括有一整流電路、一主電源、一常備電源及一 pWRGD產生電路，該 整流電路係經由其輸入端輸入一市電（交流電流）後，將該交流電源整流1291790 IX. Description of the Invention: [Technical Field] The present invention relates to a foolproof device, and more particularly to a power supply output foolproof device capable of protecting an electronic device. [Prior Art] Please refer to the Republic of China Patent Publication No. 414339. The conventional power supply system includes at least one power module and a control circuit. The power modules are connected in parallel with each other, and each power module includes at least one rectification. a circuit, a main power supply, a standing power supply, and a pWRGD generating circuit, the rectifying circuit is rectified by inputting a mains (alternating current) through an input terminal thereof
成為了直流電壓，再分別電連接_主電源之—端及該常備之—端；該主 電源係電連接該PWRGD產生電路，且具有—霞（+5V)輸出端；該常 備電源係電連接至触電關驗制單元，且具有—f備電壓（+5v)輸出 端，该主電源開關控制單元其一端係電連接至一主機♦反，另一端則連接至 :亥主屯源及3 PWRGD產生電路’當_交流電源輸人該整流電路經過整流 後連接正/爪龟路之$備電源及該主電源分別會產生一常備電壓及一主電 壓’同時，該常備電源會產生—5V f備龍給主機板，連接主電源開關 控制單源之域板剩斷是麵_電賴組之主魏啟動，若為是，該 巧機板_送-LGW (G.W町〕電位ps_Gn _至該主賴開關控制 匕龜雜收端，主電賴關控制單元則傳送—控制信號至主電源 二L啟動’當主機板傳送High電位㈣訊號時，電源供應器便停 作，糸統亦停止工作。 2面標準EPS規格電源供應器之2恤輸電璋係在第响為㈣訊 格電源供應器之2〇pin輸料則於第响為押-011訊號 機板並H麟，該連接線具備—插麟可供電予電腦主 +5Vd、二，之連結谭連接電源供應11之輸電槔而可傳送複數電位（如 曰==rri2vdc…等）之電力，主機板之_师[㈣信號皆 =之^門碰及輪電埠的第i6pm傳送到電源供應器峰來控制電源供應 EPS __埠為例，其電娜與信號端子的 匕疋義，㈣1接腳至第24接腳之定義依序為·+3鳥，+3幾，咖， 1291790 +5Vdc，GND，+5Vdc，GND，ΡΟΚ，+5Vsb，+12Vdc，+12Vdc，+3.3Vdc， +3.3Vdc，-12Vdc，GND，PS-ON，GND，GND，GND，N/C，+5Vdc，+5Vdc，It becomes a DC voltage, and is electrically connected to the end of the main power supply and the standby end; the main power supply is electrically connected to the PWRGD generating circuit, and has a Xia (+5V) output terminal; the standing power supply is electrically connected. To the electric shock detection unit, and having a -f standby voltage (+5v) output terminal, the main power switch control unit has one end electrically connected to a host ♦ reverse, and the other end is connected to: the main source and the 3 PWRGD generating circuit 'When _ AC power is input, the rectifying circuit is rectified and connected to the standby power supply and the main power supply respectively generates a standing voltage and a main voltage respectively. At the same time, the standing power supply generates -5V f standby dragon to the motherboard, connected to the main power switch control single source domain board is broken _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The main switch controls the tortoises and the terminal, and the main control unit transmits the control signal to the main power supply 2L. When the main board transmits the High potential (four) signal, the power supply stops and the system stops. Work 2 2-sided standard EPS specification power supply 2 shirt The transmission line is in the second ring of the (4) signal power supply, the 2〇pin feed is in the first ring of the -011 signal board and H Lin, the connection line has - plug the power supply to the computer main +5Vd, two The connection between Tan and the power supply of the power supply 11 can transmit the power of the complex potential (such as 曰 == rri2vdc..., etc.), and the i6pm transmission of the motherboard [(4) signal = ^ gate and the wheel 埠To the power supply peak to control the power supply EPS __埠, for example, the meaning of the electric and signal terminals, (4) 1 pin to the 24th pin are defined as +3 birds, +3, coffee , 1291790 +5Vdc, GND, +5Vdc, GND, ΡΟΚ, +5Vsb, +12Vdc, +12Vdc, +3.3Vdc, +3.3Vdc, -12Vdc, GND, PS-ON, GND, GND, GND, N/C, +5Vdc, +5Vdc,
+5Vdc，+5Vdc，GND，該插接埠由第j接腳至第24接腳之定義亦同於上 述、，市售之電源輸出線通常皆設有防呆結構，令該連結埠或該插接埠不致 因為使用者以相反角度插置錯誤而造成主機板或電源供應器損毀；然而， 習知防呆結構卻無法避免使用者誤將原本應連接主機板之插接埠連接至電 源供應器，將應連接電源供應器之連結埠錯誤插接至主機板，使用者若是 將該連結軌缝接私減且錯誤之組合連接域減電祕應器並予 以開機後，由於習用連結埠與插接埠中負責傳輸ps-〇nm號之號端 子皆位於第16pin (ATX規格20pin連接埠則皆位於第14pin)，主機板發出 之ps-〇n訊號仍會透過連結琿藉由插接埠之第16ρώ (或第卿心傳送至電 源供應器内部，令其啟動主電源供應並造成主機板損毀，帶給使用者莫大 困擾，且制電驗應H之輸料，以及其崎電路祕電區之腳位配置， 皆為了配合與插接主機板之插接埠腳位相互—致，使該電源供之電路 板電路佈局僵化、無雜，輸電埠上之腳_為了連接至電路板上對等電 位之接電區而導致繞道頻繁，無形中亦增加了業者之製造成本。 【發明内容】 本發明之主要目的，在赠決上述之缺失，敎缺失之存在，本發明 提供-種W輸出防雜置，討有效避免仙者將其上插接埠與連結埠 =接相反後’造成電子裝置之傷害，並A幅簡化電源供應器電路板之電路 為達上述目的，本發明之電源輸出防呆裝置，包含一電源供應器，呈 有—電路板’該電路板上設有複鮮嗎位之接電區，且於該電源 表n電性連接該接電區之輸電埠，於該輸料上接設一連接 tir觀有—對應連接該輸電較連結埠，另端顺有-連接至一電 二㈣反之插麟’且錢轉與插接埠场應該輸電埠設有複數用以傳 訊號腳位設置位置之對等位置 :編位之腳位’其中该插接谭上具備一控制該電源供應器作動之ps-on訊 旒腳位，且該輸電埠相對於該插接埠上 係為一空腳位或HIGH電位。 1291790 藉由以上手段，當使用者誤將該連結埠與插接埠插置相反時，訊 號則無法透過輸電琿之空腳位或HIGH電位傳遞，而達到保護電子裝置之 功效，並能大幅簡化該電路板之電路佈々，將輸電淳上相同電位之腳位儘 可能配置於鄰近區域，有效改善習知電路板因輸電埠須配合與插接淳之腳 位相-致，較為僵化、無彈性，導致為了連接電路板上對等電位之接電區 而須以不必要的繞道方式來連結。 【實施方式】 有關本發明之詳細制及技術魄，現脑合圖式說明如下： 請參閱『第1圖』以及『第2圖』，係本發明之較佳實施例及腳位配置 示意圖，如圖所示：本發明之電源輸出防呆裝置，包含一電源供應器1〇， 該電源供應器1G畴設有-電路板2〇，魏雜2()±設有複數電位各異 之接電區21、22等，該電路板20上之接電區21、22等係區分不同區塊分 離設置，且於該電源供應器1〇表面設有一輸電埠3〇，該輸電璋3〇内則設 有複數導接件31連接該接親2卜22 #而具備複數恤，該導接件31 一 係連接該輸料3G職，其另端騎伸並可垂直連接於該接電區21、^ 等，一連接線40，其一端設有一對應連接該輸電埠3〇之連結埠41，該連 接線40另端則設有一插接埠42，該插接埠犯係用以接設一電腦主機板5〇 之插接座51，而得以供電予該電腦主機板5〇，且連結璋41與插接埠幻上 相對該輸電埠30設有複數用以傳輸該電位之腳位，而該連結埠41與插接 埠42之相對腳位係以連接線4〇跳接形成不相同電位，該輸電埠3〇、連結 埠41與插接埠42可為一具備24腳位之EPS規格連接埠，或為一具備2〇 腳位之ATX規格連接埠，而不以圖式所繪24腳位之Eps規格連接埠為限。 該輸電埠30由第1接腳至第24接腳之定義依序為· +12vdc，gnd，g+5Vdc, +5Vdc, GND, the definition of the plug from the jth pin to the 24th pin is the same as above. The commercially available power output line usually has a foolproof structure, so that the link or the The plug-in port does not cause the motherboard or power supply to be damaged due to the user inserting the error at the opposite angle; however, the conventional foolproof structure cannot prevent the user from accidentally connecting the plug-in port that should be connected to the motherboard to the power supply. The connector of the power supply should be connected to the motherboard incorrectly. If the user sews the link and erroneously connects the domain to the power reducer and turns it on, the link is used. The terminals that are responsible for transmitting the ps-〇nm number in the plug-in port are all located at the 16th pin (the ATX-size 20-pin port is located at the 14th pin), and the ps-〇n signal from the motherboard will still be connected through the port. The 16th ώ (or the first heart is transmitted to the inside of the power supply, so that it starts the main power supply and causes the motherboard to be damaged, which brings great trouble to the user, and the power supply test H feeds, and its circuit circuit The position of the area is configured for The plug-in pins of the plug-in motherboard are mutually integrated, so that the circuit layout of the power supply is rigid and non-heterogeneous, and the foot of the power transmission is connected to the power-on area of the equipotential on the circuit board. The invention causes the bypass to be frequent, which inevitably increases the manufacturing cost of the manufacturer. SUMMARY OF THE INVENTION The main object of the present invention is to provide the above-mentioned deficiency and the absence of defects, and the present invention provides a kind of W output anti-missing, which is effective to avoid The power supply output foolproof device of the present invention includes a power supply by the singer connecting the splicing port and the connecting 埠= connection, causing damage to the electronic device, and simplifying the circuit of the power supply circuit board. The supplier is provided with a circuit board, and the circuit board is provided with a power receiving area of the fresh state, and the power meter n is electrically connected to the power transmission area of the power receiving area, and a connection is connected to the power feeding unit. Tir view has - corresponding connection to the transmission is more connected, the other end is connected - connected to a second (four), and vice versa, and the money transfer and plug-in market should be transmitted, and the number is used to set the position of the signal position. Peer-to-peer position: the position of the position' The plug-in tan has a ps-on signal pin for controlling the power supply, and the power port is an empty pin or a HIGH potential with respect to the plug port. 1291790 By the above means, When the user mistakenly inserts the connector 插 with the plug 埠, the signal cannot be transmitted through the empty pin or the HIGH potential of the power transmission, thereby achieving the effect of protecting the electronic device and greatly simplifying the circuit layout of the circuit board. As far as possible, the pin of the same potential on the power transmission is placed in the adjacent area, which effectively improves the conventional circuit board because the transmission does not need to match the pin position of the plug, which is relatively rigid and inelastic, resulting in the connection on the circuit board. The electric field of equal potential must be connected by unnecessary bypass. [Embodiment] The detailed description and technical specifications of the present invention are as follows: Please refer to "1" and "2nd" FIG. 3 is a schematic diagram of a preferred embodiment and a pin configuration of the present invention. As shown in the figure, the power output foolproof device of the present invention includes a power supply 1〇, and the power supply 1G domain is provided with a circuit board. 2〇 , Weiza 2 () ± is provided with a plurality of different potentials of the electrical contact areas 21, 22, etc., the electrical connection areas 21, 22 on the circuit board 20 are separated from different blocks, and the power supply 1 The surface of the crucible is provided with a power transmission port 3〇, and the transmission port 3 is provided with a plurality of connecting members 31 connected to the connecting member 2b 22# and having a plurality of shirts, and the connecting member 31 is connected to the 3G job. The other end of the connecting line 40 is provided with a plug-in connection 41 corresponding to the power transmission port 3, and the other end of the connecting line 40 is provided with a plug. The connector 42 is used to connect a plug-in base 51 of a computer motherboard 5, and is powered to the computer motherboard 5, and the connector 41 is connected to the plug-in phantom. The 埠30 is provided with a plurality of pins for transmitting the potential, and the opposite leg of the connecting 埠41 and the plug 埠42 are jumped to form a different potential by the connecting wire 4〇, and the connecting port 41〇 The plug-in port 42 can be an EPS specification port with a 24-pin position, or an ATX-size port with a 2-pin position, instead of the 24-pin position drawn in the figure. The Eps specification is limited to the limit. The definition of the power transmission port 30 from the first pin to the 24th pin is +12vdc, gnd, g
ND，GND，GND，GDN，+5VDC，+5VDC，+5VDC，+3.3VDC，+3.3VDC，POK，+12V DC，GND，GND，N/C，· 12 VDC，GND，+5 VDC，+5 VDC，+5 VDC，+3.3 VDC，+3 ·3 VD C，PS-ON。 ’ 該插接埠42由第1〜24接腳之定義則依序為：+3 3VDC，+3 3VDC，GND， +5 VDC，GND，+5 VDC，GND，P〇K，+5 VSB，+12 VDC，+12 VDC+3.3 VDC，+3.3 VD C，-12 VDC，GND，PS-ON，GND，GND，GND，N/C，+5 VDC，+5 VDC，+5 VDC，GND。 1291790 其中，該插接埠42上第I6pin係為一用以傳輸pS-on訊號致動該電源 供應器10之ps-on訊號腳位，該pS_on訊號腳位係用以接受該電腦主機板 50傳輸之ps-on訊號而控制該電源供應器5〇作動供電，且該輸電埠3〇相 對於該插接埠42上ps-on訊號腳位設置位置之對等位置第16pin則為一空 腳位（或為一 HIGH電位），當使用者誤將該連結埠41與插接埠42插置相 反時，ps-on訊號則無法透過輸電埠3〇之空腳位（或ffiGH電位）傳遞， 而達到有效保護電腦主機板50之功效，並能大幅簡化該電路板2〇之電路 佈局，可有效避免習知第16pin具有電壓位準的腳位，因使用者錯誤插接， 而々黾源供應為50誤啟動之情事發生；即便使用者以一條標準之Eps規格 之24腳位連接線（或為一 20腳位之ΑΤχ規格連接線），插接至主機板％， 其與電源供應裔20相接之連結端，由第丨接腳至第24接腳之定義依序為： +3.3Vdc，+3.3Vdc，GND，+5Vdc，GND，+5Vdc，GND，POK，+5Vsb， +12Vdc，+12Vdc，+3.3Vdc，+3.3Vdc，-12Vdc，GND，PS-ON，GND，GND， GND，N/C，+WdC，+5Vdc，+5Vdc，+5Vdc，GN〇 (請見先前技術），由 於電源供應器20之輸電埠30第I6pin設定為空腳位或HIGH電位，主機板 50之ps-on訊號仍然無法傳送到電源供應器2〇内部，啟動該電源供應器劝。 請參閱『第3圖』，係本發明輸料相對祕板接電區之電位區塊示意 圖，如圖所示：本發明係將相㈤電位之腳位設置於輸電淳3〇之同一電位= 塊上，例如第1、2pm同為+12VDC之電位，則設於輸電琿3〇之第一電位 區塊30a ;第2、3、4、5、6、14、15pin同為GND電位，則設於該輸電琿 30之第二電位區塊30b ;第7、8、19、20、21pin同為+5VDC之電位，則 設於該輸電埠3G之第三電位區塊3Ge ;第1()、u、22、23加同為+3 3vdv， 則設於該輸電埠30之第四電位區塊3〇d。 如上所述’將輸電埠30上相同電位之腳位儘可能配置於同一電位區 塊，可有效改善習知電路板20因輸電埠30須配合與插接琿^之腳位相一 致，較為僵化、無彈性，導致輸電槔3〇為了連接至電路板2〇上對等電位 之接電區U、22等，_以不必要的燒道方絲連結，大幅簡化電源供應 器10電路板20之電路佈局，且本發明可有效避免使用者將其上插接埠汜 與連結埠41插接相反後，造成電源供應器2〇誤啟動之特性，迄今尚未發 1291790 展並用於本發明之技術領域中。 圍 以上僅為本發明的較佳實施例而已，並非用來限定本發明之實施範 發明=;明申請專利範圍之内容所為的等效變化輿修飾，皆應為本 1291790 【圖式簡單說明】 第1圖，係本發明之較佳實施例示意圖 第2圖，係本發明之腳位配置示意圖 第3圖，係本發明之電位區塊配置示意圖 【主要元件符號說明】 10.............電源供應器 20 .............電路板 21 .............接電區 22 .............接電區 30 .............輸電埠ND, GND, GND, GDN, +5VDC, +5VDC, +5VDC, +3.3VDC, +3.3VDC, POK, +12V DC, GND, GND, N/C, · 12 VDC, GND, +5 VDC, + 5 VDC, +5 VDC, +3.3 VDC, +3 ·3 VD C, PS-ON. The plug-in port 42 is defined by the 1st to 24th pins in the following order: +3 3VDC, +3 3VDC, GND, +5 VDC, GND, +5 VDC, GND, P〇K, +5 VSB, +12 VDC, +12 VDC + 3.3 VDC, +3.3 VD C, -12 VDC, GND, PS-ON, GND, GND, GND, N/C, +5 VDC, +5 VDC, +5 VDC, GND. 1291790, wherein the I6pin of the plug port 42 is a ps-on signal pin for transmitting the pS-on signal to activate the power supply 10, and the pS_on signal pin is used to accept the computer motherboard 50. The power supply is controlled by the transmitted ps-on signal, and the power supply 埠3〇 is an empty position with respect to the peer position of the ps-on signal pin setting position on the plug port 42. (or a HIGH potential), when the user mistakenly inserts the connection port 41 and the plug port 42, the ps-on signal cannot be transmitted through the empty pin (or ffiGH potential) of the power transmission port. The utility model can effectively protect the computer motherboard 50, and can greatly simplify the circuit layout of the circuit board, and can effectively avoid the pin of the 16th pin having the voltage level, and the user is mistakenly plugged in, and the source is supplied. For the 50-false start situation; even if the user uses a standard Eps specification 24-pin cable (or a 20-pin ΑΤχ specification cable), plugged into the motherboard %, and the power supply 20 The connection end of the connection, from the third pin to the 24th pin The order is: +3.3Vdc, +3.3Vdc, GND, +5Vdc, GND, +5Vdc, GND, POK, +5Vsb, +12Vdc, +12Vdc, +3.3Vdc, +3.3Vdc, -12Vdc, GND, PS-ON , GND, GND, GND, N/C, +WdC, +5Vdc, +5Vdc, +5Vdc, GN〇 (see previous technique), because the power supply 20 of the power supply 20 I6pin is set to empty or HIGH At the potential, the ps-on signal of the motherboard 50 still cannot be transmitted to the inside of the power supply 2, and the power supply is activated. Please refer to "Fig. 3", which is a schematic diagram of the potential block of the power transmission area of the relative material of the present invention. As shown in the figure, the present invention sets the phase of the phase (5) potential to the same potential of the transmission 淳3〇= On the block, for example, the first and second pm are the same as the potential of +12 VDC, and the first potential block 30a of the power transmission 珲3 ; is set; the second, third, fourth, fifth, sixth, fourteen, and fis 15pin are the GND potential, then The second potential block 30b is disposed in the power transmission port 30; the seventh, eighth, 19, 20, and 21 pin are the same potential of +5 VDC, and are disposed in the third potential block 3Ge of the power transmission port 3G; , u, 22, 23 plus +3 3vdv, is set in the fourth potential block 3〇d of the power transmission port 30. As described above, the position of the same potential on the power transmission port 30 is disposed in the same potential block as much as possible, which can effectively improve the conventional circuit board 20 because the power transmission line 30 must be matched with the pin position of the plug-in port, and is relatively rigid. Inelastic, resulting in a power transmission 〇3〇 in order to connect to the power-on areas U, 22, etc. of the equipotential on the circuit board 2, _ with unnecessary burn-in square wire connection, greatly simplifying the circuit of the power supply 10 circuit board 20 Layout, and the present invention can effectively prevent the user from inserting the upper plug and the connecting port 41 oppositely, thereby causing the power supply 2 to be delayed. Therefore, it has not been issued yet and is used in the technical field of the present invention. . The above is only the preferred embodiment of the present invention, and is not intended to limit the implementation of the present invention. The equivalent variation and modification of the content of the patent application scope are as follows: 1291790 [Simple description of the drawing] 1 is a schematic view of a preferred embodiment of the present invention. FIG. 2 is a schematic view showing the arrangement of the position of the present invention. FIG. 3 is a schematic diagram of the configuration of the potential block of the present invention. ........Power Supply 20 .............Circuit Board 21 .............Power Area 22 ..... ........Power-up area 30.............Power transmission埠
30a.............第一電位區塊 30b.............第二電位區塊 30c.............第三電位區塊 30d.............第四電位區塊 31 .............導接件 40 .............連接線 41 .............連結埠 42 .............插接槔 50 .............電腦主機板 51 .............插接槽30a..................the first potential block 30b.............the second potential block 30c........... .. third potential block 30d........the fourth potential block 31.............the guide 40... .......Connecting line 41 .............Connecting 埠42.............Docking 槔50....... ......computer motherboard 51.............plug slot