1291738 〇9114twfl.doc/006 96-3-30 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路的製造方法，且特別是 有關於一種淺溝渠隔離區（Shallow Trench Isolation，STI) 的製造方法。 【先前技術】 一完整之積體電路通常是由許多的電晶體元件體所組 成，爲了避免這些相鄰的電晶體之間發生短路（Short Circuit)，必須在這些相鄰之電晶體之間，形成用來將元件 隔離之隔離區。典型的元件隔離區係形成於稠密的半導體 電路，例如是記億體元件中相鄰的場效電晶體(Field Effect Transistor，FET)之間，藉以減少由場效電晶體產生的漏電 流(Charge Leakage)現象。 淺溝渠隔離法是一種利用非等向性蝕刻的方式在半導 體基底中形成溝渠，然後再於溝渠中塡入氧化物，以形成 元件之隔離區的技術。由於淺溝渠隔離法所形成之隔離區 具有可調整大小（Scalable)的優點，並且可避免傳統區域氧 化（LOCOS)法隔離技術中鳥嘴侵蝕（Bird's Beak Encroachment)的缺點，因此，對於次微米（Sub_Micron)的金 氧半導體(Metal Oxide Semiconductor，M0S)製程而言，是 一種較爲理想的隔離技術。 第1A圖至第1D圖所示，其繪示爲習知一種淺溝渠隔 離區的製造流程剖面示意圖。 請參照第1A圖，習知形成淺溝渠隔離區的方法係首先 1291738 09114 twfl.doc/006 96-3-30 在一基底10上形成一硬罩幕層l2。之後，在硬罩幕層12 上形成一圖案化之光阻層。然而，在將光阻層M圖案化的 過程中，因光阻層Η與硬罩幕層12之間具有一作用力之 故，因此，在預定形成溝渠處之光阻層I4可能會無法清除 乾淨，而使得光阻殘留物16殘留在硬罩幕層12上。 之後，請參照第1Β圖，以光阻層14爲一蝕刻罩幕進 行一蝕刻製程，以圖案化硬罩幕層12。然後，再以光阻層 I4與硬罩幕層I2爲一蝕刻罩幕進行另一触刻製程，以圖案 化基底10，而於基底10中形成一溝渠18。由於在先前的 步驟中，硬罩幕層12之表面上係殘留有殘留物16，因此於 圖案化硬罩幕層12與基底10之過程中，蝕刻氣體必須先 將殘留物16蝕刻完之後，才能繼續蝕刻殘留物16底下之 基底10°如此’便造成了有殘留物16存在之處與未有殘留 物16存在之處的蝕刻速率不均勻，而於溝渠18中形成了 —島狀缺陷20。 繼之，請參照第1C圖，先將光阻層14移除，再於溝 渠18中塡入一絕緣層22。之後，請參照第1D圖，將罩幕 層12移除之後，即形成一淺溝渠隔離區。然而，由於島狀 缺陷2〇係爲砂材質’因此其存在於淺溝渠隔離區中，非但 會影響淺溝渠隔離區隔離的能力，且倘若島狀缺陷20形成 在車父非近溝渠18之邊緣處，還容易導致元件漏電流。 【發明内容】 因此’本發明的目的就是在提供一種淺溝渠隔離區的 製造方法，以防止島狀缺陷形成於淺溝渠隔離區中。 5 1291738 96-3-30 09114 twfl.doc/006 本發明的另一目的是提供一種淺溝渠隔離區的製造方 法’以使淺溝渠隔離區能有效發揮隔離功效，避免元件產 生漏電流。 本發明提出一種淺溝渠隔離區的製造方法，此方法係 首先在一基底上形成一硬罩幕層。接著，對此硬罩幕層之 一表面進行一離子轟擊步驟。其中，此離子轟擊步驟所使 用之一電漿氣體例如是N20、02、N2或Ar。且執行離子轟 擊步驟時之溫度例如是攝氏200度至攝氏500度。另外， 於離子轟擊步驟中所通入之氣體流量例如是150 seem 至 3000 seem。而執行離子轟擊步驟時之壓力例如是3 mTorr 至2 Tort-再者，執行離子轟擊步驟之電功率例如是100 w 至1000 W。之後，在硬罩幕層之經離子轟擊處理之表面上 形成一光阻層。接著，進行一曝光與顯影製程，以圖案化 光阻層，暴露出預定形成溝渠之處。在此，由於硬罩幕層 之表面已經由離子轟擊處理，因此在光阻層之顯影製程 中，經曝光後之光阻層可被完全的清除乾淨，而不會殘留 在硬罩幕層上。繼之，以光阻層爲一蝕刻罩幕圖案化硬罩 幕層，之後再以光阻層與硬罩幕層爲一蝕刻罩幕圖案化基 底，而於基底中形成一溝渠。在本發明中，亦可以先將光 阻層移除之後，再直接以硬罩幕層爲一蝕刻罩幕圖案化基 底，而於基底中形成溝渠。繼之，將光阻層移除之後，於 溝渠中塡入一絕緣層，接著再將硬罩幕層移除，以形成一 淺溝渠隔離區。 本發明提出一種淺溝渠隔離區的製造方法，此方法係 1291738 09114 twfl.doc/006 96-3-30 首先在一基底上形成一硬罩幕層。接著，在硬罩幕層之表 面上形成—薄材質層，例如是1氧化層在：幕= 化層上形成一光阻層。繼之，進行一曝光與顯影製程，以 圖案化光阻層，暴露出預定形成溝渠之處。在此，由於薄 氧化層與光阻層之間之作用力較爲薄弱，因此在光阻層之 顯影製程中，經曝光後之光阻餍可被完全的清除乾淨，而 不會殘留在薄氧化層上。繼之’以光阻層爲一蝕刻罩幕圖 案化硬罩幕層。然後再以光阻層與硬罩幕層爲一蝕刻罩幕 圖案化基底’而於基底中形成〜溝渠。在本發明中，亦可 以先將光阻層移除之後，再直接以硬罩幕層爲一蝕刻罩幕 圖案化基底’而於基底中形成溝渠。繼之，將光阻層移除 之後，於溝渠中塡入一絕緣層，接著再將硬罩幕層移除， 以形成一淺溝渠隔離區。 本發明之淺溝渠隔離區的製造方法，由於其在硬罩幕 層之表面進行一離子轟擊步驟，因此可避免光阻層殘留， 進而防止島狀缺陷形成於淺溝_隔離區ψ。 本發明之淺溝渠隔離區的製造方法，由於其在硬罩幕 層之表面形成一薄材質層，因此可避免光阻層殘留，進而 防止島狀缺陷形成於淺溝渠隔離區中。 本發明之淺溝渠隔離區的製造方法，由於此方法可避 免島狀缺陷的形成，因此可提高淺溝渠隔離區之隔離能 力，並有效防止元件漏電流。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 1291738 09114 twfl .doc/006 96-3-30 細說明如下= 圖式之簡單說明： 第1A圖至第ID圖爲習知一種淺溝渠隔離區的製造流 程剖面示意圖；以及 第2A圖至第2F圖是依照本發明一較佳實施例之淺溝 渠隔離區的製造流程剖面示意圖。 圖式之標示說明： 10、100 :基底 12、104 :.硬罩幕層 14、110 :光阻層 16 :殘留物 18、114 :溝渠 2 0 :島狀缺陷 22、116 :絕緣層 102 :墊氧化層 106 :離子轟擊步驟 108 :離子轟擊處理之表面 112 :開口 【實施方式】 第2A圖至第2F圖所示，其繪示爲依照本發明一較佳 實施例之淺溝渠隔離區的製造流程剖面示意圖。 請參照第2A圖，首先提供一半導體基底100。接著， 於基底1〇〇之表面上形成一墊氧化層102，用以保護基底 1〇〇之表面。其中，形成墊氧化層102之方法例如是一熱氧 1291738 09114 twfl.doc/006 96-3-30 化法。之後，在墊氧化層l〇2上形成一硬罩幕層104。在本 實施例中，硬罩幕層104之材質例如是氮化矽。 之後，請參照第2B圖，進行一離子轟擊步驟106 ’以 對硬罩幕層104之表面進行一處理步驟，而使硬罩幕層1〇4 之表面形成一經離子轟擊處理之表面108 ◦ 在本實施例中，離子轟擊步驟106所使用之一電漿氣 體例如是N20、〇2、N2或Ar。且執行離子轟擊步驟106時 之溫度例如是攝氏200度至攝氏500度。另外，於離子轟 擊步驟106中所通入之氣體流量例如是150 seem至3000 seem。而執行離子轟擊步驟106時之壓力例如是3 rnToir 至2 Torr。再者，執行離子轟擊步驟1〇6之電功率例如是 i00 W至1000 W。在一實施例中，離子轟擊步驟106在硬 罩幕層104之表面形成了 一層薄材質層，也就是圖2B所繪 示之離子轟擊處理之表面1〇8。這一層薄材質層與光阻材質 之間的作用力係低於硬罩幕層104與光阻材質之間之作用 力。 然後，請參照第2C圖，在硬罩幕層1〇4之經離子轟擊 處理之表面上形成一光阻餍11〇。繼之，進行一曝光製 程與一顯影製程，以圖案化光阻層u〇，而形成開口 112。 其中，光阻層110之開口 Π2係暴露出預定形成溝渠之處。 値得注意的是，在上述顯影製程中，開口 112中之光 阻層110可被完全的清除乾淨。這是因爲在先前步驟中， 由於硬罩幕層1〇4之表面已經過離子轟擊處理，而硬罩幕 層104之經離子轟擊處理之表面1〇8與經曝光後之光阻層 1291738 09114twfl.doc/006 lio之間的作用力已變得相當薄弱，因此，在顯影製程後， 經曝光後之光阻層110可被完全清除乾淨，而不會殘留在 硬罩幕層104之表面。 接著，請參照第2D圖，以光阻層110爲一蝕刻罩幕進 行一蝕刻製程，以將開口 112所暴露之硬罩幕層104移除。 之後，再以光阻層110與硬罩幕層104爲一蝕刻罩幕進行 另一蝕刻製程，以圖案化基底100，而於基底100中形成一 溝渠114。 在本發明中，亦可先將光阻層110移除之後，再直接 以硬罩幕層104爲一蝕刻罩幕，而於基底100中形成溝渠 114。 之後，請參照第2E圖，將光阻層110移除。然後，再 於溝渠114中塡入一絕緣層116。其中，絕緣層116之材質 例如是氧化矽。且於溝渠114中塡入絕緣層116之方法例 如是先於基底1〇〇上全面性的沈積一絕緣材質層（未繪 示），之後以一化學機械硏磨法或一回蝕刻法移除部分絕緣 材質層，直到硬罩幕層104暴露出來。接著，請參照第2F 圖，於溝渠114中塡入絕緣層116之後，將硬罩幕層104 與墊氧化層102移除，而形成一淺溝渠隔離結構。 本發明之淺溝渠隔離區的製造方法中，由於其係利用 離子轟擊步驟106處理硬罩幕層104之表面108,因此硬罩 幕層104與光阻層110之間之作用力會較爲薄弱。如此， 後續於光阻層Π0之顯影製程中，便可將開口 112處之光 阻層110完全移除乾淨，而不會有光阻層11〇殘留在硬罩 1291738 09114twfl.doc/006 幕層104之表面上。由於光阻層no不會殘留在硬罩幕層 104之表面108，因此在蝕刻基底1〇〇以形成溝渠U4的過 程中，便可避免島狀缺陷形成在溝渠114中。 特別値得一提的是，本發明還包括利用其他的方式， 以使硬罩幕層之表面與光阻層之間的作用力減弱，藉以達 到將經曝光之光阻層完全移除乾淨之目的。例如，可以在 硬罩幕層之表面形成一薄材質層(例如是薄氧化層），之後再 於薄氧化層上形成光阻層。換言之，將先前於硬罩幕層之 表面以離子轟擊處理之步驟，以形成薄氧化層之方式取代 之。由於氧化層與光阻層之間的作用力較氮化矽材質之硬 罩幕層與光阻層之間作用力弱，因此，利用於硬罩幕層之 表面形成一薄氧化層之方式亦可以達到降低光阻層與硬罩 幕層之間之作用力之目的，進而避免於溝渠中形成島狀缺 陷。 綜合以上所述，本發明具有下列優點： 1·本發明之淺溝渠隔離區的製造方法，由於其在硬罩幕 層之表面進行一離子轟擊處理，因此可避免光阻層殘留， 進而防止島狀缺陷形成於淺溝渠隔離區中。 2·本發明之淺溝渠隔離區的製造方法，由於其在硬罩幕 層之表面形成一薄材質層，因此可避免光阻層殘留，進而 防止島狀缺陷形成於淺溝渠隔離區中。 3 ·本發明之淺溝渠隔離區的製造方法，由於此方法可难 免島狀缺陷的形成，因此可提高淺溝渠隔離區之_離％ 力，並有效防止元件漏電流。 b 11 1291738 96-3-30 09114 twfl.doc/006 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 121291738 〇9114twfl.doc/006 96-3-30 IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing an integrated circuit, and more particularly to a shallow trench isolation region (Shallow Trench Isolation, STI) manufacturing method. [Prior Art] A complete integrated circuit is usually composed of a plurality of transistor elements. In order to avoid a short circuit between these adjacent transistors, it is necessary to be between these adjacent transistors. An isolation region is formed for isolating the components. Typical element isolation regions are formed in dense semiconductor circuits, such as between adjacent Field Effect Transistors (FETs) in a body element, to reduce leakage current generated by field effect transistors (Charge) Leakage) phenomenon. The shallow trench isolation method is a technique in which a trench is formed in a semiconductor substrate by an anisotropic etching and then an oxide is implanted in the trench to form an isolation region of the device. The isolation region formed by the shallow trench isolation method has the advantage of being Scalable, and can avoid the disadvantages of Bird's Beak Encroachment in the conventional LOCOS isolation technique, and therefore, for the submicron ( Sub_Micron's Metal Oxide Semiconductor (M0S) process is an ideal isolation technology. 1A to 1D are schematic cross-sectional views showing a manufacturing process of a conventional shallow trench isolation region. Referring to Figure 1A, it is conventional to form a shallow trench isolation region by first forming a hard mask layer l2 on a substrate 10 by first 1291738 09114 twfl.doc/006 96-3-30. Thereafter, a patterned photoresist layer is formed on the hard mask layer 12. However, in the process of patterning the photoresist layer M, there is a force between the photoresist layer and the hard mask layer 12, and therefore, the photoresist layer I4 at the predetermined trench may not be removed. It is clean so that the photoresist residue 16 remains on the hard mask layer 12. Thereafter, referring to FIG. 1 , an etching process is performed on the photoresist layer 14 as an etching mask to pattern the hard mask layer 12 . Then, another etching process is performed by using the photoresist layer I4 and the hard mask layer I2 as an etching mask to pattern the substrate 10, and a trench 18 is formed in the substrate 10. Since the residue 16 remains on the surface of the hard mask layer 12 in the previous step, the etching gas must first etch the residue 16 after patterning the hard mask layer 12 and the substrate 10. In order to continue etching the substrate 10 under the residue 16, the resulting etching rate is uneven in the presence of the residue 16 and the absence of the residue 16, and an island-like defect 20 is formed in the trench 18. . Next, referring to FIG. 1C, the photoresist layer 14 is removed first, and then an insulating layer 22 is inserted into the trench 18. Thereafter, referring to FIG. 1D, after the mask layer 12 is removed, a shallow trench isolation region is formed. However, since the island-like defect 2 is a sand material', it exists in the shallow trench isolation zone, which not only affects the isolation of the shallow trench isolation zone, but if the island defect 20 is formed at the edge of the vehicle's non-near trench 18 At the same time, it is easy to cause leakage current of components. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a shallow trench isolation region to prevent island defects from being formed in shallow trench isolation regions. 5 1291738 96-3-30 09114 twfl.doc/006 Another object of the present invention is to provide a method of fabricating a shallow trench isolation region so that the shallow trench isolation region can effectively exert isolation effects and prevent leakage current from being generated by components. The present invention provides a method of fabricating a shallow trench isolation region by first forming a hard mask layer on a substrate. Next, an ion bombardment step is performed on one surface of the hard mask layer. Among them, one of the plasma gases used in the ion bombardment step is, for example, N20, 02, N2 or Ar. And the temperature at which the ion bombardment step is performed is, for example, 200 degrees Celsius to 500 degrees Celsius. Further, the flow rate of the gas introduced in the ion bombardment step is, for example, 150 seem to 3000 seem. The pressure at which the ion bombardment step is performed is, for example, 3 mTorr to 2 Tort - again, the electric power for performing the ion bombardment step is, for example, 100 w to 1000 W. Thereafter, a photoresist layer is formed on the surface of the hard mask layer subjected to ion bombardment treatment. Next, an exposure and development process is performed to pattern the photoresist layer to expose where the trench is intended to be formed. Here, since the surface of the hard mask layer has been treated by ion bombardment, in the developing process of the photoresist layer, the exposed photoresist layer can be completely removed without remaining on the hard mask layer. . Then, the hard mask layer is patterned by using the photoresist layer as an etching mask, and then the photoresist layer and the hard mask layer are used as an etching mask to pattern the substrate, and a trench is formed in the substrate. In the present invention, after the photoresist layer is removed, the hard mask layer is directly used as an etching mask to pattern the substrate, and a trench is formed in the substrate. Following the removal of the photoresist layer, an insulating layer is introduced into the trench, and then the hard mask layer is removed to form a shallow trench isolation region. The present invention provides a method of fabricating a shallow trench isolation region that is first formed on a substrate by a hard mask layer on 1291738 09114 twfl.doc/006 96-3-30. Next, a thin material layer is formed on the surface of the hard mask layer, for example, an oxide layer forms a photoresist layer on the screen layer. Following this, an exposure and development process is performed to pattern the photoresist layer to expose portions where trenches are intended to be formed. Here, since the force between the thin oxide layer and the photoresist layer is weak, in the developing process of the photoresist layer, the exposed photoresist can be completely removed without remaining in the thin film. On the oxide layer. Following the photoresist layer as an etch mask, the hard mask layer is patterned. Then, the photoresist layer and the hard mask layer are used as an etching mask to pattern the substrate' to form a trench in the substrate. In the present invention, the trench can also be formed in the substrate by first removing the photoresist layer and then directly patterning the substrate with the hard mask layer as an etching mask. Then, after the photoresist layer is removed, an insulating layer is inserted into the trench, and then the hard mask layer is removed to form a shallow trench isolation region. In the method for manufacturing the shallow trench isolation region of the present invention, since the ion bombardment step is performed on the surface of the hard mask layer, the photoresist layer can be prevented from remaining, thereby preventing island defects from being formed in the shallow trench_isolated region. The method for manufacturing the shallow trench isolation region of the present invention can prevent the photoresist layer from remaining on the surface of the hard mask layer, thereby preventing island defects from being formed in the shallow trench isolation region. The method for manufacturing the shallow trench isolation region of the present invention can avoid the formation of island defects, thereby improving the isolation capability of the shallow trench isolation region and effectively preventing component leakage current. The above and other objects, features, and advantages of the present invention will become more apparent and understood in the light <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; DETAILED DESCRIPTION OF THE INVENTION = Brief Description of the Drawings: FIG. 1A to FIG. 1D are schematic cross-sectional views showing a manufacturing process of a shallow trench isolation region; and FIGS. 2A to 2F are shallow according to a preferred embodiment of the present invention. Schematic diagram of the manufacturing process of the trench isolation zone. Description of the drawings: 10, 100: substrate 12, 104: hard mask layer 14, 110: photoresist layer 16: residue 18, 114: trench 2 0: island-shaped defects 22, 116: insulating layer 102: Pad oxide layer 106: ion bombardment step 108: ion bombardment treatment surface 112: opening [embodiment] 2A to 2F, which is illustrated as a shallow trench isolation region in accordance with a preferred embodiment of the present invention Schematic diagram of the manufacturing process. Referring to FIG. 2A, a semiconductor substrate 100 is first provided. Next, a pad oxide layer 102 is formed on the surface of the substrate 1 to protect the surface of the substrate. The method of forming the pad oxide layer 102 is, for example, a hot oxygen 1291738 09114 twfl.doc/006 96-3-30 method. Thereafter, a hard mask layer 104 is formed on the pad oxide layer 〇2. In the present embodiment, the material of the hard mask layer 104 is, for example, tantalum nitride. Thereafter, referring to FIG. 2B, an ion bombardment step 106' is performed to perform a processing step on the surface of the hard mask layer 104, so that the surface of the hard mask layer 1〇4 forms an ion bombarded surface 108. In the present embodiment, one of the plasma gases used in the ion bombardment step 106 is, for example, N20, 〇2, N2 or Ar. And the temperature at which the ion bombardment step 106 is performed is, for example, 200 degrees Celsius to 500 degrees Celsius. Further, the flow rate of the gas introduced in the ion bombardment step 106 is, for example, 150 seem to 3000 seem. The pressure at which the ion bombardment step 106 is performed is, for example, 3 rnToir to 2 Torr. Furthermore, the electric power for performing the ion bombardment step 1〇6 is, for example, i00 W to 1000 W. In one embodiment, the ion bombardment step 106 forms a thin layer of material on the surface of the hard mask layer 104, i.e., the surface 1 〇 8 of the ion bombardment treatment depicted in Figure 2B. The force between this thin layer of material and the photoresist material is lower than the force between the hard mask layer 104 and the photoresist material. Then, referring to Fig. 2C, a photoresist 餍 11 形成 is formed on the surface of the hard mask layer 1 4 by ion bombardment treatment. Next, an exposure process and a development process are performed to pattern the photoresist layer u to form the opening 112. Wherein, the opening Π2 of the photoresist layer 110 exposes a place where a predetermined trench is formed. It is noted that in the above development process, the photoresist layer 110 in the opening 112 can be completely removed. This is because in the previous step, since the surface of the hard mask layer 1〇4 has been subjected to ion bombardment treatment, the surface of the hard mask layer 104 subjected to ion bombardment treatment 1〇8 and the exposed photoresist layer 1291738 09114twfl The force between the .doc/006 lio has become quite weak, so that after the development process, the exposed photoresist layer 110 can be completely removed without remaining on the surface of the hard mask layer 104. Next, referring to FIG. 2D, an etching process is performed on the photoresist layer 110 as an etching mask to remove the hard mask layer 104 exposed by the opening 112. Then, another etching process is performed by using the photoresist layer 110 and the hard mask layer 104 as an etching mask to pattern the substrate 100, and a trench 114 is formed in the substrate 100. In the present invention, after the photoresist layer 110 is removed, the hard mask layer 104 is directly used as an etching mask to form a trench 114 in the substrate 100. Thereafter, please refer to FIG. 2E to remove the photoresist layer 110. Then, an insulating layer 116 is further inserted into the trench 114. The material of the insulating layer 116 is, for example, cerium oxide. The method of inserting the insulating layer 116 into the trench 114 is, for example, comprehensively depositing an insulating material layer (not shown) on the substrate 1 and then removing it by a chemical mechanical honing method or an etching method. Part of the insulating material layer is exposed until the hard mask layer 104 is exposed. Next, referring to FIG. 2F, after the insulating layer 116 is inserted into the trench 114, the hard mask layer 104 and the pad oxide layer 102 are removed to form a shallow trench isolation structure. In the method for fabricating the shallow trench isolation region of the present invention, since the surface 108 of the hard mask layer 104 is processed by the ion bombardment step 106, the force between the hard mask layer 104 and the photoresist layer 110 is weak. . Thus, in the subsequent development process of the photoresist layer ,0, the photoresist layer 110 at the opening 112 can be completely removed without the photoresist layer 11 remaining in the hard mask 1291738 09114twfl.doc/006. On the surface of 104. Since the photoresist layer no does not remain on the surface 108 of the hard mask layer 104, island defects can be prevented from being formed in the trench 114 during the etching of the substrate 1 to form the trench U4. In particular, the present invention also includes the use of other means to weaken the force between the surface of the hard mask layer and the photoresist layer, thereby completely removing the exposed photoresist layer. purpose. For example, a thin material layer (e.g., a thin oxide layer) may be formed on the surface of the hard mask layer, and then a photoresist layer may be formed on the thin oxide layer. In other words, the previous step of ion bombardment on the surface of the hard mask layer is replaced by a thin oxide layer. Since the interaction between the oxide layer and the photoresist layer is weaker than that between the hard mask layer and the photoresist layer of the tantalum nitride material, a thin oxide layer is formed on the surface of the hard mask layer. The purpose of reducing the force between the photoresist layer and the hard mask layer can be achieved, thereby avoiding the formation of island defects in the trench. In summary, the present invention has the following advantages: 1. The method for manufacturing the shallow trench isolation region of the present invention, since it is subjected to an ion bombardment treatment on the surface of the hard mask layer, the photoresist layer can be prevented from remaining, thereby preventing the island. Shape defects are formed in the shallow trench isolation zone. 2. The method for manufacturing the shallow trench isolation region of the present invention, since a thin material layer is formed on the surface of the hard mask layer, the photoresist layer can be prevented from remaining, thereby preventing island defects from being formed in the shallow trench isolation region. 3. The manufacturing method of the shallow trench isolation region of the present invention, since the formation of island defects can be inevitable, the detachment force of the shallow trench isolation region can be improved, and the leakage current of the device can be effectively prevented. b 11 1291738 96-3-30 09114 twfl.doc/006 Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and those skilled in the art without departing from the spirit and scope of the invention In the meantime, the scope of protection of the present invention is defined by the scope of the appended claims. 12