1291239 九、發明說明： 【發明所屬之技術領域】 本發明係有關-種^封裝技術，特別是__種 基板(substrate)之晶片封裝結構及其製造方法。 辱1雙面 【先前技術】 馨於半導體科技隨著電腦與網路通訊等產品 2具備多元化、可攜性與輕薄微小化之需求，使日 程$ 離傳統技術而朝高功率、高密度、輕、薄與微小 業脫 展。為製作更輕薄之基板，封裝製程必定更為 广、4又製程發 的產品，由於製程複雜，會有損壞率高之疑慮/'能作出符合要求 【發明内容】 有鑑於此，本發明係針對上述之困 其製造方法，以改善±述之_。 種4封裝結構及 本發明的目的之一，係在提供一曰 其係以載板做為支撐，使冓及f製造”， 生產，提高製程良率。 3 ，且可依現有流程 本發明之又一目的，#备々 制以载板做騎撐，«造方法， 技產業之需求。 t 之基板’付合現有半導體科 其係雖、料及其製造方法， 他電子裝置上。 ^ ^錢板後可製作雙面基板，方便連接於其 本發明之更— ㈢的係在提供一種晶片封裝結構及其製造方法， 5 1291239 係可使用封裝業現有製锃g 印刷電路板之流程，可降低封裝成本不需增加額外設備或製程，減少 根據本發明之晶片封裝方法，其係包 其上設置一絕緣層盥一杈供一載板， 部分料崎層上；移除部分該導電層盥 ‘祕緣層絲露出該載板的部分表面；形成—第層墓 =Γ層與該暴露出的表面;移除部分該第-金屬二: 導電，《出部分魏緣層；形成—第二金屬層於部分^第=屬亥 層上，汉置至▲少-晶片於部分該第—金屬層上；電性連接該至談1291239 IX. Description of the Invention: [Technical Field] The present invention relates to a package technology, particularly a wafer package structure of a substrate, and a method of fabricating the same. Insult 1 double-sided [prior technology] Xin in semiconductor technology with the computer and network communication products 2 with diversification, portability and thin and light demand, making the schedule from the traditional technology towards high power, high density, Light, thin and tiny industries are out of the show. In order to make a thinner and lighter substrate, the packaging process must be more extensive, and the process of manufacturing is more complicated. Due to the complicated process, there is a doubt that the damage rate is high. 'There is a requirement to meet the requirements. [Invention] In view of this, the present invention is directed to The above-mentioned method of manufacturing is difficult to improve. One of the four package structures and one of the objects of the present invention is to provide a support for the carrier to be manufactured, to improve the process yield. 3 , and according to the existing process of the present invention Another purpose is to use the carrier board as a support, the method of manufacturing, and the needs of the technology industry. The substrate of t is the existing semiconductor division, the material and its manufacturing method, on his electronic device. ^ ^钱A double-sided substrate can be fabricated behind the board, which is convenient to be connected to the present invention. (3) A chip package structure and a manufacturing method thereof are provided, and 5 1291239 can use a process of manufacturing a conventional printed circuit board in the packaging industry, which can be reduced. The package cost does not need to add additional equipment or processes, and the chip packaging method according to the present invention is reduced. The package is provided with an insulating layer for a carrier plate and a portion of the chip layer; and a portion of the conductive layer is removed. a secret edge layer exposes a portion of the surface of the carrier; forming a first layer of tomb = a layer of the layer and the exposed surface; removing a portion of the first - metal two: conducting, "exiting a portion of the edge layer; forming a second metal Layer in part ^第=属海On Han ▲ set to at least - a first portion of the wafer to - metal layer; electrically connected to the Talk
第-金屬層與該第二金屬層之至少任形成 覆；"r 及移除該載板。 I復4日日片， 依據本發明之晶㈣裝結構，其係包含：-絕称 設置於該絕緣層上；-第—金屬層，係設置於料 絕緣層上；-第二金屬層，係設於部分該第—金屬層上;、 片，係设置於該第-金屬層與該第二金屬層之至少任—； 結構’係設置於該第-金屬層與該第二金屬層之至少任―；及一保護 層’其係包》第-金制、該第二金屬層、該晶片與該部分露出的 導電層及該絕緣層。 底下藉由具體實施例配合所_圖式詳加說明，#更容易瞭 發明之目的、技内容、特點及其所達成之功效。 ’、 【實施方式】 底下係以一較佳實施例來說明本發明晶片封裝結構及其製造方 法。第1圖至第12圖所示係為依據本發明一較佳實施例晶片封裝結構 及其製造方法之各步驟結構剖視圖。 請參閱第1圖，首先，提供一載板10，載板1〇上設置有一絕緣層 20及一導電層30於絕緣層20上。於一實施例中，絕緣層2〇及導電層 30可為一體成型之已商品化結構，例如RCC/銅箔板(RCC resin/coppef)。於另一實施例中，可分為三步驟進行，先利用黏貼方式、 6 1291239 印刷、旋轉塗佈、喷塗法或齡法等f知適t的方法，將絕緣層2〇， ，如-玻輯維賴布，設置錢板1G，例如_金屬、玻璃、 =子载板上。之後’再_黏貼方式、印刷、濺鍍法、壓益 =電鍍《電鍍法，料鉍Μ，例如—_，設置在麟層2〇上、: 或噴粗=°表面亦可進行棕化、黑化、化恤、刷磨Forming at least any of the first metal layer and the second metal layer; "r and removing the carrier. I complex 4th day film, according to the crystal (four) mounting structure of the present invention, which comprises: - absolutely disposed on the insulating layer; - the first metal layer is disposed on the material insulating layer; - the second metal layer, Is disposed on a portion of the first metal layer; and a sheet is disposed on at least any of the first metal layer and the second metal layer; the structure is disposed on the first metal layer and the second metal layer At least one of; and a protective layer 'the package' of the first gold, the second metal layer, the wafer and the partially exposed conductive layer and the insulating layer. The details of the invention, the technical content, the features and the effects achieved by the invention are explained by the detailed description of the specific embodiment. [Embodiment] The wafer package structure of the present invention and a method of manufacturing the same are described below in a preferred embodiment. 1 to 12 are cross-sectional views showing the steps of a wafer package structure and a method of fabricating the same according to a preferred embodiment of the present invention. Referring to Fig. 1, first, a carrier 10 is provided. The carrier 1 is provided with an insulating layer 20 and a conductive layer 30 on the insulating layer 20. In one embodiment, the insulating layer 2 and the conductive layer 30 may be an integrally formed commercial structure such as an RCC/copper sheet (RCC resin/coppef). In another embodiment, the insulating layer can be divided into three steps, and the insulating layer can be made by using a bonding method, a 612991239 printing, a spin coating, a spraying method, or an ageing method. Glass Vireb, set the money board 1G, such as _ metal, glass, = sub-board. After the 're-sticking method, printing, sputtering method, pressure = electroplating "electroplating method, material 铋Μ, for example - _, set on the lining 2 、, : or spray coarse = ° surface can also be browned, Blackening, tempering, brushing
接^ ’請參閱第2Α圖’移除部分導電層3〇以形成複數個第—圖 11作為後續移除絕緣層2G之遮罩。於—實施例中，移除導 =層3㈣方式可綱f知的微影餘、模具侧或雷射關等方法I 成具2㈣等第一圖案化凹槽40部分接續移除部份絕緣層20形 控:：、，載,1〇的第二圖案化凹槽42，其中，可利用鑽孔、深度 二1、_射或是電製法移除該等絕緣層2()，如第姐圖所示。 开來’在導電層3G、絕緣層2G與暴露出的載板1G部分表面上 50似、^屬層5〇 ’清參閱第3圖。於一實施例中，此第一金屬層 構成、，:也，法、蒸鍍法 '無電解電鍍法或電鍵法所形成之銅材質所 化學鋼〇>、通上下層之肖。其次，在形成第一金屬層 50前可先進行 再:，3第一）]黑孔等處理增加第一金屬層5〇與絕緣層2〇之吸附力。 砂裝羽a a金屬層5〇表面亦可進行棕化、黑化、化學微蝕、刷磨或噴 圖=2處理。於又-實施例中，第-金屬層5。更可以填滿第二 繼續，，久關笛 並暴露部分絕i: 圖，移除部分第一金屬層5〇與部分導電層30 該等第一金屬、曰％形成一第三圖案化凹槽44。於一實施例中，移除 雷射雕刻的方與導電層3〇的方法可以是微影製程 '模具姓刻或 明不限於作為之，該等圖案化凹槽係作為外部線路使用，但本發 50上形成一第外^部線路之用。之後，參閱第5圖，於部分第一金屬層 中，此第二金屬^金屬層52當作此後電性連接之一接點。於一實施例 形成。其次、，―層52係利用印刷、蒸艘、濺鍍、無電解電鑛或電鍍法 第〜金屬層52係為鋁、金、銀、錫、化學鎳金、化學鎳 1291239 知粗化處理。 外化’、、、化、化子祕、刷磨或噴砂等習 又》月參H?'第6圖，以習知適當的方式，例如晶片鍵結 BondmgP_ss)，設置—或多個晶片於第一金屬層％及第：金二1; 之至少任―，其中晶片可為執行不同功能的晶片6G及晶片62曰曰 60、晶片62的主動面朝上，於—實施例中，晶片6()、晶片= 面上更包含-導電連接結構，例如連接塾(BGndingpad，圖示: 著，參閱第7圖，於一實施例中，利用導電連接結構，例如 引線72,電性連接晶片6〇、62與第一金屬層％及第二金屬層 少任-。根據上述，本發明之同—晶片6G或6 θ ^ 一金屬㈣及第二金屬層52。再者，不同晶片6Q與 而要，電性連接至不同的第一金屬層5〇及第二金屬層2，增加 計上的彈性。爾後，參閱第8圖，進行—塑封程序，形成_保護層^ 包覆該等晶片60、62、引線70、72、第一金屬層50、第二金屬‘ 52 及暴露在外的導電層3〇與絕緣層2G。根據上述，本發簡徵之」，在 於第-金屬層5G、第二金屬層52及導電層3G不需傳統的感光型保護 層，例如防焊層(s〇lder mask)保護，由保護層8〇直接接觸晶片6〇、U、 引線70、72、第一金屬層50、第二金屬層52、導電層3〇及絕緣層2〇。 如此的結構可轉決感光型保護層可能造成效崎低的問題，不僅可 以提昇信賴度，還可以省略一道光罩與微影的步驟，降低製程成本。 之後，參照第9圖及第10圖，以適當的方式移除載板1〇並暴露 出部分的第一金屬層50,並於外露的第一金屬層5〇上使用表面黏著技 術（SMT ’ surfacem〇unttechn〇l0gy)或電鍍技術形成導電結構％，例 如凸塊，以利用導電結構54電性連接至其他電子裝置上，可以以每一 晶片為單位進行切割，以形成數個晶片封裝結構，如第u圖及第12 圖。於一實施例中，依據本發明之製造方法製造而成之晶片封裝結構， 可以為：一導電層，設置於一絕緣層上，且第一金屬層，係設置於導 1291239 電層與暴露έΗ之絕緣層±，再H金麟設置於部 上三又，至少m置於該第—金屬層與該第二金屬層之至少任」， ^ -導電連接結構’例如··引線等’設置於該第—金屬層與二 if之至）任―，取後’填充—保護層，使之包覆第—金屬、層Λ、第 一金屬層、與露出部分的導電層及絕緣層。 s弟Referring to FIG. 2, a portion of the conductive layer 3 is removed to form a plurality of patterns - FIG. 11 as a mask for subsequently removing the insulating layer 2G. In the embodiment, the method of removing the conductive layer 3 (4), the method of the micro-shadow, the mold side or the laser off, etc., the method of forming the second patterned groove 40, etc. 20-shaped control::,,,,, 1 〇 second patterned groove 42, wherein the insulating layer 2 () can be removed by drilling, depth 21, _ shot or electrical method, such as the first sister The figure shows. Referring to Fig. 3, the conductive layer 3G and the insulating layer 2G are similar to the surface of the exposed carrier 1G portion. In one embodiment, the first metal layer is formed by the method of vapor deposition, the electroless plating method or the copper material formed by the electroless bonding method, and the upper and lower layers. Next, before the formation of the first metal layer 50, the treatment of the first metal layer 5〇 and the insulating layer 2〇 may be performed by the treatment of the first)] black hole or the like. The sand surface of the a a metal layer can also be browned, blackened, chemically microetched, brushed or sprayed = 2 treatment. In a further embodiment, the first metal layer 5. It is also possible to fill the second continuation, and to close the whistle and expose part of the ii: the figure, remove part of the first metal layer 5 〇 and part of the conductive layer 30, the first metal, 曰% form a third patterned groove 44. In one embodiment, the method of removing the laser engraved square and the conductive layer 3 可以 may be a lithography process, where the mold name is or is not limited thereto, and the patterned grooves are used as external lines, but The hair 50 forms an external circuit. Thereafter, referring to Fig. 5, in a portion of the first metal layer, the second metal layer 52 serves as a contact for the subsequent electrical connection. Formed in an embodiment. Next, the layer 52 is printed, steamed, sputtered, electrolessly electroplated or electroplated. The metal layer 52 is made of aluminum, gold, silver, tin, chemical nickel gold, and chemical nickel 1291239. Externalization ',,, chemistry, chemistry, brushing or sand blasting, etc., "Holiday H?' Figure 6, in a suitable manner, such as wafer bonding BondmgP_ss), set - or multiple wafers At least any of the first metal layer % and the first metal layer 1 , wherein the wafer can be a wafer 6G and a wafer 62 60 that perform different functions, and the active side of the wafer 62 faces upward. In the embodiment, the wafer 6 (), wafer = surface further includes - conductive connection structure, such as a connection 塾 (BGndingpad, shown: see Figure 7, in an embodiment, using a conductive connection structure, such as lead 72, electrically connected to the wafer 6 〇, 62 is less than the first metal layer % and the second metal layer - according to the above, the same wafer - 6G or 6 θ ^ a metal (four) and the second metal layer 52. Furthermore, different wafers 6Q and To electrically connect to the different first metal layers 5 and 2, to increase the elasticity of the meter. Then, referring to FIG. 8, a plastic sealing process is performed to form a protective layer to coat the wafers 60. 62, leads 70, 72, first metal layer 50, second metal '52 and exposed conductive layer 3 The edge layer 2G. According to the above, the present invention is characterized in that the first metal layer 5G, the second metal layer 52 and the conductive layer 3G do not require a conventional photosensitive protective layer, such as a solder mask protection. The protective layer 8〇 directly contacts the wafer 6〇, U, the leads 70, 72, the first metal layer 50, the second metal layer 52, the conductive layer 3〇, and the insulating layer 2〇. Such a structure can be transferred to the photosensitive type protection. The layer may cause a problem of low efficiency, which not only improves the reliability, but also omits a mask and lithography step to reduce the cost of the process. Then, refer to Figure 9 and Figure 10 to remove the carrier in an appropriate manner. 1〇 and exposing a portion of the first metal layer 50, and forming a conductive structure %, such as a bump, on the exposed first metal layer 5 表面 using a surface adhesion technique (SMT 'surfacem〇unttechn〇l0gy) or electroplating technique to The conductive structure 54 is electrically connected to other electronic devices, and can be cut in units of each wafer to form a plurality of chip package structures, as shown in FIGS. u and 12 . In an embodiment, according to the present invention Wafer seal manufactured by manufacturing method The structure may be: a conductive layer disposed on an insulating layer, and the first metal layer is disposed on the electrical layer of the 1291239 conductive layer and the exposed insulating layer ±, and then the H Jinlin is disposed on the upper portion, at least m The at least one of the first metal layer and the second metal layer is disposed, and the conductive connection structure 'such as a lead wire or the like is disposed in the first metal layer and the second metal layer. a protective layer covering the first metal, the germanium layer, the first metal layer, and the exposed conductive layer and the insulating layer. S
綜合上述，本發明提供一種晶片封裝結構及其製造方法 ^乍為-續’利賴板的支持，得讀作超薄之基板，進而製作= 之基再者’由於載板的支撐，使得傳統因為怕破壞基板所 白、程序付㈣化。又’其製造方法係仙電路板業現有製程即可生產， 不需增加額外設備或製程’可降低電路板成本。此外，其結構不同於 一般塗佈防焊層之方法，_保護層直接接觸金屬層、導電層、絕緣 層、晶狀雜連赌構’不僅可啸昇賴度，也可崎低塗佈防 域之成本，另運用此基板之封裝業，不需增加額外設備或製程，可 降低封裝高度達聰薄短小電子料之要求及降健體封裝成本。 以上所述係藉由實施例說明本發明之特點，其目的在使熟習該技 術者此暸解本發明之内容並據以實施，㈣限定本發明之專利範圍，In summary, the present invention provides a chip package structure and a method of fabricating the same, which is a continuation of the support of the 'Lei Lai board, which can be read as an ultra-thin substrate, and then the basis of the fabrication is further improved by the support of the carrier board. Because of fear of destroying the white of the substrate, the program pays (four). Moreover, its manufacturing method can be produced by the existing circuit board industry, and no additional equipment or process is required, which can reduce the cost of the board. In addition, the structure is different from the general method of coating the solder resist layer, and the _ protective layer directly contacts the metal layer, the conductive layer, the insulating layer, and the crystalline hybrid gambling structure, which not only can be used for smear, but also has low coating resistance. The cost of the domain, the packaging industry that uses this substrate, does not need to add additional equipment or processes, can reduce the package height to meet the requirements of the thin and short electronic materials and reduce the cost of the body package. The above description of the present invention is made by way of examples, and the purpose of the invention is to be understood by those skilled in the art.
故’凡其他未脫離本發明所揭示之精神所完成之等效修飾或修改，仍 應包含在以下所述之申請專利範圍中。 【圖式簡單說明】 第1圖至第12圖係為依據本發明一較佳實施例晶片封裝結構及及 製造方法之各步驟結構剖視圖。 【主要元件符號說明】 10 載板 20 絕緣層 30 導電層 9 1291239 40 第一圖案化凹槽 42 第二圖案化凹槽 44 第三圖案化凹槽 50 第一金屬層 52 第二金屬層 54 導電結構 60 晶片 62 晶片 70 引線 72 引線 80 保護層Accordingly, any equivalent modifications or adaptations may be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 12 are cross-sectional views showing the steps of a wafer package structure and a manufacturing method in accordance with a preferred embodiment of the present invention. [Main component symbol description] 10 carrier 20 insulating layer 30 conductive layer 9 1291239 40 first patterned recess 42 second patterned recess 44 third patterned recess 50 first metal layer 52 second metal layer 54 conductive Structure 60 Wafer 62 Wafer 70 Lead 72 Lead 80 Protective Layer