TWI291177B - Semiconductor integrated circuit device with OTP memory and programming method for OTP memory - Google Patents

Abstract

A semiconductor integrated circuit device having memory elements, state-detection circuits and control circuits is provided. In said memory elements, information is programmed by changing the element properties in an electrically irreversible manner. The state-detection circuits are constructed in a way that the states of the memory elements, which have been changed irreversibly, and the unchanged states can be detected. The control circuits are constructed in a way that the detection abilities of the state-detection circuits may be changed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a stylized method thereof, which are more compact and δ. The present invention relates to a programmable irreversible Lv Yiyi. A semiconductor integrated circuit device of a component (such as an OTP (One-Time Programmable) memory) and a programmatic method of information of a memory element thereof. The present invention is based on the priority of the present patent application No. 2004-113440, the entire disclosure of which is hereby incorporated by reference. [Prior Art] In the semiconductor integrated circuit device of recent years, even if the power supply is lowered, the permanent information of the recorded information does not disappear, and the TP memory becomes an indispensable component. ΟΤΡMemory can be widely used in the so-called dram or large-capacity memory in the use of redundancy, analog circuits for tuning purposes or code storage applications such as dark keys, and the experience of manufacturing processes, etc. It is used for wafer identification (ID) for information memory for management. For example, in the standby use of the memory, the burnt phenomenon caused by the irradiation of the laser light is used to achieve the cheapest permanent memory, and the use of the f-wire Q RQM, which can be used as a material, can be used. Save the news. In the above-mentioned Ray-Ray RQM towel, the fuse of the special fuse and the burning process using the device, the required one is generated at this time. Moreover, since the minimum size of the laser-dissolved filament is determined by the wavelength of the lightning rod f 1291177 16392pif.doc used, the step of miniaturization with other circuit parts may not match, and gradually The proportion of the occupied area becomes larger. Moreover, the laser fuse can only be programmed in the wafer state due to its stylized method, and the laser fuse cannot be used in the poor relief during high-speed testing after packaging or in the test circuit mounted on the wafer. Built-in self-repair (Built_m Self Repair) and other processes. Therefore, even in a system using a laser fuse, it is possible to carry an electrically programmable permanent recording, in a system composed of a plurality of wafers, although a separate EEPROM wafer. There is a variety of information stored in the system, but the system is integrated into two solids = the S〇C used (SystemonC· = held in the interior. However, the floating gate stores the charge, when the memory is combined with the memory. It is necessary to add a mask or a process, so the cost will increase. &lt; π is started by the injury information of the above-mentioned type of memory, and the information stored in the CMOS system is not required by the CMOS system. The standard body, this place needs to be able to take the _ (10) memory information used in the (four) memory and in the irreversible changes in the characteristics of the component, in the Hai wheel, the component characteristics to electricity: the converter is always called the electrical fuse. In addition, it is a configuration example of an electric fuse. It is composed of a metal when a large current flows through a wiring that is intended to make the electric power "higher (4) i). ^ kind of change in resistance value with 1291177, 16392pif.doc ===: This type of gate oxide film is a type of circuit that is used for components such as circuits. Since there is no need for special addition ΐ = then: It is suitable for a wide range of CM〇s products (for example, see 曰: Specialized in 2G_12699 and Japanese paste open fine. Then 4). = a type of damage caused by the destruction of a physical or composed structure = the electrical phenomenon used as a stylized mechanism = a probability process. After the stress is applied, if there is also a formula: =: then there will be a bad bit in the limited stylized time that is not fully chopped and stylized, but in the process; ώ ( 感 感 感 感 感 感 感 感 感 四 四 四 四 四 四 四 四 四 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( If they are inconsistent, the kernel=reprograms the stylized bad bits. The characteristics of the components after the patterning are widely distributed. X, if you consider the change in the year of the inch, the job security (10) can be checked for sufficient room; ^兀. However, in the verification up to the present, it is not _ marginal sales due to 盥 ===: wide'. [Reading as a bad bit" will cause the city 1291177 16392pif.doc. [Invention] According to one form of the present invention, a semiconductor integrated circuit device is provided, which is provided with an element which is electrically characterized by a component. The information has been irreversibly changed to make the information stylized; the state detecting circuit is configured to distinguish between the state of the irreversible memory element and the unchanging state to achieve the detection function; and the control device It is constructed in such a way that the detection capability of the state detecting circuit can be changed. Further, according to one form of the present invention, there is provided a stylized method of a semiconductor integrated circuit device which, in a normal readout operation, distinguishes a state of an irreversibly changed memory element from an unaltered state to achieve In the stylized method of the semiconductor integrated circuit device that has read the $ information from the memory element, it has a stylization step, which is electrically irreversibly changed by the element characteristics, so that the information is in the memory element. a stylized 丄 readout step in which the detection state of the memory element that has been irreversibly changed, the detection capability of the state is lower than the normal read operation, and the detection of the monthly b-force B The difference between the evil phases is 'to achieve the detection function, the queen memory element reads the information; the output step compares the programmed information in the memory element with the information read from the memory element to output a kind of Consistent and inconsistent comparison results; specific steps that cause the comparison surrogate to be uniquely identified as bad bits; and to perform a step, the specific defect The above and other objects, features and advantages of the present invention will become more apparent in the light of the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Doc is as follows: [Embodiment] Data = real =, when the stylized electrical reliance is indicated, the data corresponding to the electricity is used instead of + Shishan "0TP &quot; the time after the stylization in the body感 感 — — 次 次 次 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 次 次 次 次 次 次 次 次 次 次 次 次Or, Γ, .^二=^2考_目 comparison, when the trusted 妒 妒 曰 曰 丨 丨 丨 、 、 、 、 、 、 、 、 、 、 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电The semaphore of the 'Τ' data seen by the sensing port can be changed. SDTW ^ The development time of the private pressure (SignalDevelopmentTime·hour) m voltage (vref) is controlled by one or both of them, verifying Bessie The margin of sensing becomes stricter. JZJL 〇耠+st, consistent/not-induced (Pass/Fa The result of il) shows the 1-bit part used. In the 'semiconductor integrated circuit device, by using a = road, the electric potential used for re-staging the bad bit S can be Efficient verification, consistency/inconsistency determination, and a series of actions such as re-king, etc., etc., the verification of the above, the determination of the consistency/inconsistency, the re-program, and the series of operations are performed efficiently. The semiconductor integrated circuit I2911737pifdoc device and its stylized method are described in detail in Fig. 4. The system shows that the semiconductor integrated circuit device in the present invention has the OTP memory and the 〇τρ memory. The stylized and measured action related peripheral circuits are extracted after the block diagram. The circuit comprises: a memory cell array u, a control circuit 12, a logic circuit 13 a vein generating private path 14, a DC control circuit 15, a sense amplifier control circuit 16, a leaf counter 17 and a multiplexer i8, and the like. The structure of the 5th-small body early-arc array 11 is formed by stacking a plurality of (n+1-segment) memory blocks 11 〇 ··· 2 . The respective memory blocks 110··: U_n are electrically irreversibly changed by 70 characteristics and constitute the following elements in a plurality of k-direction sub-columns: memory units 21-0, . . . , 21_η 'which has an electrical fuse for information that has been programmed with memory elements; and sense amplifiers 2(4), ..., 20-η, which cause irreversible changes to the bar and the unchanging (four) market and operation A state detection circuit for detection. The control circuit 12 described above operates as a circuit for sensing the sense amplifiers 2Q_n (i.e., 'sufficiently detecting the monthly power of the programmed bits), the control circuit 12 The control blocks 12 corresponding to the memory blocks 11-G, ..., u_n described above are composed of winter and HQ. The control blocks 12_〇, ..., 12_n are provided with: a flip-flop (4) 22 0...22η' corresponding to each segment of each memory block m, ιι_η to output the weight of each memory cell, ..., 21_n Signal DCP; forward and reverse (four) plus, ..., 23_n, the output of each induction 10 1291177 】 639 plus ((1 〇. Large 20-0, ···, 2〇·η enable (enable) Signal SAE; reference voltage generating circuit (VREF Gen·) 24-0, ..., 24-n, which supplies a reference voltage VREF as a reference voltage to each of the sense amplifiers 2〇_〇, ..., 2〇_n And the delay circuits 25-0, ..., 25-n. The above-mentioned logic circuit (interface logic circuit) 13 externally inputs various kinds of command signals (c〇mmand Signals), which are rotated by the logic circuit 13. The signal SENSE for sensing the operation instruction is supplied to the clock generation circuit 14 and the DC DC control circuit 15. Further, the signal VERIFY for the verification operation instruction outputted from the logic circuit 13 is supplied to the multiplexers 18, 19. The clock signal CLK generated in the generating circuit 14 is supplied to the DC control circuit 15's sense amplifier control circuit 16 and the counter 17. The signal DCEN outputted by the DC control circuit 15 is supplied to the data input terminal 正 of the flip-flop 22_〇 in the control block 12_0, and the clock signal DCCLK is supplied to each of the control blocks 12-0, . . . , ι2_η The clock input terminal CK of the positive and negative inverters 22-0, ..., 22_n is supplied to the positive and negative crying parameters 1 of the next segment by the signal DC [〇] outputted from the output terminal Q of the above-mentioned flip-flop Data input terminal D. Similarly, the signals DC(1) to DC (n_υ) outputted from the output terminal Q of the flip-flop are sequentially supplied to the data input terminal D of the flip-flops 22-2 to 22-n of the next segment. Then, The output signal DCD〇NE of the segment flip-flop 22-n is supplied to the DC control electric counter 17 and is activated in operation by the enable terminal EN receiving a k-number SDTGO outputted by the DC control circuit ,, the counter I? The output signal SAGO is supplied to the sense amplifier control circuit 16. 1291177 .16392pif.doc The signal output from the sense amplifier control circuit 16 is supplied to the data input terminal d of the flip-flop 23-〇 in the control block 12-0. = signal SACLK is supplied to each control block 12_〇, ..., i2_n flip-flop 23-0, respectively Pulse input terminal CK. The signal outputted from the output terminal Q of the flip-flop is supplied to the flip-flop completion and data input terminal D of the next segment. Similarly, the signals output by the flip-flop terminal Q are sequentially supplied. The data input terminal D of the flip-flops 23_2 to &amp; of the next stage is supplied to the logic circuit 13 by the output signal SADONE of the flip-flop 23·n of the last stage. The multiplexer 18 described above reacts to the signal VERIFY outputted by the logic circuit 13 and selects the signal TSDTN [3-〇] or TSDTV [3_〇], where one of the ##〇80丁[3-0] supplies Up to the initial setting terminal INI of the counter 17. The multiplexer 19 described above reacts to the signal VERIFY and selects the signal TVREFN [3-0] or TVREFV [3-0], wherein one of the signals DVREF [3-0] is supplied to each control block 12_〇, ... The reference voltage generating circuits 24-0 to 24-n in 12_n. The signals dc[〇], ..., DC[n] outputted from the data output terminals D of the flip-flops 22-0, ..., 22-n in the respective control blocks 12-0, ..., 12-n are respectively supplied to Among the memory blocks 11-0, ..., ll-n of the corresponding segments, a reset signal DCp is used as the memory cells 21-0, ..., 21_n. Further, the signals SAE[0], ..., SAE [n] output from the data output terminals D of the flip-flops 23-0, ..., 23-n are respectively passed through the delay circuits 25-0, ..., 25 -n is supplied to the memory blocks 11-0, ..., ll-n of the corresponding segments as the enable signals SAEn of the sense amplifiers 20-0, . . . , 20-η. Also, by 12 1291177 .16392pif.doc ΐ, 23: 〇, ..., 23·η data wheel output D output signal ..., S to the corresponding reference voltage production. 24 η Γ = action control signal V_called..., VREFG〇[n]=pressure amplifier VREF#仏i % _ , reference electric knife 刎彳~(7) to the corresponding segment of the memory block lU〇, &amp; sense amplifier 2 〇_〇, ., 2〇_n. ..., Figure 2 is a picture! The memory block in the circuit shown is called the configuration example of =:. Figure 2 shows an example of the formation of the sensed :) = connection line. In the various positions of the job, there is no comparison section (Bai Didi, ^ Mao Lu Zhongxun and the two-way electricity #性=中的的化1〒 Take the round out - kind one, compare the result; the bad detection part (bad detection circuit), whether there is irreversible characteristic change or characteristic (4) individual special limitation; multiple flip-flops, which will sense, and shell; :: Sending to the outside or transferring the stylized data from the outside and adding the secret storage, the flip-flop and the logic circuit for the control are controlled. The memory block 11·1 is input to the instruction in the logic circuit 13 To control. The circuit (memory block) in Figure 2 overlaps in multiple stages, and the output terminals SO, P〇 of the kth segment are respectively connected to the input terminals si, pl' of the first correction segment to form Figure 1. The memory cell array 11 is shown. Here, the signals supplied to the initial input terminal SI, the PI protocol, and the output terminals s0, 13 c S ) 1291177 , 16392pif.doc P0 of the previous segment are provided by the signal of FIG. 1 The logic circuit 13 supplies and the plurality of segments are collectively controlled. The stylized circuit of the first 1-bit portion of the memory block Π-i has: electrical fuse 31_0, MOS transistor 32_〇, 33_〇, sense amplification, device (S/A) 34- 0, reverse gate 35-0, 36-0, 37-0, 38_〇, Xenopus, positive, reverse 40-0, 41-0 and two gates 42-0, 43-0. The voltage VBP is applied to one of the electrical fuses 31_〇, and the other φ electrodes are connected to one end of the current path of the M〇S transistor 32-0. The other end of the current path of the MOS transistor 32-0 is connected to the input of the sense amplification crying (S/A) and is simultaneously connected to one end of the current path of the M 〇s transistor 33_〇. A voltage * VTB is applied to the gate of the MOS transistor 32-0. The other end of the current path of the MOS transistor 33-0 is connected to the ground point GND, and the gate is connected to the output terminal of the AND gate 43_〇 to supply a programmed signal PRG [0]. The output signal SAt [〇] of the above-mentioned sensed amplification state 34-0 is supplied to one input terminal of the inverse gate 35-0, and the inverted signal SAe [〇] is supplied to the first input terminal of the inverse gate 36-0. . The signal SALD is supplied to the other input of the opposite. The signal VERIFY is supplied to the second input terminal of the anti-gate 36_〇, and the output signal of the flip-flop 40-0 is supplied to the third input terminal. One of the inputs of the anti-gate 37-0 is connected to the wheel-in terminal si, and the other input is supplied with the shift signal SHIFT. The output signals of the above-mentioned respective gates 35_0, 36-0, 37_〇 are respectively supplied to the gate 38-0, and the output signal of the gate 38-0 is supplied to the input terminal D of the flip-flop. The clock input terminal CK of the flip-flop 4 (H) is supplied

12911H A clock signal FDCLK, which is supplied from the output terminal Q to the output signal so [〇] (corresponding to the input signal SI D of the sub-stage)) to the inverse of the sub-segment 37-1 and simultaneously It is supplied to one of the inputs of the anti-gate 39_〇.

The input terminal PI is connected to the data input terminal D of the flip-flop 41_0, and the signal FPCLK is supplied to the clock input terminal CK. The signal PM[0] outputted from the data input terminal Q of the flip-flop 41_〇 is supplied to the ith input terminal of the AND gate 43_〇, and at the same time, it is supplied to the other input of the reverse gate 39_Q. end. The signal FPCLK is supplied to the second input terminal of the idle 43-0, and the output signal PM [1] of the secondary flip-flop 4M is supplied to the third input terminal. The output signal of the gate 39-0 is supplied to one of the inputs of the gate 42_〇. The input terminal P! is connected to the other input terminal of the gate 42_〇, and the output (4) is supplied to the data wheel terminal d of the secondary-stage flip-flop 4M and the towel-input terminal of the gate 42 1 . The stylized circuit of the 1-bit portion of the segment as the output signal η of the bit is also the same as the initial segment. The transistor is, for example, A1, the sense amplifier (Qing 4·1 'reverse gate 35_卜纠' 37_卜38_Bu, positive and negative 40-1, 41-1 and two and illusion", a". The m-segment (final segment) of the 丨 bit part of the stylized circuit Composition also: with f. Electrically soluble wire such as, M〇S transistor 32-m '33-m 'sensing amplification (S/A) 34-m 'reverse gate 35_m, 3", 3ή": 39 , "Flip-flops and two and 42-m, 43_m. The forward side of the stylized circuit has a flip-flop 45 on the output side. And the output signal of the 1291177 16392pif.doc 42-m is supplied to the front and back. The value of 45, LK is supplied to the clock input terminal CK, (4) The output end of the material (4) is output (4) The PM [m+1] is inverted to be supplied to the 3rd input of the center of the heart. The round-out end p〇 connected to the wheel-out end of the gate 42-m is connected to the output terminal q of the positive U 40-0 S〇 the wheel end of the outer wheel. N Here, in the operation of the clock signal FDCLK be connected in series

22: ^ 减 及 崎 崎 资料 资料 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 ,image 3. A circuit diagram of a specific configuration of the 〇τρ memory cell and the sense amplifier 34 shown in Figs. 1 and 2 is shown. Here, the 纟ρ channel type MOS transistor is cut into the gate oxide film to destroy the electrical type of ~31_m. The memory unit 21 is constructed by the m〇s transistor erase and pass type MOS transistors mN0, MN1 (corresponding to the M〇s transistors 32-0 to 32-m and 33_〇 to 33_m of Fig. 2). The voltage VBP is applied to the source of the MOS transistor, the back is idle, and the interpole is connected to the drain of the M〇s transistor (node N1). The voltage VBT is applied to the idle pole of the M〇s transistor MN〇, and the source is connected to the MOS transistor face! Bungee (node N〇). Signal is supplied to the MOS transistor face! The idle pole, the source is connected to the grounding point. The MOSj crystal should be controlled to a proper level by the idle polarity VBT to limit the voltage of the node N〇 to "VBT-Vth" (the threshold of the MOS electric enamel surface, so as to prevent high voltage _ In the case of the formula = 16 1291177 16392pif.doc VBP) is applied to the transistor to which the node NO is connected. The sense amplifier 34 is a type of P-channel MOS transistor MPi to MP5 and an f-channel type M〇S transistor MN2~ The differential type amplification of the letter jin is used as a reference voltage, and the voltage of the node N0 of the memory unit 21 is compared with the voltage of the reference voltage 乂 且, and amplified to output a differential amplified signal transistor. The drain of MN2 is connected to node N〇, the source is connected to ground point GND. The signal DCp is supplied to the gate. The source of the transistor is connected to the power supply VDD. The signal SAEn is supplied to the gate. Hall transistors MP2, MP3 The source is connected to the M〇s transistor, and the gate of the transistor MP2 is connected to the node N. The reference ink vref is applied to the gate of the MOS transistor MP3. The running poles are connected to the sources of MOS transistors MP4 and Mp5 respectively. Each M〇s transistor MP4 The drain of the MOS transistor MN3, _4 and the section between the source are connected between the drain of the MP5 and the ground GND. The gate of the transistor MP4 and the surface 3 is connected to the M〇s transistor Mp5, read # The common connection point of the drain, the turn-off signal SAt is rotated by the common connection point of the drain. The gates of the MOS transistors MP5 and MN4 are connected to the common connection point of the drain of the M〇s transistors MP4 and MN3, and the output signal is SAe is output by the common junction point. Moreover, the drain of MOS transistor MP5 is connected to the connection point of MOS transistor MP2 and MP4, and the source is connected to ground GND. The drain of transistor MN6 is connected to M〇s Gate of crystal MN3, source: Connected to ground GNDMOS transistor _7 the drain is connected to M〇s 17 1291177 16392pif.doc The gate of transistor MN4, the source is connected to the ground point gnd. μ〇§ transistor The drain of MN8 is connected to the connection point of the M〇s transistor Mp3 and Na. The source is connected to the ground point GND. The signal SAEn is supplied to the gates of the M〇s transistors MN 5 to MN 8 to make these M 〇s The operation of the crystal is controlled. Also, the circuit for controlling the signal PRGp or the output signal theory, the power for reading Although it exists, it is omitted here. In addition, when the signals PRGp and DCP are not described, the default value is the ground point level, and the ^SAEN is not present (default) is the voltage VDD level. In addition, the manufacturing process used here can be used in the standard CM〇s process, but the M〇s day and day limbs of the gate oxide film having two or more types of thickness can be used. The Mеs thin idle oxide film where the electrolytic solution is located, in addition to the M0S transistor; there is a thick = polar oxide film. In the above configuration, when the electrical fuse Mp is programmed, that is, when the MOS electric solar cell, the solar cell, the MPQ_polar oxide film is destroyed (four) Yangbu, the voltages γ and ΒΡ are raised to a very high level. When the signal rises to the level of the power supply voltage VDD, the M?s transistor MN1 is turned on. Therefore, nodes NO and N1 fall to the GND level. The high voltage VBp is applied to the gate oxide film of the MOS transistor MP0, and the destruction occurs, so that the electro-crystal 脰 '通11海' can be considered as a breakdown caused by the current concentrated into the narrow fracture point after the destruction. The conductivity of the lower resistance in Joule heat is formed in an irreversible manner. ..., 18 1291177 .16392pif.doc • When reading the data of the above-mentioned electric fuse MP〇, make the voltage VBp into

For the level of the power supply voltage VDD, in order to prevent the threshold value of the voltage level of the node N〇 from decreasing, the voltage VBT must rise from the VDD level to a high level above the threshold voltage. Then, the signal DCP rises to VDD "level to turn on the M〇S transistor ^2, and the nodes N0, N1 fall to the gnd level. After a certain time, the signal DCp falls to the GND level, and the M〇s transistor MN2 returns. When the electric wire Mp is programmed, • When the resistance value becomes low, the node N0 is charged, causing the potential to rise with time. In this regard, the electric snagging MP0 is not stylized. When the leakage current charges the node NO, the node N〇 is almost guaranteed. After the SDT, the reference tevREF becomes the intermediate potential between the (four) fresh and the ?? if the signal SAEn falls from the VDD level to the GND position. Quasi, then feels to cry..." The position is dry and keeps. As a result, Qiu points ^ 准 准 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The reference circuit of the circuit shown in the electric waste production ~ specific structure of the circuit diagram. The reference 1 1 MOS capacitor charge is shared by the 1 circuit 24" because it is converted into the corresponding analog power. ^ This valve (4) Quasi-electric dust VREF. 兀 The digital value of the 颂 indicates the 16-bit basis

That is, the reference plane generating circuit is provided with: Pif type U 19 1291172 · Valley 51, inverter 52, and gate 53 to 56, P channel type MOS transistor

MP6 to MP9'N channel type MOS transistors MN9 to MN13 and M〇S capacitors C1 to C4. One of the electrodes in the MOS valley 51 is connected to the power supply VDD, and the other electrode is connected to the output of the reference VREF output (four). The output terminals for the output of the reference voltage VREF are respectively connected to the terminals of the MOS private crystals MN9 to MN13. The source of the 8-electrode MN9 is connected to the ground GND, and the gate is connected to the output of the inverter 52: 乜唬VREFGO is supplied to the input of the inverter 52. The output terminals of the M〇s transistors MN10 to MN13 connected to the M〇s capacitors C1 to C4, respectively, and the outputs of the gates 53 to 56 are connected to the gate. Each m〇s capacitor Cl C4 has another electrode connected to the grounding point transistor =6 The source of MP9 is connected to the power supply, VDD, and the drain is connected to one of the electrodes of each of the 私s private valleys ci~C4. The signal VREFG is supplied to one input terminal of each of the gates 53 to 56, and the digital signals dvref (9) to [3] are respectively supplied to the other input terminal. In the configuration, the information on the memory element (the information of the OTP memory d is performed in the manner shown in the flow diagram of Fig. 5. The first political power is electrically irreversibly changed by the metaphysical material, so that the information It is stylized in the 圮fe condition (step υ. Secondly, the state of the detection capability when the irreversible renewed action is made is distinguished for detection, 2) The state of the changed memory element is detected at a lower level than usual. The ability to read the information with the unaltered and then read by the memory element (step 20 1291177, 16392pif.doc;,;;, after the programmed information in the device and read from the memory element The information is compared to output-species-induced/not-induced comparison results (step 3). 1 The results of the abundance comparison are not—the bits of the _-specifically become bad bits: the information of the two μ-based bad bits The memory element is ordered and re-granulated (step 5). According to the above-mentioned two stylized method, switching the circuit design (margin) usually uses 眭, 晋^# τ to detect stylization, JU, / Bits with marginal characteristics, re-borrow = for relief, __ improved to achieve The high yield and the high-order map are ί2 = 2, =:, and the circuit Lif circuit shown in Fig. 6 to Fig. 9 constitutes the related action. Stacked in 4 segments (four)) 2 memory block secret... 'h (VERIFY=L) used for the timing diagram. That is, the display is not normal, the right input is externally input by a sense of eight circuits) 13 can be issued at any time, the internal nickname Logic circuit (interface logic high (H), level, if the sensing action is on = male first, the signal SENSE becomes, will act. Also, by the signal SEN^, the ancient clock generation circuit Η路15 Action: The DC control circuit generates a signal DCCLK according to the threshold of the clock generation circuit. Each of the 14 clock signals CLK block is reset (reset) and the other side is on the other hand. Reset the memory side N1. If all the segments have been reset to the node spoon of the tortoise '丨谷丝ΜΡ0 (DCDONE II H), then 21 1291177, 16392pif.doc =^ circuit i 5 stops the signal At the output of DCCLK, the signal sdt(8) becomes the "level", and the counter 17 becomes the enable state and starts the counting operation of the number CLK. The counter 17 is Clock signal: When the multiplexer 18 is applied to the initial setting terminal, the initial value is small. If the count value is 〇, the output is one, high, and the level _ sag 〇 normally operates. Since VERIFY=0 ("Low, bit ^. multiplexer 18 selects the value of TSDTN (4), becomes the STD corresponding to ^. The sense amplification control circuit 16 receives the signal sa(8) level and makes ❹mA| i can make money SAEN wire high level: the clock signal CLK produces a kind of signal SACLK. The signal saclk = mother-cycle is activated in the memory block segment and the reference voltage ¥ foot is generated and the ❹ Μ is activated. In each control block ^, ..., in, the signal VREFG (^ becomes a high-quality, generating circuit outline, ..., ... to generate the reference voltage = base = please In the case of the IFY=G, the multiplexed $i TVR is called by the reference voltage generating circuit 24 of each segment. == Raw-heterogeneous (4) charge sharing of the signal TVREFN(4): Waiting for the reference voltage to avoid F I; After the delay of the two digits, the signal sae [n] is flash locked by the high level. The paste (4) pressure value is sensed and VER wins, and the order of other signals is not changed. However, The initial surface area of n π is tsdtv (4), base 22 1291177 16392pif.doc The quasi-voltage generating circuits 24-0, ···, 24-n generate a reference voltage VREF of the level determined by the signal DVREFV [3-0] Therefore, if TSDTN &gt; TSDTV and TVREFN &lt; TVREFV are set, the SDT and the reference voltage VREF at the time of verification can be strictly set, and the sensing margin of the data can be set. Among the sense amplifiers 34-0 to 34-m shown in the sense, each of the signals when the memory data of the lock-up electrical 纟谷丝 31-0 31 31-m is read out to the outside Timing diagram. First, if the input clock signal FDCLK causes the signal SALD=H, the signal SHIFTS, and the signal VERIFY to be L, the output of the sense amplifiers 34-0, . . . , 34_m is loaded (i〇aded) to the fuse. Data temporary state (positive and negative device 40_〇,···, 4〇-m). Then, if the input clock signal fdclk makes the signal SALD=L, the signal smFT=H, the signal ERIFY L can be output SO Serially read the data. In order to program in the electrical fuse 31_〇~31-m, as shown in the sequence diagram, as shown in the timing diagram, the clock 贱FDCLK will be input by the input terminal SI. The stylized data should be input to the material data register in sequence (pros and cons. 〇,, 抓, to make SALI> L, SHIFMi, what should be. Then, as shown in Figure 9 _ riding * _ fine Materialization action. Here, 1" is set to the dissolution data holder of the bit i, and the position of the king other than = is set to, 〇,,, and thus becomes S, s〇[l]爿,S〇[2-mH)〇^=^ At the low level, all and the gates are ~42_m, the Γ has been evaluated, PI [2], ..., PIM is due, low, Level, the input terminal PI is set to, low, bit The original clock signal &lt; S ) 23 1291177 163 ppif.doc fdclk is input during the crying 4]n~々 cycle, and the program control registers (positive and 7 4 -m) can be initialized, positive and negative. 4Ι·〇~仏(7) 沾私丄丄 ΡΜ[〇], .··, PM [m+l] all become, 〇,,. The electric screen VBT: ^ rises, the voltage VBP rises to the height of the stylization; the quasi-become becomes the "high" level, and the 砗骱 味 味 味 则 则 入 入 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ k k k k k If you enter, you can make Ί" == and call k, the state will be 2.::;; : LK only during the high level period, the stylized signal pR ^ two are quasi-programmed. Although 9 shows only 1 bit of stylized action, when stylizing multiple materials, 'only the bits in the dissolve data register have been set to be available in each pulse cap. The element is stylized. Even if the bit of the segment is controlled by the remaining 1-bit program, it can be stylized in the same way as other bits by the existence of the temporary storage (reverse $45). In the stylization of the data, since the output p〇 becomes, high, and bit two' can be programmed by the external end point to minimize the total programming time. If the fuse data register is all bits When the input terminal pi becomes a high level, the wheel end of the clock signal FpcLK is not entered. The voltage VBP is set to the potential at the time of sensing to sense the programmed data. If VERIFY=H during sensing, the stylized bits of the margin described above are sensed as "〇". Here, when the bit i becomes a stylized failure, then SAt [1b 0 (SAc [1 Bu 1]). Then, when VERIFY=H remains in the original state, if the clock signal fDCLK is input, since SI [η (s〇24 I2911?63Uc [0])=1, SAc [1] two, the corresponding fuse data $ a becomes 1 ' in the scratchpad. It is remembered that the bit k of "0" becomes SI [k] (SO [kl]&gt;=〇, SA, and the Hyun data buffer is set to, Q,, and again. (4) Good record e remembers" The bit k of 1" becomes SI [k]=l, SAc [k]=〇, still SI [k]=l, SAc Μ=0, and the corresponding wire data buffer is set to ^, That is, by loading the value of the sense amplifier and the data buffer register, the ship data register, , !, the data becomes the desired program = material 'only failed bit The element will be set to "1,". By the above method, if there is a bad 1-bit, even if the input port is set to a high level, the output terminal P〇 remains at a low level. High level, at this time, the output terminal Κ) Ϊ = FPCLK is not rounded when the high scale, f, 1 bit / hour, can determine the stylized consistency / no = again, in the event of a problem, if it is carried out The original stylized action program material (4) (4) can be used to verify the efficiency of the electric shattering wire, the determination of the Γ/Γΐ and the re-stylization. And the composition of the inconsistency, the irreversible change of the estranged component has been stylized. When it is detected by the IT test, the information is used for the information: 4 (Brit (4) Going down to verify the status. The job---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Rescue and two = current if the volume of the circuit is checking the efficiency - the second program rate, the coffee and the high inspection, in the description of the implementation form above, although by way of example, π kinds of idle oxide Material, which consists of a vi〇s η gate gate emulsion electrical fuse. For example, electrical melting, destructive electrical melting wire, to be smeared =:; r kinds of conductive film is destroyed for program -1de) (4) The conductive film dissolves 2 = 34 'In accordance with the appearance of the present invention, the verification power of the verification using the electric clock can be improved, and the detected method is further performed by the method Read, shoot high yield _ U shell semiconductor integrated circuit f device and its stylized method. 6 Although the present invention has been disclosed in the above preferred embodiments, it is not an invention, and any person skilled in the art can make some modifications and retouchings without departing from the spirit of the invention. The target area is defined in the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a semiconductor integrated circuit device in an embodiment of the present invention, which is a peripheral circuit in which an OTP memory and a process of sensing and sensing the 〇τρ memory have been performed. The block diagram after the extraction. Figure 2 is a detailed diagram of a memory block in the circuit shown in Figure 1 1291177 16392pif.doc. Fig. 3 is a circuit diagram showing a specific configuration of an OTP memory cell and a sense amplifier in Figs. 1 and 2. Fig. 4 is a circuit diagram showing a specific configuration of a reference voltage generating circuit of the circuit shown in Fig. 1. Fig. 5 is a flow chart showing the stylization method of the OTP memory in the embodiment of the present invention. Fig. 6 is a timing chart showing a normal sensing operation when the memory blocks are stacked in four stages in the circuit shown in Fig. 1. Fig. 7 is a timing chart showing signals when the memory data of the latched electrical fuse in the sense amplifier shown in Fig. 2 is read out to the outside. Fig. 8 is a timing chart showing signals in the case where the electric fuse shown in Fig. 2 is programmed. Fig. 9 is a timing chart showing the stylized operation in the semiconductor integrated circuit device shown in Figs. 1 to 4 . [Main component symbol description] 11 Memory cell array 12 Control circuit 13 Logic circuit 14 Clock generation circuit 15 DC control circuit 16 Sense amplifier control circuit 17 Counter 18, 19 Multiplexer 27 1291177 16392pif.doc

11-0,···, 11 -n memory block 12-0, .··, 12_n control block 20-0, ···, 20_n sense amplifier 21-0 &gt; ..., 21-n memory Body unit 22-0, ···, 22-n flip-flop 23-0, ···, 23-n flip-flop 24-0, ···, 24-n reference voltage generating circuit 25-0 &gt; ... &gt; 25-n delay circuit 31-0 &gt; ..., 31-m electrical fuse 32-0 &gt; ..., 32-m MOS transistor 33-0, ···, 33 -m MOS transistor 34-0, ···, 34-m sense amplifier 35-0 ^ ..., 39-m reverse gate 40_0, ···, 41-m flip-flop 42-0, · ··, 43_m and gate 51 P channel type MOS capacitor 52 inverter 53 to 56 and gate 0 to MN13 N channel type MOS transistor ΜΡ0 to MP9 P channel type MOS transistor C1 to C4 capacitor 28

Claims (1)

1291177 I6392pif.doc X. Patent Application Scope 1. A semiconductor integrated circuit device, including a device, which is programmed to change information by electrically irreversibly changing the characteristics of the device. A form of nuclear test circuit, which is constructed such that the U element that can be irreversibly changed can be distinguished from the unaltered state for detection, and the 包 包 包 , , , , , , , 状态 状态 状态 状态 状态 状态 状态The detection capability changes; the dissolve, the data temporary storage 'is used to store the data to be stylized in the memory element; the second compares the f road to compare the programmed data in the fuse data register And 比较 and the output read from the memory element by the state detecting circuit to output a kind of consistent/inconsistent comparison result, and the comparison result is not: the time-based bit smear-specific bad bit, The memory element is reprogrammed with information about a particular bad bit. The semiconductor integrated circuit device according to claim 1, wherein the state detecting circuit converts the resistance value of the memory element into a corresponding level, and compares the converted voltage with the reference voltage. The state of the memory element is taken out. The semiconductor integrated circuit device of claim 2, wherein the control circuit detects the state of the circuit by causing the reference voltage to occur. 4. The semi-conducting unit as described in claim 2, wherein the control circuit changes by the time during which the memory element 29 1291177 16392pif.doc is electrically or discharged to change the state detecting circuit. Test your ability. 5. The semiconductor integrated circuit device according to claim 1, wherein the control circuit is verified by the state detecting circuit to verify that the edge of the sensing is smaller than that during normal sensing. A semiconductor integrated circuit device comprising: a memory element having a plurality of memory blocks, each of the memory blocks φ blocks comprising memory elements, wherein the information is changed by electrically irreversibly changing the characteristics of the elements Stylized; and state detecting circuit, the frame is configured to measure irreversible changes of the memory element distinguishable from the unchanging state; Η double cell, different control block, respectively, one to one $ square, Each of the control blocks controls the read operation of the relative circuit, and changes the status check circuit to detect a defectively programmed bit; and &gt;&amp; 2 control circuit, A round of instructions to generate money to protect the operation of the control circuit. The memory of the semiconductor integrated body, the upper, and the middle of the memory block further includes: ^ into the memory element in the middle ...,; 曰存斋, its number I _ should be privateized beetle and state detection circuit in the rim ff; and stylized control temporary cries, _ turn out seven ^ stylized to control the data person - kind of on the t 4 Patent scope No. 7 where the fuse tastes the ancestor AA &lt;~ 卞 歧 歧 体 电路 电路 电路 暂 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 9. According to the sixth aspect of the patent application scope, wherein the recording element is provided with a circuit-mounted electric thick electric material, one of the electrodes is applied with a process A1, an electric fuse, and a crucible electric fuse. Also included: Column 5 transistor with current path, its end-to-end technology;:? The other electrode of the fuse; and the gate, the applied voltage, is used to batch the voltage of the other end of the current path, and the electric ground is used to control the other end of the current path of the Rashio L package. Another guard, hit to the grounding point; and the gate and the other electric wire. The privateized Mdx stylized the i body of the ninth application of the patent scope: = silk is - thin closed oxidized type of heart:; added to the back ^ the = back asks 'where the stylized voltage is applied to the channel M 〇s electricity day and day body is thick _ oxygen 11 view f day body and the second N set, material 6 half-shaped half-frequency circuit circuitized voltage, wire, one of the electrodes is applied to the crystal , with a - current path, the - terminal is connected to the 3 secrets of the other end connected to the grounding point, and the formula 其 'the application of - (four) signal 'for the electric sleek, silk ride 12 · The semiconductor integrated circuit package 31 1291177 16392pif.doc as described in the patent application scope n, has the electrical, dermatoglyphic _ crystal, straight and has a (four) polar oxidation type P channel MOS electrical channel (10) The transistor is a resistance value of the semiconductor integrated circuit package of the thick _^ Cong transistor and the second N, and is replaced by a sense amplifier 'which makes the memory cell voltage and the reference voltage = the bit that should be The quasi-voltage 'and the variable axis ^ two = volume body circuit mounted transistor and the » thin s electricity; find the connection point of the 1M〇s private day The voltage is supplied to the 筮, the wheel input end; and the second input end, wherein the reference lion drawn by the phoenix gives the butterfly 2 the wheel of the circuit and compares the converted voltage with the reference voltage, and the amplified voltage difference is rotated. The amplified differential amplified signal. The semiconductor integrated circuit device of claim 6, wherein each control block in the first control circuit comprises: a first flip-flop that outputs a reset signal for use from a corresponding memory An electrical fuse of the block, reading data; a second flip-flop that outputs an enable L number of the sense amplifier, a delay circuit that delays the output signal of the second flip-flop and provides a delayed signal to The sense amplifier; and a reference voltage generating circuit 'which is controlled by the output signal of the second flip-flop to provide a quasi-voltage to the sense amplifier. 〃 16 · · · · · · 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 17. As claimed in claim 15: a: wherein the second control circuit further comprises: a semiconductor integrated circuit circuit, receiving an instruction; and a π pulse generating circuit 'the pair responding to the The output signal for sensing the action generates a clock controller that rotates the first controller, and according to the indication, the counter responds to the third pulse control signal, and the clock signal supplied by the path enters the ^^ 'The second controller at that time, based on the counter's signal _ signal' to provide an initial value to: the verification action is rotated to provide the benchmark money to generate the base money pressure _ digital signal 18 · a semiconductor In the read operation of the integrated circuit, by means of an irreversible signal that is distinguishable from the unaltered / memory element in the normally changed memory element, the stylized method will be programmed to store the mm. The wire data register; 33 1291177 16392pif.doc The message is changed to the power; the component characteristics are reversibly changed, and the ability to measure changes in the memory element is lower than the normal readout action, by detecting the non-memory component Recalling 70 pieces Electrical irreversible change state 'from the readout ratio of the wire!! The information in the bucket register and the comparison result from the memory component to indicate - caused / not - good; good bit; / / ratio The secret indicator indicates that the bit is not specified, and the information of the bad bit is not specified, and the memory element is cut and the memory node of the memory component is reset. The bite of the edge of the two sides;:::= The component readout information is the clip of the checkout tool and the state detection circuit, and the test is performed by the tester (10) to change the state detection circuit. · In the semiconductor dry memory described in the scope of the patent application, when the current is read by the memory device, the current is charged or discharged, so that the capacitor is charged or discharged, so that the detection of the circuit is detected. The ability to change 23 - a semiconductor integrated circuit device, comprising: a memory element, which is electrically irreversibly made to change the information to be programmed; 卞% electrical 乂 乂 state detection, its surface The shape of the 魏 变 变 变 变 变 变 变 可 可 可The state of pure Xianjin, &quot; control circuit, its composition can make the state check double and change, the detection force of the ridge occurs, the control circuit is more strict with the sound in the state detection circuit than in the normal sensing, In order to check the date: the side is a bad bit. 35 1291177 t 1639_2pif.doc VII. Designated representative map: (1) The representative representative of the case is: Figure (1). (b) The symbol of the symbol of the representative figure is briefly described: 11 memory cell array 12 control circuit 13 logic circuit 14 clock generation circuit 15 DC control circuit 16 sense amplifier control circuit 17 counter 18, 19 multiplexer 11-0 ..., ll-η memory block 12- 0, ..., 12-n control block 20- 0, ..., 20-n sense amplifier 21- 0, ..., 21-n memory early 22- 0, ..., 22-n flip-flop 23- 0, ..., 23-η flip-flop 24-0, ·.., 24-n reference voltage generating circuit 25- 0, ..., 25-η delay circuit VIII, if this case When there is a chemical formula, please reveal the chemical formula that best shows the characteristics of the invention: Ml