1291177 16392pif.doc 九、發明說明: 【發明所屬之技術領域】 本發明涉及一種半導體積體電路裝置及其程式化方 法’更洋細而δ,本發明涉及一種具備可程式化的不可逆 吕己憶元件(所谓OTP (One-Time Programmable)記憶體)之半 導體積體電路裝置及其記憶元件的資訊之程式化方法。 本發明是以先前200年4月7曰申請之曰本專利申請 案號No· 2004-113440為基準且主張其優先權之權益,其 整個内容加入本發明中作為參考。 【先前技術】 近年的半導體積體電路裝置中,即使電源下降但所記 憶的資訊亦不會消失之永久性〇TP記憶體成為不可欠缺 的元件。ΟΤΡ記憶體可廣泛地用在所謂dram或 之大容量的記憶體中的備用(redundance)用途,類比電路的 調諳(tunning)用途或暗鍵等的碼儲存用途以及製造過程的 經歷等之類的管理用的資訊記憶用之晶片辨認(ID)用 等。 、 例如,在記憶體的備用用途中,藉由雷射光的照射所 造成的燒斷現象以達成最便宜的永久性記憶體,則可使用 -種使用f雜絲$ RQM,其叫可制料儲存 訊。 貝 在上述的雷_絲RQM巾,f純殊的熔絲 置以及使用該裝置的燒斷過程,此時會產生所需的^ 本。又,雷射溶絲中由於其最小尺寸是由所使用的雷f 1291177 16392pif.doc 的波長所決定,則與其它電路部份之間的微細化的步調會 不相配合’且逐漸地使所佔有的面積的比例變大。而且, 雷射熔絲由於其程式化方法而只能在晶圓狀態下被程式 化,雷射熔絲不能使用在封裝後的高速測試時的不良救濟 中或晶片内所搭載的測試電路所進行的内建式自我修^ (Built_m Self Repair)等過程中。因此,即使是使用雷射熔 絲的系統中仍會有,,希期搭載著電性可程式化的永久性記 另—方面,在多個晶片所構成的系統中,雖然獨立的 EEPROM的晶片中可儲存著各種資訊,但使系統積化 二固=所用的 S〇C(SystemonC· =持在内部中。然而,浮動閘極中儲存著電荷之此種 ,以性記憶舰合絲時,有必要因•追加光罩 或製程,於是成本會上升。 < π早 由上述型式的記憶體的傷用資訊開始, 中所儲存的資訊由於連 ° CMOS制加a 人都不需要’則在標準的 體,,。此地需要該可搭_⑽記憶 下資訊二用的㈣Ί憶體且在元件特性不可逆地變化 又、亥輪件中,元件特性以電 : 化者總稱為電性熔絲。、的方式而被受 就作為電性熔絲的構成例 炫絲’其在由意圖使電《度變高之重反㈣i) 的配線中流過—種大的電流時可利用一^金屬所構成 ^種使電阻值變化用 1291177 ,16392pif.doc ===:電路等構成用之元件的絕 ^之此種閘極氧化膜破壞型反_由於不需特別的追加ΐ =則:適用於廣泛的CM〇s製品中(例如,請參閱曰: 專開2G_12699以及日本糊公開細.则4)。 =而造成物理的或組成的構造的破壞時的一種二= ,此’破壞現象作為程式化機構用的電性 =一種機率過程。施加應力後,若亦存在著已:式: =:則有限的程式化時間内亦會存在著未充份丄 切程式化未充份完成的不良位元,則在程 ;^生溶絲讀ώ資料(感測),對已程式化的資料 ί ㈣魏師响)輕成為有必 " ’、也末#疋—致(Pass)或不一致(Fail)。若不一致, 核=要對該程式化不良位元進行再程式化。 ,式化後的元件特性分佈著廣泛的偏差。X,若考慮 寸性时年變化,職保⑽充份的餘地錢可檢; ^兀。然而’直至目前為止的驗證中,由盥 ===:广’則不_邊 場銷售不良。讀為不良的位元’這樣會造成市 1291177 16392pif.doc 【發明内容】 依據本發明的一種形式而提供一種半導體積體電路裝 置,其具備·圮fe、元件,其藉由元件特性在電性上已不可 逆地被變化而使資訊被程式化;狀態檢測電路,其構成方 ^是可在已不可逆地的記憶元件的狀態和未變化的狀 恶之間進行區別以達成檢測作用;以及控制裝置,其構成 方式是可使該狀態檢測電路的檢測能力發生變化。 又,依據本發明的一種形式而提供一種半導體積體電 路裝置的程式化方法,其在通常的讀出動作中,使已不可 逆地變化的記憶元件的狀態可與未變化的狀態相區別以達 成檢測作用,在已由記憶元件讀$資訊之半導體積體電路 裝置的程式化方法中,其具備:程式化步驟,其藉由元件 特性在電性上已不可逆地被變化,使資訊在記憶元件中程 式化丄讀出步驟,其藉由使已不可逆地被變化的記憶元件 ,狀態在-種較通常的讀出動作時的檢測能力還低的檢測 月b力B守可與未1化的狀恶相區別’以達成檢測作用,蜂後 ^記憶元件讀出資訊;輸出步驟,其比較該記憶元件'中'已 程式化的資訊和由該記憶元件中已讀出的資訊,以輸出一 種一致和不一致的比較結果;特定步驟,其使該比較姓果 不—致時的位元個別地特定成不良位元;以及進行步^, 該已特定的不良位元的資訊,對該記憶元件進行再程 為讓本發明之上述和其他目的、特徵和優點能更 董,下文特舉較佳實施例,並配合所附圖式,作詳細說 1291177 ,16392pif.doc 明如下 【實施方式】 資料=實=,已程式化的電性賴對應的 表示時,就使用電對應的資料以 噔而+士山“之0TP "己體中程式化之後的驗 時Γ證感測— 次粗从a、t、自 7 口貝出動作(Normal Sense),則由於”1” 不良位’邊際的特性的位元亦可能被檢出成 讀出,,〇,,或,,Γ,。^二=^2考_目比較時,可 信妒帝 曰毛丨生烙、、、糸的谷置的充電或放電而產生 :即:吏藉产該參考電壓的變化,仍可使由感測 口口看到的’Τ’資料的信號量發生變化。 SDTW ^ 乜唬私壓的發展時間(SignalDevelopmentTime· 時”m電壓(vref)的一方或兩方受到控制,驗證 貝枓的感測邊際(margin)成為較嚴。 JZJL 〇 耠+s t,一致/不—致(Pass/Fail)的結果顯示用的1位元 部。又’半導體積體電路裝置中藉由設有一種= 路,因ί式化貧料相—致的不良位S再程式化所用的電 r 上可效率良好地進行驗證,一致/不一致之判定,再 王式化等一連串的動作。 化等'人,如上所述的驗證,一致/不一致之判定,再程式 、—連串的動作效率良好地進行所用的半導體積體電路 I2911737pifdoc 裝置和其程式化方法中,就圖4 詳細說明。 ^係身示本發_實卿式中的半導體積體電路裝 置二係#已將OTP記憶體以及與〇τρ記憶體的程式 化和怎測動作有關的周邊電路抽出後的方塊圖。該電路之 構成包含:記憶體單元陣列u,控制電路12,邏輯電路 13叶脈產生私路14,直流控制電路15,感測放大器控制 電路16,叶數器17以及多工器i8、等。 5亥疏體早兀陣列11的構成是以多段(n+1段)記憶體 方塊11 〇 ···二11,堆疊配置而成。各別的記憶體方塊 110 ··: U_n藉由70件特性在電性上不可逆地被改變而 以多個k向亚列之方式構成以下各元件:記憶體單元 21-0、···、21_η ’其具有資訊已程式化的記憶元件之電性 熔絲;以及感測放大器2㈣、…、20-η,其使已不可逆地 被變化的條_陳射與未變化的㈣墟別且操作 成檢測用的狀態檢測電路。 上述的控制電路12操作成一種可使感測放大器 …2Q_n的檢測能力(即’充份地檢測已程式化的位 元之月匕力)½生、:化用的電路,該控制電路12以上述各記 憶體方塊11-G、...、u_n所對應的控制方塊12冬…、HQ 來構成。控制方塊12_〇、...、12_n具備:正反器㈣ 22 0…22η’其對應於各記憶體方塊m 、ιι_η 的各段以輸出各記憶體單元抑、...、21_n的重 信號DCP;正反器㈣加、...、23_n,其輸出各感應放 10 1291177 】639加((1〇。 大為20-0、···、2〇·η的致能(enable)信號SAE ;基準電壓 產生電路(VREF Gen·) 24-0、…、24-n,其供給一種作為參 考電壓用的基準電壓VREF至各感應放大器2〇_〇、...、2〇_n 中;以及延遲電路25-0、…、25-n。 上述的邏輯電路(介面邏輯電路)13中由外部輸入各種 、 指令^號(c〇mmand Signals)。由該邏輯電路13所輪出的 感測動作指示用的信號SENSE供給至時脈產生電路14和 鲁 直流控制電路15中。又,由邏輯電路13所輸出之驗證動 作指示用的信號VERIFY供給至多工器18、19中。時脈 產生電路14中所產生的時脈信號CLK供給至直流控制電 路15 ’感測放大器控制電路16和計數器17中。 、 由直流控制電路15所輸出的信號DCEN供給至控制 方塊12_0中的正反器22_〇的資料輸入端〇,時脈^號 • DCCLK分別供給至各控制方塊12-0、···、ι2_η中的正反^ 器22-0、…、22_n的時脈輸入端CK。由上述正反器 的輸出端Q所輸出的信號DC [〇]供給至下一段的正反哭 參 Μ·1的資料輸入端D。同樣,由上述正反器 的輸出端Q所輸出的信號DC⑴〜DC (η_υ依序供給至 下一段的正反器22-2〜22-η的資料輸入端D。然後, 段的正反器22-n的輸出信號DCD〇NE供給至直流控制電 計數器17在致能端EN接收一種由直流控制電路Η 所輸出的k號SDTGO而在動作上受到控制,該計數器I? 的輸出信號SAGO供給至感測放大器控制電路16中。 1291177 .16392pif.doc 由感測放大器控制電路16所輸出的信號^ 至控制方塊12-0中的正反器23-〇的資料輸入端d = 信號SACLK分別供給至各控制方塊12_〇、...、i2_n 正反器23-0、的時脈輸入端CK。由該正反器 的輸出端Q所輸出的信號供給至下一段的正反器Μ工、 資料輸入端D。同樣,由上述正反器 端Q所輸出的信號依序供給至下一段的正反器23_2〜& 的資料輸入端D。然後,最後段的正反器23·η的輸出信^ SADONE供給至邏輯電路13。 上述之多工器18對該由邏輯電路13所輸出的信號 VERIFY起反應且選取信號TSDTN [3-〇]或TSDTV [3_〇], 其中一方的#號〇80丁 [3-0]供給至計數器17的初期設定 端INI。上述之多工器19對該信號VERIFY起反應且選取 信號TVREFN [3-0]或TVREFV [3-0],其中一方的信號 DVREF [3-0]分別供給至各控制方塊12_〇、…、12_n中的 基準電壓產生電路24-0〜24-n中。 由各控制方塊12-0、…、12-n中的正反器22-0、…、 22-n的資料輸出端D所輸出的信號dc[〇]、…、DC[n]分 別供給至相對應的段的記憶體方塊11-0、…、ll-η中,以 作為記憶體單元21-0、…、21_n的重置(reset)信號DCp。 又’由正反器23-0、·· ·、23-n的資料輸出端D所輸出的信 號SAE[0]、···、SAE [n]分別經由延遲電路25-0、…、25-n 供給至相對應的段的記憶體方塊11-0、…、ll-η中,以作 為感測放大器20-0、··.、20-η的致能信號SAEn。又,由 12 1291177 .16392pif.doc ίΐ,23:〇、…、23·η的資料輪出端D所輸出的信妒分 …、S至相對應的基準電壓產 .24 η Γ =動作控制信號v_叫...、VREFG〇[n]=以 壓VREF分別#仏i % _ 、基準電 刀刎彳〜⑺至相對應的段的記憶體方塊lU〇、 &中之感測放大器2〇_〇、 .、2〇_n中。 …、 圖2係圖!所示的電路中之記憶體方塊叫 =:的構成例。該圖2顯示—種使已感測的 :) =連接線所形成的例子。在各職丨位元部份的= 没有·比較部(比齡帝枚、^ 毛路中 訊和由二對電#性=中已程式化的資 1〒所靖出的育訊進行比較,以輪出—種一 二 、比較結果;不良檢測部(不良檢測電路),立 是否有不可逆的特性的變化或特性的㈣ 個別的特殊限定;多個正反器,其將感 、、貝;::卞送至外部或由外部轉送程式化資料且加 祕儲子乂,私式化控制用的正反器和邏輯電路。該記憶 脰方塊11·ι藉由輸入至邏輯電路13中的指令來控制。 圖2中所不的電路(記憶體方塊)以多段方式相重疊, 第k段的輸出端SO、P〇分別連接至第糾段的輸入端si、 pl’則可構成圖1中所示的記憶體單元陣列11。此處,供 給至初段輸人端SI、PI辦叙及由前段的輸出端s0、 13 c S ) 1291177 ,16392pif.doc P0所供給的信號是由圖1的邏輯電路13所供給,且多個 段共同受到控制。 記憶體方塊Π-i中的初段之1位元部份的程式化電路 具備:電性熔絲31_0,MOS電晶體32_〇,33_〇,感測放大 , 器(S/A)34-0,反及閘 35-0,36-0,37-0,38_〇,爪〇,正 , 反器40-0,41-0以及二個及閘42-0,43-0。 電壓VBP施加至電性熔絲31_〇中的一個電極,另一 φ 個電極連接至M〇S電晶體32-0的電流路徑的一端。該 M0S電晶體32-0的電流路徑的另一端連接至感測放大哭 (S/A)則的輸入端且同時連接至M〇s電晶體33_〇的電流 路徑的一端。該M0S電晶體32-0的閘極上施加一種電壓 * VTB。M0S電晶體33-0的電流路徑的另一端連接至接地 點GND,閘極連接至及閘43_〇的輸出端,以供給一種程 式化信號PRG [0]。 上述感測放大态34-0的輸出信號SAt [〇]供給至反及 閘35-0中的一個輸入端,其反相信號SAe [〇]供給至反及 閘36-0的第1輸入端。信號SALD供給至該反及問 的另一個輸入端。信號VERIFY供給至反及閘36_〇的第2 輸入端,正反器40-0的輸出信號供給至第3輸入端。反及 閘37-0中的一個輸入端連接至輪入端si,另一輸入端則被 供應以移位信號SHIFT。 上述各反及閘35_0,36-0,37_〇的輸出信號分別供給 至,及閘38-0,反及閘38-0的輸出信號供給至正反器.〇 的貝料輸入端D。該正反器4(H)的時脈輸入端CK被供給BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a stylized method thereof, which are more compact and δ. The present invention relates to a programmable irreversible Lv Yiyi. A semiconductor integrated circuit device of a component (such as an OTP (One-Time Programmable) memory) and a programmatic method of information of a memory element thereof. The present invention is based on the priority of the present patent application No. 2004-113440, the entire disclosure of which is hereby incorporated by reference. [Prior Art] In the semiconductor integrated circuit device of recent years, even if the power supply is lowered, the permanent information of the recorded information does not disappear, and the TP memory becomes an indispensable component. ΟΤΡMemory can be widely used in the so-called dram or large-capacity memory in the use of redundancy, analog circuits for tuning purposes or code storage applications such as dark keys, and the experience of manufacturing processes, etc. It is used for wafer identification (ID) for information memory for management. For example, in the standby use of the memory, the burnt phenomenon caused by the irradiation of the laser light is used to achieve the cheapest permanent memory, and the use of the f-wire Q RQM, which can be used as a material, can be used. Save the news. In the above-mentioned Ray-Ray RQM towel, the fuse of the special fuse and the burning process using the device, the required one is generated at this time. Moreover, since the minimum size of the laser-dissolved filament is determined by the wavelength of the lightning rod f 1291177 16392pif.doc used, the step of miniaturization with other circuit parts may not match, and gradually The proportion of the occupied area becomes larger. Moreover, the laser fuse can only be programmed in the wafer state due to its stylized method, and the laser fuse cannot be used in the poor relief during high-speed testing after packaging or in the test circuit mounted on the wafer. Built-in self-repair (Built_m Self Repair) and other processes. Therefore, even in a system using a laser fuse, it is possible to carry an electrically programmable permanent recording, in a system composed of a plurality of wafers, although a separate EEPROM wafer. There is a variety of information stored in the system, but the system is integrated into two solids = the S〇C used (SystemonC· = held in the interior. However, the floating gate stores the charge, when the memory is combined with the memory. It is necessary to add a mask or a process, so the cost will increase. < π is started by the injury information of the above-mentioned type of memory, and the information stored in the CMOS system is not required by the CMOS system. The standard body, this place needs to be able to take the _ (10) memory information used in the (four) memory and in the irreversible changes in the characteristics of the component, in the Hai wheel, the component characteristics to electricity: the converter is always called the electrical fuse. In addition, it is a configuration example of an electric fuse. It is composed of a metal when a large current flows through a wiring that is intended to make the electric power "higher (4) i). ^ kind of change in resistance value with 1291177, 16392pif.doc ===: This type of gate oxide film is a type of circuit that is used for components such as circuits. Since there is no need for special addition ΐ = then: It is suitable for a wide range of CM〇s products (for example, see 曰: Specialized in 2G_12699 and Japanese paste open fine. Then 4). = a type of damage caused by the destruction of a physical or composed structure = the electrical phenomenon used as a stylized mechanism = a probability process. After the stress is applied, if there is also a formula: =: then there will be a bad bit in the limited stylized time that is not fully chopped and stylized, but in the process; ώ ( 感 感 感 感 感 感 感 感 感 四 四 四 四 四 四 四 四 四 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( If they are inconsistent, the kernel=reprograms the stylized bad bits. The characteristics of the components after the patterning are widely distributed. X, if you consider the change in the year of the inch, the job security (10) can be checked for sufficient room; ^兀. However, in the verification up to the present, it is not _ marginal sales due to 盥 ===: wide'. [Reading as a bad bit" will cause the city 1291177 16392pif.doc. [Invention] According to one form of the present invention, a semiconductor integrated circuit device is provided, which is provided with an element which is electrically characterized by a component. The information has been irreversibly changed to make the information stylized; the state detecting circuit is configured to distinguish between the state of the irreversible memory element and the unchanging state to achieve the detection function; and the control device It is constructed in such a way that the detection capability of the state detecting circuit can be changed. Further, according to one form of the present invention, there is provided a stylized method of a semiconductor integrated circuit device which, in a normal readout operation, distinguishes a state of an irreversibly changed memory element from an unaltered state to achieve In the stylized method of the semiconductor integrated circuit device that has read the $ information from the memory element, it has a stylization step, which is electrically irreversibly changed by the element characteristics, so that the information is in the memory element. a stylized 丄 readout step in which the detection state of the memory element that has been irreversibly changed, the detection capability of the state is lower than the normal read operation, and the detection of the monthly b-force B The difference between the evil phases is 'to achieve the detection function, the queen memory element reads the information; the output step compares the programmed information in the memory element with the information read from the memory element to output a kind of Consistent and inconsistent comparison results; specific steps that cause the comparison surrogate to be uniquely identified as bad bits; and to perform a step, the specific defect The above and other objects, features and advantages of the present invention will become more apparent in the light of the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Doc is as follows: [Embodiment] Data = real =, when the stylized electrical reliance is indicated, the data corresponding to the electricity is used instead of + Shishan "0TP " the time after the stylization in the body感 感 — — 次 次 次 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 次 次 次 次 次 次 次 次 次 次 次 次Or, Γ, .^二=^2考_目 comparison, when the trusted 妒 妒 曰 曰 丨 丨 丨 、 、 、 、 、 、 、 、 、 、 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电 充电The semaphore of the 'Τ' data seen by the sensing port can be changed. SDTW ^ The development time of the private pressure (SignalDevelopmentTime·hour) m voltage (vref) is controlled by one or both of them, verifying Bessie The margin of sensing becomes stricter. JZJL 〇耠+st, consistent/not-induced (Pass/Fa The result of il) shows the 1-bit part used. In the 'semiconductor integrated circuit device, by using a = road, the electric potential used for re-staging the bad bit S can be Efficient verification, consistency/inconsistency determination, and a series of actions such as re-king, etc., etc., the verification of the above, the determination of the consistency/inconsistency, the re-program, and the series of operations are performed efficiently. The semiconductor integrated circuit I2911737pifdoc device and its stylized method are described in detail in Fig. 4. The system shows that the semiconductor integrated circuit device in the present invention has the OTP memory and the 〇τρ memory. The stylized and measured action related peripheral circuits are extracted after the block diagram. The circuit comprises: a memory cell array u, a control circuit 12, a logic circuit 13 a vein generating private path 14, a DC control circuit 15, a sense amplifier control circuit 16, a leaf counter 17 and a multiplexer i8, and the like. The structure of the 5th-small body early-arc array 11 is formed by stacking a plurality of (n+1-segment) memory blocks 11 〇 ··· 2 . The respective memory blocks 110··: U_n are electrically irreversibly changed by 70 characteristics and constitute the following elements in a plurality of k-direction sub-columns: memory units 21-0, . . . , 21_η 'which has an electrical fuse for information that has been programmed with memory elements; and sense amplifiers 2(4), ..., 20-η, which cause irreversible changes to the bar and the unchanging (four) market and operation A state detection circuit for detection. The control circuit 12 described above operates as a circuit for sensing the sense amplifiers 2Q_n (i.e., 'sufficiently detecting the monthly power of the programmed bits), the control circuit 12 The control blocks 12 corresponding to the memory blocks 11-G, ..., u_n described above are composed of winter and HQ. The control blocks 12_〇, ..., 12_n are provided with: a flip-flop (4) 22 0...22η' corresponding to each segment of each memory block m, ιι_η to output the weight of each memory cell, ..., 21_n Signal DCP; forward and reverse (four) plus, ..., 23_n, the output of each induction 10 1291177 】 639 plus ((1 〇. Large 20-0, ···, 2〇·η enable (enable) Signal SAE; reference voltage generating circuit (VREF Gen·) 24-0, ..., 24-n, which supplies a reference voltage VREF as a reference voltage to each of the sense amplifiers 2〇_〇, ..., 2〇_n And the delay circuits 25-0, ..., 25-n. The above-mentioned logic circuit (interface logic circuit) 13 externally inputs various kinds of command signals (c〇mmand Signals), which are rotated by the logic circuit 13. The signal SENSE for sensing the operation instruction is supplied to the clock generation circuit 14 and the DC DC control circuit 15. Further, the signal VERIFY for the verification operation instruction outputted from the logic circuit 13 is supplied to the multiplexers 18, 19. The clock signal CLK generated in the generating circuit 14 is supplied to the DC control circuit 15's sense amplifier control circuit 16 and the counter 17. The signal DCEN outputted by the DC control circuit 15 is supplied to the data input terminal 正 of the flip-flop 22_〇 in the control block 12_0, and the clock signal DCCLK is supplied to each of the control blocks 12-0, . . . , ι2_η The clock input terminal CK of the positive and negative inverters 22-0, ..., 22_n is supplied to the positive and negative crying parameters 1 of the next segment by the signal DC [〇] outputted from the output terminal Q of the above-mentioned flip-flop Data input terminal D. Similarly, the signals DC(1) to DC (n_υ) outputted from the output terminal Q of the flip-flop are sequentially supplied to the data input terminal D of the flip-flops 22-2 to 22-n of the next segment. Then, The output signal DCD〇NE of the segment flip-flop 22-n is supplied to the DC control electric counter 17 and is activated in operation by the enable terminal EN receiving a k-number SDTGO outputted by the DC control circuit ,, the counter I? The output signal SAGO is supplied to the sense amplifier control circuit 16. 1291177 .16392pif.doc The signal output from the sense amplifier control circuit 16 is supplied to the data input terminal d of the flip-flop 23-〇 in the control block 12-0. = signal SACLK is supplied to each control block 12_〇, ..., i2_n flip-flop 23-0, respectively Pulse input terminal CK. The signal outputted from the output terminal Q of the flip-flop is supplied to the flip-flop completion and data input terminal D of the next segment. Similarly, the signals output by the flip-flop terminal Q are sequentially supplied. The data input terminal D of the flip-flops 23_2 to & of the next stage is supplied to the logic circuit 13 by the output signal SADONE of the flip-flop 23·n of the last stage. The multiplexer 18 described above reacts to the signal VERIFY outputted by the logic circuit 13 and selects the signal TSDTN [3-〇] or TSDTV [3_〇], where one of the ##〇80丁[3-0] supplies Up to the initial setting terminal INI of the counter 17. The multiplexer 19 described above reacts to the signal VERIFY and selects the signal TVREFN [3-0] or TVREFV [3-0], wherein one of the signals DVREF [3-0] is supplied to each control block 12_〇, ... The reference voltage generating circuits 24-0 to 24-n in 12_n. The signals dc[〇], ..., DC[n] outputted from the data output terminals D of the flip-flops 22-0, ..., 22-n in the respective control blocks 12-0, ..., 12-n are respectively supplied to Among the memory blocks 11-0, ..., ll-n of the corresponding segments, a reset signal DCp is used as the memory cells 21-0, ..., 21_n. Further, the signals SAE[0], ..., SAE [n] output from the data output terminals D of the flip-flops 23-0, ..., 23-n are respectively passed through the delay circuits 25-0, ..., 25 -n is supplied to the memory blocks 11-0, ..., ll-n of the corresponding segments as the enable signals SAEn of the sense amplifiers 20-0, . . . , 20-η. Also, by 12 1291177 .16392pif.doc ΐ, 23: 〇, ..., 23·η data wheel output D output signal ..., S to the corresponding reference voltage production. 24 η Γ = action control signal V_called..., VREFG〇[n]=pressure amplifier VREF#仏i % _ , reference electric knife 刎彳~(7) to the corresponding segment of the memory block lU〇, & sense amplifier 2 〇_〇, ., 2〇_n. ..., Figure 2 is a picture! The memory block in the circuit shown is called the configuration example of =:. Figure 2 shows an example of the formation of the sensed :) = connection line. In the various positions of the job, there is no comparison section (Bai Didi, ^ Mao Lu Zhongxun and the two-way electricity #性=中的的化1〒 Take the round out - kind one, compare the result; the bad detection part (bad detection circuit), whether there is irreversible characteristic change or characteristic (4) individual special limitation; multiple flip-flops, which will sense, and shell; :: Sending to the outside or transferring the stylized data from the outside and adding the secret storage, the flip-flop and the logic circuit for the control are controlled. The memory block 11·1 is input to the instruction in the logic circuit 13 To control. The circuit (memory block) in Figure 2 overlaps in multiple stages, and the output terminals SO, P〇 of the kth segment are respectively connected to the input terminals si, pl' of the first correction segment to form Figure 1. The memory cell array 11 is shown. Here, the signals supplied to the initial input terminal SI, the PI protocol, and the output terminals s0, 13 c S ) 1291177 , 16392pif.doc P0 of the previous segment are provided by the signal of FIG. 1 The logic circuit 13 supplies and the plurality of segments are collectively controlled. The stylized circuit of the first 1-bit portion of the memory block Π-i has: electrical fuse 31_0, MOS transistor 32_〇, 33_〇, sense amplification, device (S/A) 34- 0, reverse gate 35-0, 36-0, 37-0, 38_〇, Xenopus, positive, reverse 40-0, 41-0 and two gates 42-0, 43-0. The voltage VBP is applied to one of the electrical fuses 31_〇, and the other φ electrodes are connected to one end of the current path of the M〇S transistor 32-0. The other end of the current path of the MOS transistor 32-0 is connected to the input of the sense amplification crying (S/A) and is simultaneously connected to one end of the current path of the M 〇s transistor 33_〇. A voltage * VTB is applied to the gate of the MOS transistor 32-0. The other end of the current path of the MOS transistor 33-0 is connected to the ground point GND, and the gate is connected to the output terminal of the AND gate 43_〇 to supply a programmed signal PRG [0]. The output signal SAt [〇] of the above-mentioned sensed amplification state 34-0 is supplied to one input terminal of the inverse gate 35-0, and the inverted signal SAe [〇] is supplied to the first input terminal of the inverse gate 36-0. . The signal SALD is supplied to the other input of the opposite. The signal VERIFY is supplied to the second input terminal of the anti-gate 36_〇, and the output signal of the flip-flop 40-0 is supplied to the third input terminal. One of the inputs of the anti-gate 37-0 is connected to the wheel-in terminal si, and the other input is supplied with the shift signal SHIFT. The output signals of the above-mentioned respective gates 35_0, 36-0, 37_〇 are respectively supplied to the gate 38-0, and the output signal of the gate 38-0 is supplied to the input terminal D of the flip-flop. The clock input terminal CK of the flip-flop 4 (H) is supplied
12911H 一種時脈信號FDCLK,由輸出端Q供給該位元的輸出信 號so [〇](對應於次段的輸入信號SI D])至次段的反及閑 37-1中且同時將該信號供給至反及閘39_〇的其中一個輸 入端。12911H A clock signal FDCLK, which is supplied from the output terminal Q to the output signal so [〇] (corresponding to the input signal SI D of the sub-stage)) to the inverse of the sub-segment 37-1 and simultaneously It is supplied to one of the inputs of the anti-gate 39_〇.
輸入端PI連接至正反器41_0的資料輸入端D,信號 FPCLK供給至時脈輸入端CK。由正反器41_〇的資料輸入 端Q所輸出的信號PM [0]供給至及閘43_〇的第i輸入端, 同時其反她琥供給至反及閘39_Q的另—個輸人端。信號 FPCLK供給至及閑43-0的第2輸人端,次段的正反器4M 的輸出信號PM [1]供給至第3輸入端。 反及閘39-0的輸出信號供給至及閘42_〇的苴中一個 輸入端。輸入端P!連接至及閘42_〇的另一輸入端,苴輸 出㈣供給至次段的正反器4M的資料輪人端d和該及 閘42 1的其巾—個輸人端,以作為該位元的輸出信號η 借.段的1位元部份的程式化電路亦與初段同樣具 3Μ ’则電晶體如,A1,感測放大器 (卿4·1 ’反及閘35_卜糾’ 37_卜38_卜叫,正反 态40-1,41-1以及二個及閘幻」,a」。 第m段(最終段)的丨位元部份的程式化電路的構成亦 :具f .電性溶絲如,M〇S電晶體32-m ’ 33-m ’感 測放大裔(S/A)34-m ’ 反及閘 35_m,3“,3ή“: 39,」正反器以及二個及鬧42-m,43_m。 敢終段的程式化電路的輸出側中設有正反器45。及閑 1291177 16392pif.doc 42-m的輸出信號供給至正反器、45的資 =LK供給至時脈輸人端CK,㈣料輸出端㈣輸㈣ 仏號PM [m+1]被反相以供給至及間心的第3輸入端。 然後,由及閘42-m的輪出端所連接的輪出端p〇和正 U 40-0的輸出端q所連接的輪出端s〇輪 外部中。 此處,以時脈信號FDCLK來動作的串聯相連接的正The input terminal PI is connected to the data input terminal D of the flip-flop 41_0, and the signal FPCLK is supplied to the clock input terminal CK. The signal PM[0] outputted from the data input terminal Q of the flip-flop 41_〇 is supplied to the ith input terminal of the AND gate 43_〇, and at the same time, it is supplied to the other input of the reverse gate 39_Q. end. The signal FPCLK is supplied to the second input terminal of the idle 43-0, and the output signal PM [1] of the secondary flip-flop 4M is supplied to the third input terminal. The output signal of the gate 39-0 is supplied to one of the inputs of the gate 42_〇. The input terminal P! is connected to the other input terminal of the gate 42_〇, and the output (4) is supplied to the data wheel terminal d of the secondary-stage flip-flop 4M and the towel-input terminal of the gate 42 1 . The stylized circuit of the 1-bit portion of the segment as the output signal η of the bit is also the same as the initial segment. The transistor is, for example, A1, the sense amplifier (Qing 4·1 'reverse gate 35_卜纠' 37_卜38_Bu, positive and negative 40-1, 41-1 and two and illusion", a". The m-segment (final segment) of the 丨 bit part of the stylized circuit Composition also: with f. Electrically soluble wire such as, M〇S transistor 32-m '33-m 'sensing amplification (S/A) 34-m 'reverse gate 35_m, 3", 3ή": 39 , "Flip-flops and two and 42-m, 43_m. The forward side of the stylized circuit has a flip-flop 45 on the output side. And the output signal of the 1291177 16392pif.doc 42-m is supplied to the front and back. The value of 45, LK is supplied to the clock input terminal CK, (4) The output end of the material (4) is output (4) The PM [m+1] is inverted to be supplied to the 3rd input of the center of the heart. The round-out end p〇 connected to the wheel-out end of the gate 42-m is connected to the output terminal q of the positive U 40-0 S〇 the wheel end of the outer wheel. N Here, in the operation of the clock signal FDCLK be connected in series
二二:^格減及崎絲資料暫存器’時脈信號 ^ LK來動作的串聯相連接的正反器群41_〇、…、* 稱為程式控制暫存器。 、圖3。係圖1和圖2中所示的〇τρ記憶體單元和 測放大器34的具體的構成之電路圖。此處,纟ρ通道型 MOS電晶體刪中分別形成閘極氧化膜破壞型的電性您 〜31_m。記憶體單元21以該m〇s電晶體刪和 通運型MOS電晶體mN0、MN1 (對應於圖2的M〇s電 晶體32-0〜32-m和33_〇〜33_m)來構成。 電壓VBP施加至M0S電晶體綱的源極,汲極 面(back)閑極,間極連接至M〇s電晶體丽〇的汲極(節點 N1)。電壓VBT施加至M〇s電晶體MN〇的閑極,源極連 接至MOS電晶體麵!的汲極(節點N〇)。信號供給 至MOS電晶體麵!的閑極,源極連接至接地點〇助。 该MOSj晶體應〇藉由閑極電麼VBT控制成適當的位 準而使節點N〇的電壓限制在” VBT-Vth (MOS電曰雕 麵的門限值電釘,為止,以防止高電_式化時的= 16 1291177 16392pif.doc VBP)施加至節點NO所連接的電晶體。 感測放大器34是—種由P通道型MOS電晶體MPi 〜MP5和f通道型M〇S電晶體MN2〜函戶斤構成的差 動型放大’錢鲜電壓VREF作為參考電壓,對該記 憶體單元21的節點N0的電壓和基準電壓乂卿的電壓進 行比較且放大而輸出-種差動放大信號 電晶體MN2的汲極連接至節點N〇,源極連接至接地點 GND。信號DCp供給至閘極。電晶體刪的源極連 接至電源VDD。信號SAEn供給至閘極。廳電晶體 MP2、MP3的源極連接至M〇s電晶體刪的沒極。m〇s 電晶體MP2的閘極連接至節點N〇。基準電墨vref施加 至MOS電晶體MP3的閘極。M〇s電晶體赠、跑的 沒極分別連接著MOS電晶體MP4、Mp5的源極。各M〇s 電晶體MP4、MP5的汲極和接地點GND之間分別連接著 MOS電晶體MN3、_4的汲極,源極間的區段。電 晶體MP4、麵3的閘極連接至M〇s電晶體Mp5、讀# 的汲極共通連接點,該輪出信號SAt由汲極共通連接點輪 出。MOS電晶體MP5、MN4的閘極連接至M〇s電晶體 MP4、MN3的汲極共通連接點,該輸出信號SAe由沒極共 通連接點輸出。 而且,MOS電晶體MP5的汲極連接至M0S電晶體 MP2和MP4的連接點,源極連接至接地點GND。電 晶體MN6的汲極連接至M〇s電晶體MN3的閘極,源: 連接至接地點GNDMOS電晶體_7的汲極連接至M〇s 17 1291177 16392pif.doc 電晶體MN4的閘極,源極連接至接地點gnd。μ〇§電晶 體MN8的汲極連接至M〇s電晶體Mp3和娜5的連接 點’源極連接至接地點GND。信號SAEn供應至M〇s電 晶體MN 5〜MN 8的閘極使這些M 〇 s電晶體之動作受到控 制。 又,信號PRGp的控制用白勺電路或輸出信號論、— 的讀出用的電路雖然存在,但此處省略。 又、,信號PRGp、DCP在未說明時固有(default)值是接 地點位準,^號SAEn在未時目有(default)值是電 壓VDD位準。 、义又’此處所使用的製造過程雖然以標準CM〇s製程作 =提’但具備2種類以上的厚度之閘極氧化膜之M〇s 兒日日肢亦可使用。電性溶絲所在的M〇s 薄的閑極氧化膜,除此之外的M0S電晶體;;有厚= 極氧化膜。 在上述的構成中,電性熔絲Mp〇在程式化時,即, MOS電日日日體MPQ _極氧化膜破壞㈣杨補)時,電壓 γ、ΒΡ㊂上升至很咼的位準,藉由信號上升至電源電 壓VDD的位準,則M〇s電晶體MN1成為導通狀態。因 此節點NO、N1下降至GND位準。高的電壓VBp施加 至MOS電晶體MP0的閘極氧化膜,會發生破壞而使電晶 脰‘通11亥‘通狀悲可考慮成破壞之後藉由電流集中流入 狹乍之破壞點所產生的焦耳熱中比較低電阻的傳導性 以不可逆的方式而形成者。 …、 18 1291177 .16392pif.doc • 在讀出上述電性熔絲MP〇的資料時,使電壓VBp成22: ^ 减 及 崎 崎 资料 资料 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 ,image 3. A circuit diagram of a specific configuration of the 〇τρ memory cell and the sense amplifier 34 shown in Figs. 1 and 2 is shown. Here, the 纟ρ channel type MOS transistor is cut into the gate oxide film to destroy the electrical type of ~31_m. The memory unit 21 is constructed by the m〇s transistor erase and pass type MOS transistors mN0, MN1 (corresponding to the M〇s transistors 32-0 to 32-m and 33_〇 to 33_m of Fig. 2). The voltage VBP is applied to the source of the MOS transistor, the back is idle, and the interpole is connected to the drain of the M〇s transistor (node N1). The voltage VBT is applied to the idle pole of the M〇s transistor MN〇, and the source is connected to the MOS transistor face! Bungee (node N〇). Signal is supplied to the MOS transistor face! The idle pole, the source is connected to the grounding point. The MOSj crystal should be controlled to a proper level by the idle polarity VBT to limit the voltage of the node N〇 to "VBT-Vth" (the threshold of the MOS electric enamel surface, so as to prevent high voltage _ In the case of the formula = 16 1291177 16392pif.doc VBP) is applied to the transistor to which the node NO is connected. The sense amplifier 34 is a type of P-channel MOS transistor MPi to MP5 and an f-channel type M〇S transistor MN2~ The differential type amplification of the letter jin is used as a reference voltage, and the voltage of the node N0 of the memory unit 21 is compared with the voltage of the reference voltage 乂 且, and amplified to output a differential amplified signal transistor. The drain of MN2 is connected to node N〇, the source is connected to ground point GND. The signal DCp is supplied to the gate. The source of the transistor is connected to the power supply VDD. The signal SAEn is supplied to the gate. Hall transistors MP2, MP3 The source is connected to the M〇s transistor, and the gate of the transistor MP2 is connected to the node N. The reference ink vref is applied to the gate of the MOS transistor MP3. The running poles are connected to the sources of MOS transistors MP4 and Mp5 respectively. Each M〇s transistor MP4 The drain of the MOS transistor MN3, _4 and the section between the source are connected between the drain of the MP5 and the ground GND. The gate of the transistor MP4 and the surface 3 is connected to the M〇s transistor Mp5, read # The common connection point of the drain, the turn-off signal SAt is rotated by the common connection point of the drain. The gates of the MOS transistors MP5 and MN4 are connected to the common connection point of the drain of the M〇s transistors MP4 and MN3, and the output signal is SAe is output by the common junction point. Moreover, the drain of MOS transistor MP5 is connected to the connection point of MOS transistor MP2 and MP4, and the source is connected to ground GND. The drain of transistor MN6 is connected to M〇s Gate of crystal MN3, source: Connected to ground GNDMOS transistor _7 the drain is connected to M〇s 17 1291177 16392pif.doc The gate of transistor MN4, the source is connected to the ground point gnd. μ〇§ transistor The drain of MN8 is connected to the connection point of the M〇s transistor Mp3 and Na. The source is connected to the ground point GND. The signal SAEn is supplied to the gates of the M〇s transistors MN 5 to MN 8 to make these M 〇s The operation of the crystal is controlled. Also, the circuit for controlling the signal PRGp or the output signal theory, the power for reading Although it exists, it is omitted here. In addition, when the signals PRGp and DCP are not described, the default value is the ground point level, and the ^SAEN is not present (default) is the voltage VDD level. In addition, the manufacturing process used here can be used in the standard CM〇s process, but the M〇s day and day limbs of the gate oxide film having two or more types of thickness can be used. The Mеs thin idle oxide film where the electrolytic solution is located, in addition to the M0S transistor; there is a thick = polar oxide film. In the above configuration, when the electrical fuse Mp is programmed, that is, when the MOS electric solar cell, the solar cell, the MPQ_polar oxide film is destroyed (four) Yangbu, the voltages γ and ΒΡ are raised to a very high level. When the signal rises to the level of the power supply voltage VDD, the M?s transistor MN1 is turned on. Therefore, nodes NO and N1 fall to the GND level. The high voltage VBp is applied to the gate oxide film of the MOS transistor MP0, and the destruction occurs, so that the electro-crystal 脰 '通11海' can be considered as a breakdown caused by the current concentrated into the narrow fracture point after the destruction. The conductivity of the lower resistance in Joule heat is formed in an irreversible manner. ..., 18 1291177 .16392pif.doc • When reading the data of the above-mentioned electric fuse MP〇, make the voltage VBp into
為電源電壓VDD的位準,為了防止節點N〇的電壓位準的 門限(threshold)值下降,則電壓VBT須由VDD位準上升 . 至門限電壓以上的高位準。然後,信號DCP上升至VDD “ 位準使M〇S電晶體^2導通,節點N0、N1下降至gnd 位準。一定時間之後,信號DCp下降至GND位準,M〇s 電晶體MN2回到關閉狀態。電性炼絲Mp〇被程式化時, • 纟於其電阻值變低,節點N0被充電,使電位隨著時間而 上升。對此而言,電性炫絲MP0未被程式化時,由於 漏電流對節點NO充電,則節點N〇幾乎保 準 適,SDT之後,基準tevREF成為㈣鲜和= • 辦之間騎當的中間電位。若信號SAEn由VDD位準下 降至GND位準,則感測於去哭…“ 位旱下 且保持著。結果,邱點^立準^^果被放大 低,則輸出咖位準而成為挪還 位準較基彻瓣還高,則輪出卿位右準郎謂的 攀圖4係圖!中所示電路之基準電廢產 〜―具體的構成之電路圖。基準 1 1 MOS電容的電荷共有 1生电路24”由於 變換成相對應的類比電請^。本瓣㈣ 準電塵VREF。 兀的數位值中頌示16位準的基For the level of the power supply voltage VDD, in order to prevent the threshold value of the voltage level of the node N〇 from decreasing, the voltage VBT must rise from the VDD level to a high level above the threshold voltage. Then, the signal DCP rises to VDD "level to turn on the M〇S transistor ^2, and the nodes N0, N1 fall to the gnd level. After a certain time, the signal DCp falls to the GND level, and the M〇s transistor MN2 returns. When the electric wire Mp is programmed, • When the resistance value becomes low, the node N0 is charged, causing the potential to rise with time. In this regard, the electric snagging MP0 is not stylized. When the leakage current charges the node NO, the node N〇 is almost guaranteed. After the SDT, the reference tevREF becomes the intermediate potential between the (four) fresh and the ?? if the signal SAEn falls from the VDD level to the GND position. Quasi, then feels to cry..." The position is dry and keeps. As a result, Qiu points ^ 准 准 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The reference circuit of the circuit shown in the electric waste production ~ specific structure of the circuit diagram. The reference 1 1 MOS capacitor charge is shared by the 1 circuit 24" because it is converted into the corresponding analog power. ^ This valve (4) Quasi-electric dust VREF. 兀 The digital value of the 颂 indicates the 16-bit basis
即,基準麵產生電路糾具備:Pif道型·U 19 1291172· 谷51,反相器52,及閘53〜56,P通道型MOS電晶體That is, the reference plane generating circuit is provided with: Pif type U 19 1291172 · Valley 51, inverter 52, and gate 53 to 56, P channel type MOS transistor
MP6〜MP9’N通道型MOS電晶體MN9〜MN13以及M〇S 電容Cl〜C4。 MOS電谷51中的一個電極連接至電源VDD,另 個 電極則連接至基準職VREF輸出㈣輸出端。 上述基準電壓VREF輸出用的輸出端分別連接至 MOS私晶體MN9〜MN13的沒極。购8電晶體MN9的源 極連接至接地點GND,閘極連接至反相器52的輸出端:、 乜唬VREFGO供給至反相器、52的輸入端。M〇s電晶體 MN10〜MN13的没極分別連接著M〇s電容C1〜C4的— 们包極’及閘53〜56的輸出端連接至閘極。各m〇s電容 Cl C4的另-個電極連接至接地點電晶體 =6 MP9的源極連接至電源、VDD,汲極分別連接至各 〇s私谷ci〜C4的一個電極。信號VREFG〇供給至各 ,閘53〜56的一個輸入端,數位信號dvref⑼〜 [3]分別供給至另一輸入端。 構成中’針對記憶元件(OTP記憶d的資訊 之私式化纽上是如圖5的流簡所示的方式來進行。 在先政Ϊ由元物生在電性上不可逆地變化,使資訊 在圮fe兀件中被程式化(步驟υ。 其次,使不可逆地已 的續出動作時的檢測能力 狀態相區別以進行檢測, 2)。 變化的記憶元件的狀態在較通常 還低的檢測能力下可與未變化的 然後由記憶元件讀出資訊(步驟 20 1291177 ,16392pif.doc ;、、;、後對5亥圮憶元件中已程式化的資訊和由該記憶元 件中所讀出的資訊進行比較,以輸出-種-致/不-致的比 較結果(步驟3)。 1丰比較結果不—剌的位元_地特定成不良位 :二μ依據轉定的不良位元的資訊來對該記憶元件 進订再粒式化(步驟5)。 依據上述二的程式化方法,切換該電路設 (margin)車父通常使用眭、晉^ # τ 以檢出程式化, JU、/ 有邊際特性的位元,進行再藉 =以便救濟,__改良以達成高成品率和高信 序圖來ί二= 2,=:,藉由圖6至圖9的時 如圖!所示的電路Lif電路構成有關的動作。 以4段㈣)堆疊而成,則2記憶體方塊祕...'h (VERIFY=L)用的時序圖。 即為顯不通常的感測動作 右由外部輸入一種感涓於八 電路)13可隨時發出内部俨號,則由邏輯電路(介面邏輯 高(H),,位準,若感測動作開=雄首先,信號SENSE成為,, 會動作。又,藉由信號SEN^丁,古則時脈產生電路Η即 路15動作。依據時脈產生電路的鬲位準而使直流控制電 以產生一種信號DCCLK。每〜 14所輪出的時脈信號CLK 塊1段進行重置(reset)且另—周』中一方面對記憶體方 N1進行重置。若全部的段 對龟性'丨谷絲ΜΡ0的節點 勺重置已终了(DCDONE二H),則 21 1291177 ,16392pif.doc =^制電路i 5停止該信號DCCLK的輸出,信號sdt⑻ 成為向”位準,計數器17成為致能狀態而開始進 號CLK的計數動作。該計數器17在每個時脈信號: 生時使由多工器18施加至初期設定端顧上的初期^ 少,若該計數值成為〇,則輸出一種,,高,,位準的_號sag〇 通常動作時,由於VERIFY=0 (“低(Ly,位^ 。 多工器18來選取TSDTN㈣的值,成為_種對應於^ 的STD。該感測放大控制電路16接收該信號sa⑻ 位準且使❹mA|i致能錢SAEN絲高位準 : 時脈信號CLK而產生-種信號SACLK。信號saclk = 母一周期中-方面對記憶體方塊丨段進行活性化且另 面產生基準電壓¥腳以及使❹极Μ活性化。 在各控制方塊^、...、以中,由正反器23_〇、、 23_η所輪出的信號VREFG(^成為高 美 ,產生電路綱、…、…以產生基準電壓=基= 請作時由於徽IFY=G,則藉由多工$ i TVR娜叫由各段的基準電壓產生電路24^取= =生-雜應於信號TVREFN㈣的 ㈣電荷共有:在等待基準電壓避F的I; 為二位成的延遲後,信號sae [n]由高位準成 被閃鎖住。 切糊㈣壓值受到感測而 Π有VER勝Η,其它信號的順序全部未改 交。然而,植n π的初缝麵域tsdtv㈣,基 22 1291177 16392pif.doc 準電壓產生電路24-0、···、24-n產生一種以信號DVREFV [3-0]所決定的位準的基準電壓VREF。因此,若設定成 TSDTN > TSDTV、TVREFN < TVREFV,則使驗證時的 SDT和基準電壓VREF變化後可嚴格地設定”】,,資料的感 測邊際(margin)。 圖7係圖2中所示的感測放大器34-0〜34-m中已問鎖 的電性纟谷絲31-0〜31-m的記憶資料讀出至外部時的各信 號的時序圖。首先,若輸入時脈信號FDCLK使信號 SALD=H,信號SHIFTS,信號VERIFY二L,則感測放大 裔34-0、…、34_m的輸出被載入(i〇aded)至熔絲資料暫存 态(正反器40_〇、···、4〇-m)中。然後,若輸入時脈信號 fdclk使信號SALD=L,信號smFT=H,信號 ERIFY L則可由輸出端SO依序(serially)讀出資料。 士為了在電性熔絲31_〇〜31-m中進行程式化,則如圖8 ,時序圖所示,藉由時脈賤FDCLK由輸人端SI將應程 式化的資料依序輸人至料資料暫存器(正反器.〇、、 抓叫中,使SALI>L,SHIFMi,呢應何。然後, 如圖9的_騎*_細進行料化動作。 此處,1”設定至位元i的溶絲資料暫存器咖中, =以外的王部的位几設定成,,〇,,,因此成為S , s〇[l]爿,S〇[2-mH)〇 出^=^在低位準時,全部的及閘伽〜42_m的輸 ,Γ已°將评、PI [2]、...、PIM由於成為,,低,,位準,則 輸人端PI設定成,,低,,位準的原來的時脈信號 < S ) 23 1291177 163 ppif.doc fdclk 在 哭4】n〜々周期中被輸入,可對各程式控制暫存器(正及 7 4 -m)進行初始化,正反器4Ι·〇〜仏⑺沾私山丄 號 ΡΜ[〇]、.··、PM [m+l]全部成為,,〇,,。電屏 VBT : ^ 上升,電壓VBP上升至程式化用的高;、,準 成為”高”位準,蕤由砗骱γ味 土爰幸則入糕ΡΙ —^ 猎由守脈k^FPCLK的輪入,則可使,Ί” ==且叫k,的狀態才會2。::;; :LK只有在高位準期間該程式化信號pR ^ 兩位準以進行程式化。 []才s成為 個,9中雖'然只顯示1位元的程式化動作,但對多 ^貝料進行程式化時’只有溶絲資料暫存器中已設定 ^的位以可在每辦脈帽丨位元進行程式化。即使 段的位元中,仍可藉由剩餘1位元的程式控制暫存 為(曰反$45)的存在而與其它位元同樣地被程式化。 取後的”1”資料的程式化中由於輸出端p〇成為,,高,,位 二’則可由外部檢出程式化的終點,使全部的程式化時間 最小。、若熔絲資料暫存器的全部的位元成為”〇,,,則輸入端 pi成為高位準時,未輸入該時脈信號FpcLK的輪出端卩〇 會成為局位準。 電壓VBP設定成感測時的電位,以對已程式化的資料 進行感測。感測時若VERIFY=H,則如前所述邊際之程式 化不良的位元被感測成”〇”。此處,位元i成為程式化不良 時’則SAt [1卜0 (SAc [1卜1)。然後,VERIFY=H而保持 原狀時,若輸入時脈信號fDCLK,則由於SI [η (s〇 24 I2911?63Uc [0])=1,SAc [1]二1,則相對應的熔絲資料暫存器中$ a 成1 ’。記憶著”0的位元k成為SI [k] (SO [k-l]>=〇,SA ,炫絲資料暫存器中設定成,,Q,,。又,㈣良好的記e 憶著”1”的位元k成為SI [k]=l,SAc [k]=〇,仍然是SI [k]=l,SAc Μ=0,相對應的炼絲資料暫存器中設定成^,,。 即,藉由載入該感測放大器和溶絲資料暫存器的值的渾管 結果,舰絲資料暫存器的,,!,,資料成為所要程式化= 料’只有已失敗的位元才會再設定成”1,,。 、 藉由上述方式,若存在著不良的1位元,即使輸入端 Η設定成高位準,輸出端P〇仍保持著低位準。若 輸入端ΡΙ成為高位準,此時輸出端Κ)由Ϊ = FPCLK未輪人時的高鱗, f,的1位/時,可判定該程式化的一致/不= 又,在發生不良情況時,若進行其原來的程式化動作則 料程式料㈣㈣可再料細 j 施形式中可效率良好地進行電性炫絲的驗證,一Γ/Γΐ 的判定以及再程式化。 且致/不一致 的狀的構成,已不可逆地變化之記情元件 已程式化的狀態以it行檢測時 =之猎由&別 讀出資訊,則該資訊具有充份用:4(贿㈣變低以 狀態進行驗證。職—细何_式化之後的 又内4中猎由设置良/不良的檢測電路和進行不良位 1291177 16392pif.doc ί的特定利恤,㈣彻物^位元的救 置及二= 現if體積體電路裳 查效率的-次可程式率,咖性以及高檢 ,明二Ϊ以上的實施形式的說明中,雖然以舉例方式來 ,π種閑極氧化物電性料,其藉由]vi〇s η門 閘極乳化物電性熔絲。例如,電性熔衅,、 破壞型電性溶絲,待蝴=:;r種導電膜 被破壞以進行程式化—lde)㈣的導電膜 溶2=34 ’依據本發明的—種外觀,可使該使用電性 記鐘的驗證的檢魏力提高,藉由已檢出的 ^ 70再破程式切進行讀,射制高成品率_ U 貝性的半導體積體f路裝置及其程式化方法。 6雖然本發明已以較佳實施例揭露如上,然其並非 發明’,任何熟習此技藝者,在不脫離本發明之精神 二耗圍内’當可作些許之更動與潤飾,因此本發明之保 靶圍當視後附之申請專利範圍所界定者為準。 w 【圖式簡單說明】 圖I係繪不本發明的實施形式中的半導體積體電路裝 置’其係一種已將OTP記憶體以及與〇τρ記憶體的程 化和感測動作有關的周邊電路抽出後的方塊圖。 圖2係圖1所示的電路中之記憶體方塊的詳細的構成 1291177 16392pif.doc 例。 圖3係圖1和圖2中OTP記憶體單元和感測放大器的 具體的構成之電路圖。 圖4係圖1中所示電路之基準電壓產生電路的具體的 構成之電路圖。 圖5係本發明的實施形式中OTP記憶體的程式化方法 況明用的流程圖。 圖6係圖1所示的電路中記憶體方塊以4段堆積而成 時顯示通常的感測動作用的時序圖。 圖7係圖2中所示的感測放大器中已閂鎖的電性熔絲 的記憶資料讀出至外部時的各信號的時序圖。 圖8係圖2中所示的電性熔絲中進行程式化時的各信 號的時序圖。 圖9係顯示圖1至圖4所示的半導體積體電路裝置中 之程式化動作的時序圖。 【主要元件符號說明】 11 記憶體單元陣列 12 控制電路 13 邏輯電路 14 時脈產生電路 15 直流控制電路 16 感測放大器控制電路 17 計數器 18、19 多工器 27 1291177 16392pif.docMP6 to MP9'N channel type MOS transistors MN9 to MN13 and M〇S capacitors C1 to C4. One of the electrodes in the MOS valley 51 is connected to the power supply VDD, and the other electrode is connected to the output of the reference VREF output (four). The output terminals for the output of the reference voltage VREF are respectively connected to the terminals of the MOS private crystals MN9 to MN13. The source of the 8-electrode MN9 is connected to the ground GND, and the gate is connected to the output of the inverter 52: 乜唬VREFGO is supplied to the input of the inverter 52. The output terminals of the M〇s transistors MN10 to MN13 connected to the M〇s capacitors C1 to C4, respectively, and the outputs of the gates 53 to 56 are connected to the gate. Each m〇s capacitor Cl C4 has another electrode connected to the grounding point transistor =6 The source of MP9 is connected to the power supply, VDD, and the drain is connected to one of the electrodes of each of the 私s private valleys ci~C4. The signal VREFG is supplied to one input terminal of each of the gates 53 to 56, and the digital signals dvref (9) to [3] are respectively supplied to the other input terminal. In the configuration, the information on the memory element (the information of the OTP memory d is performed in the manner shown in the flow diagram of Fig. 5. The first political power is electrically irreversibly changed by the metaphysical material, so that the information It is stylized in the 圮fe condition (step υ. Secondly, the state of the detection capability when the irreversible renewed action is made is distinguished for detection, 2) The state of the changed memory element is detected at a lower level than usual. The ability to read the information with the unaltered and then read by the memory element (step 20 1291177, 16392pif.doc;,;;, after the programmed information in the device and read from the memory element The information is compared to output-species-induced/not-induced comparison results (step 3). 1 The results of the abundance comparison are not—the bits of the _-specifically become bad bits: the information of the two μ-based bad bits The memory element is ordered and re-granulated (step 5). According to the above-mentioned two stylized method, switching the circuit design (margin) usually uses 眭, 晋^# τ to detect stylization, JU, / Bits with marginal characteristics, re-borrow = for relief, __ improved to achieve The high yield and the high-order map are ί2 = 2, =:, and the circuit Lif circuit shown in Fig. 6 to Fig. 9 constitutes the related action. Stacked in 4 segments (four)) 2 memory block secret... 'h (VERIFY=L) used for the timing diagram. That is, the display is not normal, the right input is externally input by a sense of eight circuits) 13 can be issued at any time, the internal nickname Logic circuit (interface logic high (H), level, if the sensing action is on = male first, the signal SENSE becomes, will act. Also, by the signal SEN^, the ancient clock generation circuit Η路15 Action: The DC control circuit generates a signal DCCLK according to the threshold of the clock generation circuit. Each of the 14 clock signals CLK block is reset (reset) and the other side is on the other hand. Reset the memory side N1. If all the segments have been reset to the node spoon of the tortoise '丨谷丝ΜΡ0 (DCDONE II H), then 21 1291177, 16392pif.doc =^ circuit i 5 stops the signal At the output of DCCLK, the signal sdt(8) becomes the "level", and the counter 17 becomes the enable state and starts the counting operation of the number CLK. The counter 17 is Clock signal: When the multiplexer 18 is applied to the initial setting terminal, the initial value is small. If the count value is 〇, the output is one, high, and the level _ sag 〇 normally operates. Since VERIFY=0 ("Low, bit ^. multiplexer 18 selects the value of TSDTN (4), becomes the STD corresponding to ^. The sense amplification control circuit 16 receives the signal sa(8) level and makes ❹mA| i can make money SAEN wire high level: the clock signal CLK produces a kind of signal SACLK. The signal saclk = mother-cycle is activated in the memory block segment and the reference voltage ¥ foot is generated and the ❹ Μ is activated. In each control block ^, ..., in, the signal VREFG (^ becomes a high-quality, generating circuit outline, ..., ... to generate the reference voltage = base = please In the case of the IFY=G, the multiplexed $i TVR is called by the reference voltage generating circuit 24 of each segment. == Raw-heterogeneous (4) charge sharing of the signal TVREFN(4): Waiting for the reference voltage to avoid F I; After the delay of the two digits, the signal sae [n] is flash locked by the high level. The paste (4) pressure value is sensed and VER wins, and the order of other signals is not changed. However, The initial surface area of n π is tsdtv (4), base 22 1291177 16392pif.doc The quasi-voltage generating circuits 24-0, ···, 24-n generate a reference voltage VREF of the level determined by the signal DVREFV [3-0] Therefore, if TSDTN > TSDTV and TVREFN < TVREFV are set, the SDT and the reference voltage VREF at the time of verification can be strictly set, and the sensing margin of the data can be set. Among the sense amplifiers 34-0 to 34-m shown in the sense, each of the signals when the memory data of the lock-up electrical 纟谷丝 31-0 31 31-m is read out to the outside Timing diagram. First, if the input clock signal FDCLK causes the signal SALD=H, the signal SHIFTS, and the signal VERIFY to be L, the output of the sense amplifiers 34-0, . . . , 34_m is loaded (i〇aded) to the fuse. Data temporary state (positive and negative device 40_〇,···, 4〇-m). Then, if the input clock signal fdclk makes the signal SALD=L, the signal smFT=H, the signal ERIFY L can be output SO Serially read the data. In order to program in the electrical fuse 31_〇~31-m, as shown in the sequence diagram, as shown in the timing diagram, the clock 贱FDCLK will be input by the input terminal SI. The stylized data should be input to the material data register in sequence (pros and cons. 〇,, 抓, to make SALI> L, SHIFMi, what should be. Then, as shown in Figure 9 _ riding * _ fine Materialization action. Here, 1" is set to the dissolution data holder of the bit i, and the position of the king other than = is set to, 〇,,, and thus becomes S, s〇[l]爿,S〇[2-mH)〇^=^ At the low level, all and the gates are ~42_m, the Γ has been evaluated, PI [2], ..., PIM is due, low, Level, the input terminal PI is set to, low, bit The original clock signal < S ) 23 1291177 163 ppif.doc fdclk is input during the crying 4]n~々 cycle, and the program control registers (positive and 7 4 -m) can be initialized, positive and negative. 4Ι·〇~仏(7) 沾私丄丄 ΡΜ[〇], .··, PM [m+l] all become, 〇,,. The electric screen VBT: ^ rises, the voltage VBP rises to the height of the stylization; the quasi-become becomes the "high" level, and the 砗骱 味 味 味 则 则 入 入 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ k k k k k If you enter, you can make Ί" == and call k, the state will be 2.::;; : LK only during the high level period, the stylized signal pR ^ two are quasi-programmed. Although 9 shows only 1 bit of stylized action, when stylizing multiple materials, 'only the bits in the dissolve data register have been set to be available in each pulse cap. The element is stylized. Even if the bit of the segment is controlled by the remaining 1-bit program, it can be stylized in the same way as other bits by the existence of the temporary storage (reverse $45). In the stylization of the data, since the output p〇 becomes, high, and bit two' can be programmed by the external end point to minimize the total programming time. If the fuse data register is all bits When the input terminal pi becomes a high level, the wheel end of the clock signal FpcLK is not entered. The voltage VBP is set to the potential at the time of sensing to sense the programmed data. If VERIFY=H during sensing, the stylized bits of the margin described above are sensed as "〇". Here, when the bit i becomes a stylized failure, then SAt [1b 0 (SAc [1 Bu 1]). Then, when VERIFY=H remains in the original state, if the clock signal fDCLK is input, since SI [η (s〇24 I2911?63Uc [0])=1, SAc [1] two, the corresponding fuse data $ a becomes 1 ' in the scratchpad. It is remembered that the bit k of "0" becomes SI [k] (SO [kl]>=〇, SA, and the Hyun data buffer is set to, Q,, and again. (4) Good record e remembers" The bit k of 1" becomes SI [k]=l, SAc [k]=〇, still SI [k]=l, SAc Μ=0, and the corresponding wire data buffer is set to ^, That is, by loading the value of the sense amplifier and the data buffer register, the ship data register, , !, the data becomes the desired program = material 'only failed bit The element will be set to "1,". By the above method, if there is a bad 1-bit, even if the input port is set to a high level, the output terminal P〇 remains at a low level. High level, at this time, the output terminal Κ) Ϊ = FPCLK is not rounded when the high scale, f, 1 bit / hour, can determine the stylized consistency / no = again, in the event of a problem, if it is carried out The original stylized action program material (4) (4) can be used to verify the efficiency of the electric shattering wire, the determination of the Γ/Γΐ and the re-stylization. And the composition of the inconsistency, the irreversible change of the estranged component has been stylized. When it is detected by the IT test, the information is used for the information: 4 (Brit (4) Going down to verify the status. The job---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Rescue and two = current if the volume of the circuit is checking the efficiency - the second program rate, the coffee and the high inspection, in the description of the implementation form above, although by way of example, π kinds of idle oxide Material, which consists of a vi〇s η gate gate emulsion electrical fuse. For example, electrical melting, destructive electrical melting wire, to be smeared =:; r kinds of conductive film is destroyed for program -1de) (4) The conductive film dissolves 2 = 34 'In accordance with the appearance of the present invention, the verification power of the verification using the electric clock can be improved, and the detected method is further performed by the method Read, shoot high yield _ U shell semiconductor integrated circuit f device and its stylized method. 6 Although the present invention has been disclosed in the above preferred embodiments, it is not an invention, and any person skilled in the art can make some modifications and retouchings without departing from the spirit of the invention. The target area is defined in the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a semiconductor integrated circuit device in an embodiment of the present invention, which is a peripheral circuit in which an OTP memory and a process of sensing and sensing the 〇τρ memory have been performed. The block diagram after the extraction. Figure 2 is a detailed diagram of a memory block in the circuit shown in Figure 1 1291177 16392pif.doc. Fig. 3 is a circuit diagram showing a specific configuration of an OTP memory cell and a sense amplifier in Figs. 1 and 2. Fig. 4 is a circuit diagram showing a specific configuration of a reference voltage generating circuit of the circuit shown in Fig. 1. Fig. 5 is a flow chart showing the stylization method of the OTP memory in the embodiment of the present invention. Fig. 6 is a timing chart showing a normal sensing operation when the memory blocks are stacked in four stages in the circuit shown in Fig. 1. Fig. 7 is a timing chart showing signals when the memory data of the latched electrical fuse in the sense amplifier shown in Fig. 2 is read out to the outside. Fig. 8 is a timing chart showing signals in the case where the electric fuse shown in Fig. 2 is programmed. Fig. 9 is a timing chart showing the stylized operation in the semiconductor integrated circuit device shown in Figs. 1 to 4 . [Main component symbol description] 11 Memory cell array 12 Control circuit 13 Logic circuit 14 Clock generation circuit 15 DC control circuit 16 Sense amplifier control circuit 17 Counter 18, 19 Multiplexer 27 1291177 16392pif.doc
11-0、··· 、11 -n 記憶體方塊 12-0、.·· 、12_n 控制方塊 20-0、··· 、20_n 感測放大器 21-0 > ... 、21-n 記憶體單元 22-0、··· 、22-n 正反器 23-0、··· 、23-n 正反器 24-0、··· 、24-n 基準電壓產生電路 25-0 > ... > 25-n 延遲電路 31-0 > ... 、31-m 電性熔絲 32-0 > ... 、32-m MOS電晶體 33-0、··· 、33-m MOS電晶體 34-0、··· 、34-m 感測放大器 35-0 ^ ... 、39-m 反及閘 40_0、··· 、41-m 正反器 42-0、··· 、43_m 及閘 51 P通道型MOS電容 52 反相器 53 〜56 及閘 ΜΝ0 〜MN13 N通道型MOS電晶體 ΜΡ0 〜MP9 P通道型MOS電晶體 C1 〜C4 電容 2811-0,···, 11 -n memory block 12-0, .··, 12_n control block 20-0, ···, 20_n sense amplifier 21-0 > ..., 21-n memory Body unit 22-0, ···, 22-n flip-flop 23-0, ···, 23-n flip-flop 24-0, ···, 24-n reference voltage generating circuit 25-0 > ... > 25-n delay circuit 31-0 > ..., 31-m electrical fuse 32-0 > ..., 32-m MOS transistor 33-0, ···, 33 -m MOS transistor 34-0, ···, 34-m sense amplifier 35-0 ^ ..., 39-m reverse gate 40_0, ···, 41-m flip-flop 42-0, · ··, 43_m and gate 51 P channel type MOS capacitor 52 inverter 53 to 56 and gate 0 to MN13 N channel type MOS transistor ΜΡ0 to MP9 P channel type MOS transistor C1 to C4 capacitor 28