1289924 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種深溝渠式（deep-1 rench)半導體記憶體 單元結構及其製法，尤指一種深溝渠式單電晶體隨機存取記憶 體（1T-RAM)元件及其製法。根據本發明之較佳實施例，深溝渠 式單電晶體隨機存取記憶體元件利用形成於溝渠電容下部之 外擴散井（out diffusion well)與離子佈植井（impiantati〇n ion well)貫通連結，藉此得到較高的電容值(Cs)以及低漏電 流（leakage)特性。 【先前技術】 一般電腦系統使用的隨機存取記憶體可分為動態以及靜態 Ik機存取記憶體，其差異在於動態隨機存取記憶體一個位元只 使用一個電晶體，需要週期性地補充電源(refresh),以保持 战體内錄不會流失，靜態隨機存取記憶雜關每個位元 使用4個或6個電晶體(4T/6T)組成，不需要週期性地補充電 源速度較快，價格也較高。電腦中的主記憶體一般都是使用 DRAM，快取記憶體（cache memory)則是採用SRM。 1289924 隨著科技進步，可攜式小型電子產品如手機、個人數位助 理（PDA)等也越來越普遍地被大眾所使用，這些電子產品受限 於電池以及體積需要搭配高密度高效能低電壓的系統單晶片 嵌入式記憶體裝置，因此發展出如該行業者所知的單電晶體靜 態隨機存取記憶體UT-SRAM)元件。這類單電晶體靜態隨機存 取圯憶體元件與傳統由六個電晶體所構成之靜態隨機存取記 憶體（six-transistor SRAM)不同在於其具有更高的元件密 度、較佳的操作效能、更為省電及較簡化的電路設計，並且可 以利用純粹邏輯（l〇gic)製程製作或利用嵌入(embedded)記憶 體製程製作。 單電晶體靜態隨機存取記憶體（1T—SRAM)技術使用平置的 電容來構成記憶體位單元，作用與標準六電晶體81^^相似， 但部只佔約一半的裸片面積，儲存密度比標準SRAM高約四 倍。作法是將電容折成接近90度角嵌入蝕刻在矽晶片上的溝 槽或空穴内，從而減小了儲存單元尺寸。但為了構建儲存單 元須對製造製程做某些改動：增加一次光罩，並添加新的姓 刻和植入步驟，以便形成能嵌入電容2/3體積的空穴。相關之 先W技術可參考 MoSys 公司（Monolithic System Technology) 所有之美國專利第6028804號「IT-SRAM相容記憶體之方法及 叙置（Method and apparatus for 1T-SRAM compatible 1289924 memory)」以及美國專利第6573548號r動態隨機存取記憶體 具有部分製作於空穴内之電容結構及其操作方法(DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same)」。 然而’習知單電晶體靜態隨機存取記憶體（1T—即使使 用隶先進之製程技術其單位記憶體胞所佔面積仍達 0.5〜0.6"m2，而且製程成本相對於標準邏輯製程仍高出約 4%。此外，習知單電晶體靜態隨機存取記憶體（1T—S^)只有 增加少量的電容值（約3〜7fF)。再者，在相鄰兩電容之間的 絕緣性差亦是習知單電晶體靜態隨機存取記憶體（1T-sram )主 要缺點。由此可知，該等單電晶體靜態隨機存取記憶體 (IT-SRAM)技術仍有進一步改善之空間。 【發明内容】 據此，本發明之主要目的在於提供一種深溝渠式單電晶體 靜態隨機存取記憶體（IT-SRAM)元件及其製法。 根據本發明之較佳實施例，本發明係揭露一種深溝渠電容 記憶體單元結構，包含有—第—導魏first _ductivity 1289924 type)半導體基底，具有一主表面（main surface); 一第二導 電型（second conductivity type)離子佈植井，具有一井接面 深度（well junction depth)，設於該半導體基底之該主表面 上；一閘極介電層，設於該離子佈植井上；一閘極，設於該閘 極介電層上；一第一導電型重摻雜(heavily d〇ped)區，設於 閘極一側之該離子佈植井中；一第一導電型輕摻雜（lightly doped)區，設於閘極與該第一導電型重摻雜區相反之另一側之 該離子佈植井中；以及—深溝渠電容，錢触表面形成於該 半導體基底内並向下深入超過該離子佈植井之井接面深度至 一預定深度，例如3至5微米深，其中該深溝渠電容包含有一 離子外擴散井（i〇n QUt diffusiQn weu)，其形成於該溝渠電 谷之下邻，並與该離子佈植井貫通連結(㈤打狀），其中該深溝 渠電容另包含有一多晶矽電極，其係藉由一電容介電層 (capacitor dielectric)以及一溝渠上端絕緣層（trench ΐορ insulation layer)與該第一導電型輕摻雜區、該離子佈植井 以及a亥外擴散井電性隔絕。 根據本發明之較佳實施例，深溝渠式單電晶體靜態隨機存 取记丨思體7L件利用形成於溝渠電容下部之離子外擴散井與形 、：半^豆基底表面之離子佈植井（丨即 貝通連結’藉此得到較高的電容值(Cs)以及低漏電流（leakage) 1289924 特性。 為了使責審查委員能更近一步了解本發明之特徵及技術内 各明參閱以下有關本發明之詳細說明與附圖。然而所附圖式 僅仏參考與輔助說明用，並非用來對本發明加以限制者。 【實施方式】 首先’請參閱圖九，本發明係關於一種深溝渠電容記憶體 單元結構’包含有一第一導電型（first conductivity type) 半導體基底10，具有一主表面（main surface)ll ; —第二導 電型（second conductivity type)離子佈植井20，具有一井 接面深度(well junction depth)，設於該半導體基底1〇之該 主表面11上；一閘極介電層72，設於該離子佈植井20上； 一閘極81，設於該閘極介電層72上；一第一導電型重摻雜 (heavily doped)區101，設於閘極81 —側之該離子佈植井2〇 中；一第一導電型輕摻雜（lightly doped)區1〇2，設於閘極 81與該第一導電型重換雜區101相反之另一側之該離子佈植 井20中；以及一深溝渠電容120，垂直該主表面π形成於該 半導體基底10内並向下深入超過該離子佈植井20之井接面深 度至一預定深度，例如3至5微米深，其中該深溝渠電容12〇 1289924 包含有一離子外擴散井（iQD Qiit diffusion well)25 ,其形成 於忒溝木電谷12〇之下部，並與該離子佈植井2〇貫通連結 (m6rge)，其中該深溝渠電容120另包含有一多晶矽電極34， 乂、係籍由一電容介電層（capacitor dielectric)32以及一溝 :而、邑、彖層（trench top insulation layer)105 與該第一 導電型輕摻雜區102、該離子佈植井20以及該外擴散井25電 性隔絕。 明參閱圖一至圖九，圖一至圖九顯示依據本發明較佳實施 例衣作先進深溝渠式（deep—trench)記憶體元件的剖面示意 圖。如圖一所示，首先提供一基底10，例如P型摻雜矽基底， 其内形成有一 N型井20。N型井20的井接面深度約為〇· 5至 1· 5微米（micrometer)，較佳為1微米左右。然後，利用已知 技術，例如微影（lithographic process)以及乾蝕刻，於沿著 基底10之一表面11向下深挖穿過N型井2〇形成離p型基底 1〇之表面11深約為3至5微米（較佳為3· 5微米）左右的兩相 鄰深溝渠（deep trench)15及16。於矽基底1〇挖出深溝渠之 技術乃該行業者所熟知，可利用光阻以及沈積於矽基底表面上 之襯墊層100，例如襯氧化石夕層12以及襯既化砍層14，作為 餘刻遮罩’配合反應性離子钮刻（reactive ion etching，RIE) 製程進行之。 1289924 接者’如圖二所示，在距離基底10表面下約4000至6000 埃左右之珠度的〉米溝渠15及16表面側壁以及底部進行高濃度 N換雜’例如先沈積坤碎玻璃（gxsejiic si 1 icate glass， ASG)，隨後以熱製程驅入(thermal drive-in)，或直接沈積高 》辰度摻雜之多晶石夕層。根據本發明之較佳實施例，先於深溝渠 15及16表面侧壁以及底部沈積一層石申石夕玻璃21，然後於深溝 渠15及16内填入光阻層（圖未示）’回|虫刻該光阻層至預定之 深度，例如距離基底10表面下約4000至6000埃左右之深度， 再去除未被該光阻層覆蓋之砷矽玻璃21，去除光阻層後，以 熱驅入製程將N型摻質由石申石夕玻璃21擴散進入與珅石夕玻璃21 接觸之深溝渠15及16内的基底1〇中，藉此形成一離子外擴 散井（ion out diffusion well)或稱為埋入式(buried)N+摻雜 區25。最後，將砷矽玻璃21去除。如前所述，在本發明之其 它較佳實施例中，砷矽玻璃21亦可以由重摻雜之多晶矽層代 替，此時，形成埋入式摻雜區25後，可以不用將重摻雜之 多晶矽層去除，而將其留置於深溝渠15及16内。由圖中可特 別看出，本發明形成在深溝渠丨5及16下部之埋入式N+摻雜區 25乃與N型井20相連貫。 如圖三所示，接著於襯墊層1〇〇以及深溝渠15及16内壁 12 1289924 上形成$合"電層32，例如氧化石夕_氮化石夕—氧化石夕(_介 電層，但不限於此。隨後於深溝渠15及16内填滿n推雜多晶 矽層34。 如圖四所不’接著回綱摻雜多晶㊉層％至深溝渠巧及 16内低於基底10表面下預定深度，例如100至400埃，較佳 為200至3GG埃。隨後’再以濕姓刻方式去除暴露出來的電容 ;丨电層32此日守’於沬溝渠15及16各形成凹陷口奶以及站。^ 此時，大致完成深溝渠電容12〇以及14〇之製作。 如圖五所示，接著進行邏輯淺溝絕緣模組（logic STI module)製程。根據本發明之較佳實施例，首先於基底上沈 積一介電層52，例如硼矽玻璃（b〇r〇silicate bsg)， 亚填滿凹陷口 45以及46。然後於介電層52上以黃光製程定 ，光阻層54 ’其具有一開口 55，定義淺溝絕緣區域。在其它φ 實施例中，介電層52與光阻層54之間可以有-層抗反射層， 但其並非本發明之魅。然後，再_光阻層％與介電層曰泣 作為I虫刻遮罩，經由光阻層54中的開口 55向下敍刻介曰電層 52、襯墊層100、基底10、部分的摻雜多晶石夕層34以及電容 介電層32，再去除剩餘的光阻層54以及介電層52 ,即形成淺 溝系巴緣開口 60，如圖六所示。 13 1289924 然後’如圖七所示，進行一高密度電漿化學氣相沈積 (high-density plasma chemical vapor deposition, HDPCVD) 製私’於基底10上沈積一高密度石夕氧oxide)層62，並 且填滿淺溝絕緣開口 60。再進行一化學機械研磨（chemicai mechanical polishing，CMP)製程，利用襯墊層1〇〇為研磨停 止層，使基底10表面平坦化。剩餘的襯墊層100被去除，然 後進行標準邏輯製程，以熱氧化方式於暴露出的基底1〇表面 上成長出新的閘極氧化層72，其厚度約為1〇至1〇〇埃。 如圖八所示’接著於閘極氧化層72上沈積多晶矽層，並以 習知黃光以及蝕刻製程將多晶矽層定義成閘極結構81、82、 83及84。然後再以閘極結構81、82、83及84為離子佈植遮 罩進行 P 型輕摻雜及極(p—type Hghtly doped drain/source， _冉為PLDD)102製程，完成側壁子的製作之後，再利用一適 當遮罩進行Pf源極/汲極1〇1重摻雜離子佈植，如此即完成電 晶體部分的邏輯製程。其中藉由控制閘極81下方之p通道可 以存取沬溝渠電容12〇之資料，而藉由控制閘極84下方之p 通道可以存取深溝渠電容140之資料。接著，於半導體基底 1〇 上沈積一層間介電層（inter layer dielectric，IL_， 其可以為硼矽玻璃、硼磷矽玻璃、二氧化矽等等。 14 1289924 最後，如圖九所示，接著利用黃光以及韻刻製程於層間介 電層90⑽成接觸開a(eQntac—呢），紐在接觸開口 内填入導電材質，例如鎮金屬’如此分別形成共用接觸插塞 (shareC〇ntaCt)201，其穿過位於深溝渠電容！20以及140之 多晶石夕電極34上方之絕緣層j 〇5而與深溝渠電容⑽以及⑽ 之多晶梦電極34電連接’以及位元線插塞2()2，其與p+源極/ 沒極101電連接。操作時，提供一閘極電壓予間極Μ，使間 極81下方之水平P通道開啟，並經位元線插塞2〇2輸入一位 兀線電壓^ P4祕/汲極m，同時經由插塞2G1輸入一負電 壓於多晶料極34 ’藉此在p _摻極⑽_2與埋入 式（buried)N1摻雜區25之間感應形成垂直p通道，在上述條 件下，電洞經由P+源極/汲極101、閘極81下方之水平p通道、 P型輕摻雜汲極⑽D)l〇2、垂直p通道，而到達埋入式N+換 雜區25。 以上所述僅為本發明之健實關，凡依本翻巾料利範圍 所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。 【圖式簡單說明】 15 1289924 圖式之簡單說明 圖一至圖九顯示依據本發明較佳實施例製作深溝渠式記憶 體元件的剖面示意圖。 圖式之符號說明 10 半導體基底 11 表面 12 襯氧化矽層 14 襯氮化矽層 15 深溝渠 16 深溝渠 20 N型井 21 砷矽玻璃 25 埋入式N+摻雜區 32電容介電層 34 摻雜多晶矽層 45 凹陷口 46 凹陷口 52 介電層 54 光阻層 55 開口 60 淺溝絕緣開口 62 高密度矽氧層 72 閘極氧化層 81 閘極 82 閘極 83 閘極 84 閘極 90 層間介電層 100 襯墊層 1289924 101 P+源極/汲極 102 P型輕摻雜汲極 105絕緣層 120深溝渠電容 140深溝渠電容 201共用接觸插塞 202位元線插塞BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a deep-deep-type semiconductor memory cell structure and a method of fabricating the same, and more particularly to a deep trench-type single-crystal random access memory. (1T-RAM) component and its method of manufacture. According to a preferred embodiment of the present invention, the deep trench single-crystal random access memory device is connected to the ion implantation well (impiantati〇n ion well) by an out diffusion well formed outside the trench capacitor. Thereby, a higher capacitance value (Cs) and a low leakage current characteristic are obtained. [Prior Art] The random access memory used in general computer systems can be divided into dynamic and static Ik machine access memory. The difference is that the dynamic random access memory uses only one transistor for one bit and needs to be periodically replenished. The power supply (refresh) is used to keep the recording in the war. The static random access memory is composed of 4 or 6 transistors (4T/6T). It does not need to periodically replenish the power supply. Fast, the price is also higher. The main memory in the computer is usually DRAM, and the cache memory is SRM. 1289924 With the advancement of technology, portable small electronic products such as mobile phones and personal digital assistants (PDAs) are becoming more and more popular among the public. These electronic products are limited by the battery and the volume required for high-density high-efficiency low voltage. The system is a single-chip embedded memory device, thus developing a single-crystal SRAM (UT-SRAM) component as known to those skilled in the art. This type of single-crystal static random access memory component differs from a conventional six-transistor SRAM in that it has a higher component density and better operational efficiency. More power-saving and simplified circuit design, and can be produced by pure logic (l〇gic) process or by embedded memory system. The single-crystal static random access memory (1T-SRAM) technology uses a flat capacitor to form a memory bit cell, which is similar to the standard six-electrode 81^^, but only accounts for about half of the die area, storage density. It is about four times higher than the standard SRAM. This is done by folding the capacitor into a groove or cavity etched into the ruthenium wafer at a nearly 90 degree angle, thereby reducing the size of the storage unit. However, some changes must be made to the manufacturing process in order to build the storage unit: add a mask and add new surnames and implant steps to create a cavity that can be embedded in a 2/3 volume of the capacitor. For the related W technology, please refer to the "Method and apparatus for 1T-SRAM compatible 1289924 memory" and the US patent of the US Patent No. 6028084, which is owned by MoSys Corporation (Monolithic System Technology). The DRAM cell having a capacitor structure partially in a cavity and method for operating the same. However, the conventional single crystal static random access memory (1T - even with the advanced process technology, its unit memory cell area still accounts for 0.5~0.6" m2, and the process cost is still higher than the standard logic process. About 4%. In addition, the conventional single-crystal static random access memory (1T-S^) only adds a small amount of capacitance (about 3~7fF). Moreover, the insulation between adjacent two capacitors is poor. It is also a major drawback of the conventional single crystal static random access memory (1T-sram). It can be seen that there is still room for further improvement in the single-crystal static random access memory (IT-SRAM) technology. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a deep trench single crystal static random access memory (IT-SRAM) device and method of fabricating the same. According to a preferred embodiment of the present invention, the present invention discloses a The deep trench capacitor memory cell structure comprises a -first-first conductivity sductivity 1289924 type semiconductor substrate having a main surface; a second conductivity type ion implantation well a well junction depth is disposed on the main surface of the semiconductor substrate; a gate dielectric layer is disposed on the ion implantation well; and a gate is disposed on the gate dielectric layer a first conductive type heavily doped region disposed in the ion implantation well on the gate side; a first conductive type lightly doped region disposed at the gate The ion-implanting well of the opposite side of the first conductive type heavily doped region; and the deep trench capacitor, the surface of the money contact is formed in the semiconductor substrate and penetrates deeper than the well junction depth of the ion implanted well Up to a predetermined depth, for example, 3 to 5 microns deep, wherein the deep trench capacitor comprises an ion diffusion well (i〇n QUt diffusiQn weu) formed adjacent to the trench electric valley and connected to the ion implantation well Connecting ((5)-shaped), wherein the deep trench capacitor further comprises a polysilicon electrode, which is lightly coupled to the first conductive type by a capacitor dielectric layer and a trench ΐορ insulation layer Doped region, the ion Plant and a well diffusion Hai outer electrically isolated from the well. According to a preferred embodiment of the present invention, a deep trench type single crystal static random access memory (SIL) 7L device utilizes an ion diffusion well formed in a lower portion of the trench capacitor and an ion implantation well on the surface of the substrate.丨, ie, the Beton connection, which results in a higher capacitance value (Cs) and a low leakage current (1289924). In order to enable the review committee to learn more about the features and technologies of the present invention, refer to the following related text. DETAILED DESCRIPTION OF THE INVENTION AND EMBODIMENT(S) The present invention is not intended to limit the invention. [Embodiment] First, please refer to FIG. 9, the present invention relates to a deep trench capacitor memory. The body unit structure 'includes a first conductivity type semiconductor substrate 10 having a main surface 11; a second conductivity type ion implantation well 20 having a well junction depth (well junction depth) is disposed on the main surface 11 of the semiconductor substrate 1; a gate dielectric layer 72 is disposed on the ion implantation well 20; a gate 81, The first conductive type heavily doped region 101 is disposed in the ion implantation well 2 — on the side of the gate 81; a first conductivity type lightly doped a lightly doped region 1〇2 disposed in the ion implantation well 20 on the opposite side of the gate 81 from the first conductivity type heavy exchange region 101; and a deep trench capacitor 120 perpendicular to the main surface π Formed in the semiconductor substrate 10 and deeper down the depth of the well junction of the ion implantation well 20 to a predetermined depth, for example 3 to 5 microns deep, wherein the deep trench capacitor 12〇1289924 comprises an ion diffusion well (iQD) Qit diffusion well) 25, which is formed in the lower part of the 12th raft of the rafting wood electricity valley, and is connected to the ion implantation well 2m (m6rge), wherein the deep trench capacitor 120 further comprises a polycrystalline yttrium electrode 34, A capacitor dielectric layer 32 and a trench: a trench top insulation layer 105 and the first conductive light doped region 102, the ion implant well 20, and the outer diffusion well 25 electrical isolation. See Figure 1 to Figure 9, Figure 1 to 9 shows a schematic cross-sectional view of an advanced deep trench memory element in accordance with a preferred embodiment of the present invention. As shown in FIG. 1, a substrate 10, such as a P-type doped germanium substrate, is first formed therein. There is an N-type well 20. The depth of the well junction of the N-type well 20 is about 5·5 to 1.5 micrometers, preferably about 1 micrometer. Then, using a known technique, such as a lithographic process and dry etching, deep digging down the surface 11 of the substrate 10 through the N-well 2 to form a surface 11 deep from the p-type substrate 1 Two adjacent deep trenches 15 and 16 of about 3 to 5 microns (preferably 3.5 microns). The technique of excavating deep trenches on the substrate 1 is well known in the art, and it is possible to utilize photoresist and a liner layer 100 deposited on the surface of the crucible substrate, such as an oxidized oxidized layer 12 and a delaminated layer 14, It is carried out as a residual mask 'in conjunction with a reactive ion etching (RIE) process. 1289924 The picker', as shown in Figure 2, performs high-concentration N-replacement on the surface sidewalls and bottom of the m-channels 15 and 16 below the surface of the substrate 10, which is about 4000 to 6000 angstroms. Gxsejiic si 1 icate glass, ASG), followed by thermal drive-in, or direct deposition of a high-density doped polycrystalline layer. According to a preferred embodiment of the present invention, a layer of Shishen Shixi glass 21 is deposited on the sidewalls and bottom of the deep trenches 15 and 16, and then a photoresist layer (not shown) is filled in the deep trenches 15 and 16. The photoresist layer is inscribed to a predetermined depth, for example, a depth of about 4,000 to 6,000 angstroms below the surface of the substrate 10, and the arsenic bismuth glass 21 not covered by the photoresist layer is removed, and after the photoresist layer is removed, the heat is removed. The drive-in process diffuses the N-type dopant from the Shishen Shixi glass 21 into the substrate 1〇 in the deep trenches 15 and 16 in contact with the Xieshishi glass 21, thereby forming an ion out-diffusion well (ion out diffusion well). Or referred to as a buried N+ doped region 25. Finally, the arsenic bismuth glass 21 is removed. As described above, in other preferred embodiments of the present invention, the arsenic bismuth glass 21 may also be replaced by a heavily doped polysilicon layer. In this case, after the buried doping region 25 is formed, the heavily doped may not be used. The polysilicon layer is removed and left in the deep trenches 15 and 16. As can be seen particularly from the figure, the buried N+ doped region 25 formed in the lower portion of the deep trenches 5 and 16 of the present invention is connected to the N-type well 20. As shown in FIG. 3, an electric layer 32 is formed on the backing layer 1〇〇 and the inner walls 12 1289924 of the deep trenches 15 and 16 , for example, oxidized stone _ _ 氮化 夕 — 氧化 氧化 氧化 _ _ _ _ dielectric layer However, it is not limited to this. Then, the n-doped polysilicon layer 34 is filled in the deep trenches 15 and 16. As shown in Fig. 4, the polysilicon layer is doped and the polysilicon layer is 10% to the deep trench and 16 is lower than the substrate 10 The predetermined depth under the surface, for example, 100 to 400 angstroms, preferably 200 to 3 GG angstroms. Then, the exposed capacitance is removed by wet etching; the enamel layer 32 is sagged at the dam ditch 15 and 16 Mouth milk and station. ^ At this point, the fabrication of the deep trench capacitors 12〇 and 14〇 is completed. As shown in Fig. 5, the logic shallow trench insulation module (logic STI module) process is followed. According to the preferred embodiment of the present invention For example, a dielectric layer 52 is first deposited on the substrate, such as b〇r〇silicate bsg, which fills the recesses 45 and 46. Then, the yellow layer is formed on the dielectric layer 52, and the photoresist is blocked. Layer 54' has an opening 55 defining a shallow trench isolation region. In other φ embodiments, dielectric layer 52 There may be a layer of anti-reflection layer between the photoresist layer 54 and the like, but it is not the charm of the present invention. Then, the photoresist layer % and the dielectric layer are weep as an I-inscribed mask through the photoresist layer 54. The opening 55 etches down the dielectric layer 52, the liner layer 100, the substrate 10, a portion of the doped polysilicon layer 34, and the capacitor dielectric layer 32, and then removes the remaining photoresist layer 54 and the dielectric layer. 52, that is, the shallow groove system edge opening 60 is formed, as shown in Fig. 6. 13 1289924 Then, as shown in Fig. 7, a high-density plasma chemical vapor deposition (HDPCVD) system is performed. A layer 62 of high density sulphur oxide is deposited on the substrate 10 and fills the shallow trench isolation opening 60. Further, a chemicai mechanical polishing (CMP) process is carried out, and the surface of the substrate 10 is planarized by using the liner layer 1 as a polishing stop layer. The remaining liner layer 100 is removed and then subjected to a standard logic process to thermally grow a new gate oxide layer 72 on the exposed substrate surface having a thickness of about 1 Å to 1 Å. As shown in Fig. 8, a polysilicon layer is deposited on the gate oxide layer 72, and the polysilicon layer is defined as gate structures 81, 82, 83 and 84 by conventional yellow light and etching processes. Then, the gate structures 81, 82, 83, and 84 are used as ion implantation masks to perform P-type light doping and pole (p-type Hghtly doped drain/source, _冉 is PLDD) 102 processes to complete the fabrication of the sidewalls. Thereafter, the Pf source/drain 1〇1 heavily doped ion implantation is performed using a suitable mask, thus completing the logic process of the transistor portion. The data of the trench capacitor 12 can be accessed by controlling the p channel under the gate 81, and the data of the deep trench capacitor 140 can be accessed by controlling the p channel below the gate 84. Next, an inter-layer dielectric layer (IL_) may be deposited on the semiconductor substrate 1 ,, which may be borosilicate glass, borophosphon glass, cerium oxide, etc. 14 1289924 Finally, as shown in FIG. The yellow light and the rhyme process are used to form a contact (aQntac-?) in the interlayer dielectric layer 90(10), and the contact is filled with a conductive material, such as a town metal, to form a shared contact plug (shareC〇ntaCt) 201, respectively. , which is electrically connected to the deep trench capacitors (10) and the polycrystalline dream electrodes 34 of the deep trench capacitors (10) and the bit line plugs 2 through the insulating layers j 〇 5 located above the deep trench capacitors 20 and 140. () 2, which is electrically connected to the p+ source/nopole 101. During operation, a gate voltage is applied to the interpole Μ, so that the horizontal P channel below the interpole 81 is turned on, and the bit line plug 2 〇 2 Input a 兀 line voltage ^ P4 secret / 汲 pole m, while inputting a negative voltage to the polycrystalline material electrode 34 ' via the plug 2G1, thereby in the p _ dopant (10)_2 and the buried N1 doping region 25 Inductively forms a vertical p-channel, and under the above conditions, the hole passes through the P+ source/drain 101 The horizontal p-channel below the gate 81, the P-type lightly doped drain (10) D) l2, the vertical p-channel, and reach the buried N+ replacement region 25. The above is only the practicality of the present invention, and all the equivalent changes and modifications made according to the scope of the present invention should be covered by the patent of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS 15 1289924 BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 9 show schematic cross-sectional views of a deep trench memory device in accordance with a preferred embodiment of the present invention. Symbol of the diagram 10 semiconductor substrate 11 surface 12 lining yttrium oxide layer 14 lining tantalum nitride layer 15 deep trench 16 deep trench 20 N-well 21 arsenic bismuth glass 25 buried N + doped region 32 capacitor dielectric layer 34 doped Heterogeneous polysilicon layer 45 Defects 46 Depressions 52 Dielectric layer 54 Photoresist layer 55 Opening 60 Shallow trench insulation opening 62 High density silicon oxide layer 72 Gate oxide layer 81 Gate 82 Gate 83 Gate 84 Gate 90 Interlayer Electrical layer 100 liner layer 1289924 101 P+ source/drain 102 P-type lightly doped drain 105 insulation layer 120 deep trench capacitor 140 deep trench capacitor 201 shared contact plug 202 bit line plug
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