TWI289885B - Method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process and etching method - Google Patents

Abstract

A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method comprises performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.

Description

1289885 9

I. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device process, and more particularly to the removal of a self-aligned metal telluride layer in a semiconductor device process. [Prior Art] The size of a semiconductor device is drastically reduced compared to several decades ago. Currently, manufacturers have been able to manufacture semiconductor devices with line widths of 0·35, 9 〇 nm, or even 65 nm or less. As the size shrinks, semiconductor manufacturing methods often need to be improved. • The _M0S device requires more speed, both using polysilicon as the gate, and the method 'causes many problems, such as high gate resistance, depletion of polysilicon, and Channel area. Therefore, a method including a metal gate/high dielectric gate dielectric layer has been proposed to reduce the polycrystalline lithotripsy effect and also to provide a lower thermal budget, but it has disadvantages. Figs. 1 to 5 are cross-sectional views showing a manufacturing process for manufacturing a m〇s electromorph 10 having a metal gate in a known manufacturing method. Referring to FIG. j, a polycrystalline stone inter-pole U is formed on a semiconductor substrate, the semiconductor substrate includes a tree layer 16, and a surface source extension 17 and a shallow junction drain extension 19 are formed on both sides of the gate 12 In the layer 16, the channel 22 is |^. Then, a spacer % is formed on the sidewalls of the polycrystalline 1:12, and source/drain regions 18 and 2 are formed in the layer 16 of the polycrystalline intertidal pole 12, and The shallow junction source extension 17 is adjacent to the shallow junction no pole extension 19. The gate 12 is separated from the channel ^ ! 289885 I by a gate dielectric layer 14 . A spacer layer 30, typically of hafnium oxide, may be disposed between the spacer 32 and the sidewall of the gate 12. Semiconductor 〇 8 Electric The exposed germanium surface of the body element 10, including the drain/source region 18/20 surface and the polysilicon 顶部 top of the gate 12, forms a self-aligned metal germanide layer 42. Thereafter, a nitriding layer 46 is formed overlying the entire semiconductor region, including the source/drain regions and the shallow source source extensions 17 and the shallow junction drain extensions 19, and the polysilicon gates 12 are also covered. After depositing the tantalum nitride cap layer 46, a dielectric layer 48 is subsequently deposited, and the tantalum nitride cap layer 46 is typically between about 300 and about 1000 angstroms thick, and can be chemically vapor deposited by plasma ( Formed by PECVD). Next, referring to FIG. 2, the tantalum nitride cap layer 46 and the dielectric layer 48 are ground by a CMP process until the top of the polysilicon gate 12 is exposed. The gate is over-grinded so that the top of the polysilicon gate 12 is completely exposed. Next, refer to the 3rd ffl, using chlorine for the electrical reactive ion etch, or performing the conventional application of the chemical wet polycrystalline slab to form an opening (i.e., the groove) 54. Referring to FIG. 4, the barrier metal layer may be formed on the sidewall of the recess 54 and the surface of the dielectric layer 48, the nitride blanket layer 46, the spacer %, and the surface layer 3, and then deposited. A metal layer 58 is filled to fill the trench and deposited onto the barrier metal layer 56. Finally, referring to Fig. 5, the excess metal layer % is ground and removed, leaving a portion of the gate forming a M〇s transistor 1〇 having a metal gate. The above manufacturing method includes an integrated process of a metal gate replacement process, and the integration process 1289885 i

I includes the following: chemical mechanical polishing of the inner dielectric layer (ILDCMP) after the construction of the transistor, removal of the metallization layer and the polysilicon plug, deposition of the metal layer, and metal layer CMP. However, it is difficult to remove the metallazine layer by the CMP process. The ftjlly silidded polysilicon gate (FUSI gate) is another option for metal gates because of the relatively simple integration process. Referring to Figure 2, the dielectric layer above the gate 12 and the tantalum cap layer 46 are polished by the CMP process until the top of the polycrystalline silicon gate 12 is exposed. Then, refer to Fig. 6 to deposit a metal layer 5〇 on the exposed portion of the Shishi gate 12, the nitride layer, the spacer %, the spacer 30, and the dielectric layer 48. The metal layer % thickness is typically less than about 1 angstrom, and in some instances, may be between about 1 angstrom and about 1 angstrom. The metal layer 50 may also be a plurality of layers such as Ti_, c〇/TiN, or c〇/Ti/TiN or the like. Heat treatment is performed on the substrate having the metal layer 50 to convert the polycrystalline silicon gate into a metallization gate 52. The heat treatment process can be carried out in two steps, that is, the first step is performed at about 400 to about 60 (the thermal process is performed at rc, and the second step is performed at about 800 to about 丨. Next, the unreacted residual metal is removed to obtain the contact 8 transistor b as shown in Fig. 7, which has a fully deuterated interpole. In the above-described FUSI metal gate integration process manufacturing method, via direct ILD The CMP step removes the NlSi polycrystalline lithic compound and then performs the complete crystallization of the crystallization of the smectite, to 1288885

I forms a NiSi metal gate. However, this method also has the difficulty of removing the metal and the ruthenium layer by the CMp process. Directly using the CMP process, it is difficult to control the grinding of the Nisi polycrystalline telluride layer, so it is difficult to obtain a good uniform removal result. Therefore, there is still a need for a preferred method for removing a metal telluride layer in a semiconductor process. SUMMARY OF THE INVENTION The object of the present invention is to provide a method for removing a metallization layer on a gate electrode in a semiconductor process, which can effectively and uniformly remove the metal germanide layer on the gate for subsequent processing. The invention also provides a wet side method for effective and uniform removal of the metal telluride layer. • In another embodiment in accordance with the invention, a dry remnant method is also provided to effectively and uniformly remove the metallurgical layer. In the method for removing a metal-lithium layer on a gate in a semiconductor process according to the present invention, the gate is on the semiconductor substrate, and the upper surface of the gate is covered with a metal-lithium gate and a metal-lithium layer. Each of the sidewalls formed together is provided with a spacer layer of a nitride layer covering the metal-lithium layer, a spacer, and a semiconductor substrate, and the dielectric layer covers the Ni-na cover layer. 1289885

I » The method of the metallization layer comprises the following steps: first, performing a chemical mechanical polishing process to polish the dielectric layer, the iUxlUb7 cap layer is a polishing stop layer, and exposing the gate, the nitrogen (10) cap layer above the pole; The exposed nitrogen cap layer is removed to expose the metal-lithium layer on the gate electrode; finally, a -first-etch process is performed to remove the metal telluride layer on the gate. The wet sculpt method according to the present invention comprises wet etching a metal slab layer using a side liquid, the side liquid comprising hydrogen fluoride (HF), ammonium fluoride _4F, and ethylene glycol. At least one of the group consisting of propylene glycol and water. The dry side method according to the present invention comprises the use of a side-side pair-metal lithium layer for dry remnant, the surname gas comprising argon, at least one selected from the group consisting of hydrogen and chlorine, and carbon monoxide. It is conventional to remove the metal lithium layer by the CMp method, and it is not easy to have a good grinding result for the metallization layer. When the method of the present invention is applied to remove the metal telluride layer on the gate, since the etching selectivity is good, effective and uniform removal can be obtained for subsequent processes, so that a semiconductor of better quality can be obtained. Device. [Embodiment] The present invention is a semi-conductive ", for example, the fabrication of a ship 08, a PMOS transistor element or a CMOS device, particularly a method of removing a metal lithium layer on a gate. 1289885: Referring to FIG. 8 to FIG. 3, there is shown a cross-sectional view of a method for fabricating a turn-off transistor element 4 having a closed-cell polarity according to a preferred embodiment of the present invention, the same symbols being used only or in part. Said. It should be noted that the drawings are for illustrative purposes only and are not mapped to the original dimensions. As shown in Fig. 8, 'preparation of a semiconductor substrate' generally includes a sapphire layer. The front = two conductor base can be the bottom of the record or the Wei can be like the Yang, the soil bottom. An electrode is defined on the semiconductor substrate, for example - a closed pole 12. A shallow junction source extension n and a shallow junction no-pole extension β may be formed in the Shixi layer I6, the shallow junction source extension 17 and the shallow junction drain extension I9--the channel 22. An inter-electrode dielectric layer 14 can be formed on the channel 22, with __12 and channel 22. The interpole 12 typically contains a polycrystalline donor. The dielectric layer 14 may be formed of oxidized oxide or may be formed by a thermal oxidation method or a oxidized oxide/nitridinated composite film, and may be formed by a thermal oxidation method followed by a thermal nitridation method. However, in another embodiment of the present invention, the dielectric layer 14 is composed of a high-intermediate (tetra) material which can be formed by a chemical vapor deposition method to a thickness of from about % Å to about 2 (8 Å). As a material having a high dielectric constant, it is possible to form a tantalum nitride spacer 32 on the sidewall of the gate 12 after the Zr〇2, the leg 2, the in〇2, the 2, and the Ta〇2 slave. There may be another % layer between the # nitride and the nitride spacers 32. The cushion layer may be made of oxidized stone. The liner layer 3 is usually L-shaped and has a thickness of about 3 〇 to m. Between the angstroms, the spacer layer 30 may have an offset spacer peak (4), which is known to those skilled in the art and therefore not shown. 1289885 As shown in Fig. 9, after forming the tantalum nitride spacer 32 Further performing an 'ion implantation process, implanting N-type dopant species such as arsenic, antimony or structure into the ruthenium layer 16' or implanting a P-type dopant species such as boron into the sap layer 16 Thereby, the source region 18 of the NMOS or PMOS device 40 and the non-polar region 20 are formed. After completing the doping of the gateless source, the semiconductor substrate can usually be subjected to a tempering or activation dopant. The thermal process, which is also well known to those skilled in the art, will not be stated. _ As shown in Figure 10, a substance is formed on the gate 12, the exposed source region 18, and the exposed drain region 20. a layer, such as a metal lithium layer (four) tal silicide la (four) 42. Using automatic alignment of metal telluride (sdf-aligned silidde, from let Forming a metal telluride layer; that is, after forming the source/drain region, a metal layer is formed over the source/drain region and the gate structure by sputtering or electroplating, and then a rapid temperature is applied The process (RTP) causes the metal to react with the gate structure and the germanium in the source/drain region to form a metal telluride. The metal halide can be exemplified by a nickel ruthenium compound or a cobalt ruthenium compound, such as nickel hydride (NiSi). Or cobalt telluride ((: 〇 & 2). The RTp temperature can be between 7 〇〇 C and 1 〇〇〇 c. After forming the self-aligned metal dream layer, the spacers 32 can be removed or retained as needed. Next, as shown in FIG. 11, a tantalum nitride cap layer 46 is further deposited on the semiconductor substrate, wherein the tantalum nitride cap layer 46 covers the metal telluride layer 42 and the tantalum nitride spacer 32, and the thickness thereof is usually The thickness of the nitride layer is 46. The purpose of depositing the nitride cap layer 46 is to make the subsequent contact hole etching have a significant etching end point, that is, 12 1289885 is used as the _stop layer. Money_stretched cap layer 46' to form a strained structure in the source region of the lower layer ^Into the channel a: charge relocation. In the deposition - 6 reading, _ (10) Γ ": Wei layer, etc. can also be high dielectric materials 'such as multilayer metal oxides or p_kites. Usually dielectric layer 48 It is much thicker than the nitrogen capping layer 46. The thickness A from the top of the dielectric layer 48 to the nitride nitride 46 above the opening 12 is the thickness of the method of the present invention to be removed by the CMP process. See Figure 12, It shows the structure of the structure in Fig. u after the portion of the dielectric layer 48 is removed by the process of (10). The nitride light layer 46 can be used as the polishing stop layer of (10), and the nitrogen cut cap layer 46 is removed in a side manner. The method may be to wet etch the exposed tantalum nitride cap layer using a hot phosphoric acid solution or to remove the tantalum nitride cap layer 46 directly in a cMp manner. Figure 13 shows the structure of the metal telluride layer 42 over the gate after the tantalum nitride cap layer 46 is removed. • Next, the metallurgical layer 42 above the gate 12 is removed in a residual manner. The metal-lithium layer 42 can be wet-etched using an etching solution, and the surname includes fluorene fluoride (HF), ammonium fluoride (NHJ), and a group consisting of ethylene glycol and propylene glycol. At least one solution in water. Hydrogen fluoride (HF) in the etching solution: ammonium fluoride (nh4f): The weight of at least one selected from the group consisting of ethylene glycol and propylene glycol is preferably from 〇.5 to 6:15 to 25:30 to 40. In one embodiment of the invention, the etchant comprises about 3.5% by weight of TM, about 20% by weight of NH4F, and about 35% by weight of ethylene glycol (or propylene glycol), the balance being water. At 25 ° C, the etch rate of NiSi and CoSi2 13 1289885 is 6G.5 and 5G.4 Å/min, respectively, while the ratios of oxygen cut, polycrystalline shi, and nitrite are only It is 4.77, (10), and 丨4 w minutes, so there is a high selection ratio, which can effectively remove the deletion and shouting, leaving the oxidized stone eve, polycrystalline stone eve, gasification stone eve structure. For _σ lion (four), make CMP __ except the brain and tons of layers. The metallurgical layer 42 above the gate can also be removed using a dry money engraving. The gas can be dry-recharged using the side gas to the metal-lithium layer 42 above the gate. The gas of the surname includes any of argon (Ar), hydrogen (h2), and chlorine (cl2), and carbon monoxide ( C0) In this dry-type surrogate, it is presumed that the metal components of the carbon monoxide and the metal-lithium layer are derived from earixmyls, such as Ni(CQ)4. Fj2 removes the carbon film produced by chemical sputtering or the carbon film deposited by the precursor. & ion bombardment can increase the removal of miscellaneous items. The flow rate of argon gas, chlorine gas and carbon monoxide in the side button is preferably 5 to 15 ··15 to 25 ·· 5 to 15, or argon gas · chlorine gas · carbon monoxide flow rate is preferably 10 to 2 〇·· 2〇 to 3〇·· 5 to 15. In the other-frequency implementation of the present invention, a blessing body prescription is c〇·· CI2 · Ar is 1〇〇seem · 200 seem ·· 1〇〇seem ' using a TCP9400 model machine, pressure 10 mTorr Ear (mTorr), temperature 75 γ, power above 5 watts (toppower, ΤΡ), and power below 50 watts (b〇ttomp〇wer, Βρ). In the other specific embodiment of the present invention, the side gas prescription used is CC) ·· Η2 ·· & 100 seem: 250 seem: 150 seem, using a DRM85 model machine, pressure 30 mTorr (mTorr), temperature 6 (rc, 1 watt power) can be effective

14 1289885 The metal telluride layer 42 is removed. The above-mentioned metal-lithium layer 42 may be a metal-grain layer obtained by a self-aligned metal method in a layer or a polycrystalline layer. After removing the metallization layer using the above method, the resulting structure is as shown in FIG. Next, you can use the plasmon anti-ship ion side _) Qian Wet Μ 卿 赖 赖 ^ (9), as shown in Figure 15. A barrier layer is formed on the sidewalls of the opening 60 and the surface of the dielectric layer 48. φ is then deposited with a metal layer 64' to fill the opening 6'' as shown in FIG. Finally, the metal layer 64 on the dielectric layer 48 is removed to obtain a MOS transistor 40 having a metal gate as shown in Fig. 17. If the FUSI _ is to be fabricated, reference is made to the structure of the 14th®, in which the metal lithium layer 42 has been removed using the method of the present invention to expose the gate 12 of the polycrystalline stone. Next, please refer to Fig. 18 to deposit a metal layer 66 on the polycrystalline sprue 12 and the vaporized capping layer 46, the thickness of which may be less than 1 〇〇〇 or about 500 to about 约 约between. The material of the metal layer 66 may be a multilayer material such as Ni, Co, Ti, Ti/TiN, Co/TiN, or Co/Ti/TiN or the like. The semiconductor substrate is heat-treated to react the polycrystalline silicon with the metal to form a metal halide to remove the unreacted metal to obtain a M?s transistor 70 having a fully metal polycrystalline telluride gate, as shown in FIG. In the conventional metal gate process or the full metal germanium gate process, the CMP process is used to remove the metal telluride layer on the original gate. The present invention uses the etch 15 1289885 J method to remove the polycrystalline stone gate in the process. The metal-lithium layer on the pole has good removal effect due to its excellent residual selectivity, so that the metal gate process or the complete metal telluride gate process can be carried out smoothly. The above description is only the preferred embodiment of the present invention, and all the changes and modifications made in the scope of the patent application of the present invention are within the scope of the present invention.

[Simple description of the diagram] The cross section of the method of the electromorphic component

The first to fifth _ show the semiconductor MOS diagram with the metal gate

Mesh etch < Flat Conductor MOS Nos. 6 to 7 show a schematic cross-sectional view of a conventional method of fabricating a crystal element. ===17Saki is a schematic cross-sectional view of a method with a metal gate semiconductor MOS device. Figs. 18 to 19 are cross-sectional views showing a method for removing the components of the present invention. Dispatch ~ 16 1289885 [Main component symbol description] 10, 15, 40, 70 MOS transistor. 12 gate 14 gate dielectric layer 16 chopped layer 17, 19 shallow junction source extension 18, 20 source / Nom region 22 channel 30 liner layer 32 spacer 42 metal vaporization layer 46 tantalum nitride cap layer 48 dielectric layer 50 metal layer 52 metal germanium gate electrode 54 opening 56 barrier metal layer 58 metal layer 60 opening 62 barrier Layer 64 metal layer 66 metal layer A thickness

17

Claims (1)

1289885 X. Patent Application Range: 1. A method for removing a metal telluride layer on a gate in a semiconductor process, the gate being on a semiconductor substrate, the upper surface of the gate being covered with a metal telluride layer, the gate a sidewall is formed on each of the sidewalls formed with the metal telluride layer, a layer of tantalum nitride capping covers the metal halide layer, the spacers, and the semiconductor substrate, and a dielectric layer covers the nitrogen The enamel cap layer, the method of removing the metal lithium layer on the gate of the semiconductor process comprises: φ performing a chemical mechanical polishing process to polish the dielectric layer and terminating the yttrium nitride capping layer And exposing the tantalum nitride cap layer over the gate; removing the exposed tantalum nitride cap layer to expose the metal telluride layer on the gate; and • performing a first etching process to remove the gate electrode a metal telluride layer. 2. The method of claim 1, wherein the first etching process comprises: wet etching a metal telluride layer over the gate using an etchant, the etchant comprising hydrogen fluoride (HF) , ammonium fluoride (NHj), selected from the group consisting of ethylene glycol and propylene glycol • at least one of the group, and water. 3. The method of claim 2, wherein the etchant contains hydrogen fluoride (HF) · ammonium fluoride (NHJ): a weight ratio selected from at least one of a group consisting of ethylene glycol and propylene glycol It is 0.5 to 6: 15 to 25: 30 to 40. 4. The method of claim 3, wherein the etchant contains hydrogen fluoride (HF), ammonium fluoride (NI^F), and at least 1289885 selected from the group consisting of ethylene glycol and propylene glycol. The weight ratio is 3.5:20:35. 5. The method described in the third paragraph of the patent application uses a metal above the gas paste electrode. The process includes: The milk body includes at least one of the group consisting of hydrogen and thieves. . Wherein the etching gas is argon: 20 to 30: 5 to 15. 6. The method described in item 5 of the patent application scope is that the flow ratio of hydrogen·· carbon monoxide is 1〇 to 2〇: = If the method described in item 6 is applied, the chlorine in the coffee should be thrown in the coffee: hydrogen·· The flow ratio of carbon monoxide is 15 : 25 : 1 〇. 8. The method of claim 5, wherein the chlorine gas in the side gas: chlorine gas: carbon monoxide flow ratio is 5 to 15: 15 to 25: 5 to 15. 9. The method of claim 8, wherein the chlorine gas in the side gas: chlorine gas: carbon monoxide flow ratio is 10:20:1〇. 10. The method of claim 1, wherein the metal telluride layer comprises at least one selected from the group consisting of nickel dreaming compound and starting stone compound. The method of claim 1, wherein the removing the exposed tantalum nitride cap layer comprises: 19 1289885 wet-etching the exposed nitride layer with a hot phosphoric acid solution. The method of claim 1, wherein the removing the exposed tantalum nitride cap layer comprises: removing the scaled cash cut cap layer by the Wei Xue thief grinding method. 13. The method of claim 1, wherein the dielectric layer comprises cerium oxide, Zr 〇 2, HfO 2 , In 〇 2, La 〇 2, or Ta 〇 2 . 14. The method of claim i, wherein a gate oxide layer is further disposed between the gate and the semiconductor substrate. 20 1 15· A wet etching method comprising: wet-etching a metal-lithium layer using a money engraving solution comprising hydrogenated hydrogen (HF), ammonium fluoride (nh4f), selected from The group consisting of ethylene glycol and propylene glycol is less than one, and water. The method of wet etching according to claim 15, wherein the hydrogen fluoride (HF) in the etching solution: ammonium fluoride (NH^F): selected from the group consisting of ethylene glycol and propylene glycol The weight ratio of at least one of 〇·5 to 6: 15 to 25: 30 to 40. The wet etching method according to claim 16, wherein the vaporized hydrogen (HF) in the etching solution: ammonium fluoride (NHJ): selected from the group consisting of ethylene glycol and propylene glycol The weight ratio of at least one of them is 3.5:20:35. 1289885. The method of claim 1, wherein the metal telluride layer comprises nickel telluride or cobalt telluride. 19. A dry etching method comprising: dry-treating a gold-on-metallization layer comprising a argon gas, at least one selected from the group consisting of hydrogen and chlorine, and a rock oxide mountain 20 The dry etching method according to claim 19, wherein a flow ratio of argon gas to hydrogen gas to carbon monoxide in the gas is as wide as 15 minutes. : 20 to 30: 5 21 · The dry residual method described in the second paragraph of the patent application, • Argon gas in the gas: Hydrogen: The flow ratio of carbon monoxide is 15 · · · · · Medium, the etching • 10 〇 22. The method of dry-money engraving as described in claim 19 of the patent application ❿ Argon gas in gas: gas gas: carbon monoxide flow ratio is 5 to ^, the etching is 15. 15 to 25 · · 5 to 23 · If applied In the dry etching method described in claim 22, the flow ratio of argon gas: gas gas: carbon monoxide in the gas is 1 〇: wherein, the etching is 10 〇 24. dry etching as described in claim 19 The method, the telluride layer comprises nickel telluride or cobalt telluride. wherein the metal 21