!289881 九、發明說明： 【發明所屬之技術領域】 - 本發明之標的為一多層結構，包括一基材及一異質磊晶沉積在 、 該基材上之矽與鍺層（siGe層）’該SiGe層之晶格常數與基材之晶 格常數不同。沉積在此類型之SiGe層上之石夕係呈雙軸應變的 (biaxially strained)。因為應變石夕中電荷載子之移動率高於未應變 矽，對利用應變矽提升開關速率之電子元件感興趣者日益增多。 φ 【先前技術】 由矽及鍺之混合物組成、鍺含量為20至50%且儘可能完全鬆弛 之SiGe層尤其適合用來沉積應變矽。因為SiGe層之晶格常數大 於碎之晶格常數儿積在此類型層上之梦晶格會擴大，製造' 應 變矽層。 通常，石夕亦被用作沉積在其上面之鬆弛（relaxed)SiGe層之基 材。因為晶格常數不同，成長之異質磊晶層本身於一開始即已應 變。應變現象在逾越一-臨界層厚度後消失，而形成差排 _ (dislocations)。參差差排傾向於在一沿該成長層之成長方向的平面 • 持續。然而，螺紋差排(threading dislocations)亦形成作為參差差排 (misfit dislocations)之延伸。該等螺紋差排沿SiGe層成長方向而延 伸，盡遠地達該層之表面。若沉積之SiGe層在簡單熱處理（退火) 期間係呈鬆弛的，此現象更為嚴重。螺紋差排應儘可能地加以避 免，因其通常於沉積在該SiGe層上之層内持續且使整合於此種類 型之層内的電子元件之功能中斷。螺紋差排之堆集特別有害。另 一有關SiGe層品質之重要參數為表面粗糙度，其應儘量低。參差 5 1289881 差排產生應力場且導致在SiGe層成長期間成長率之局部差異及最 終之表面形貌，此為已知之交叉排線表面形貌，其同樣移轉至沉 積在該SiGe層上之層。此種交叉排線之測量係表面均方根粗糙 度，例如用原子力顯微儀(AFM)測得者。 ’ 已有發展減少螺紋差排密度之策略。一種可能的選擇係逐步或 持續提升SiGe層中之鍺濃度。另一方法係沉積該SiGe層在另一 具有高濃度之點缺陷之層上。參差差排則傾向於形成閉差排環， 其通過高濃度點缺陷之區域而不延伸入面向SiGe層表面之螺紋差 ^ 排。仍可達到該基材表面之螺紋差排之密度係至少lxio7螺紋差排 /平方公分的數量級，所以對適合於製造電子元件之材料而言，該 密度仍然太高。US2004/0067644A1公開一種方法，該方法可將螺 紋差排密度減至lxl〇5螺紋差排/平方公分以下。該方法實質上包 括SiGe層表面之蝕刻，同時熱處理鬆弛SiGe層（蝕刻退火法）。此 方式有利之副作用係表面粗糙度亦可減少。 【發明内容】 φ 本發明之目的係提供一多層結構及製造該多層結構之簡單方 法，其中該結構表面具有低粗糙度、低螺紋差排之密度及低螺紋 差排堆集之密度。 " 【實施方式】 本發明之標的係一多層結構，包括一基材及一異質磊晶沉積在 該基材上之矽與鍺層（SiGe層），該SiGe層之組成為SiNxGex且其 晶格常數與矽之晶格常數不同，該多層結構包括一薄界面層，該 層係沉積在該SiGe層上且具有Sii_yGey之組成，該薄界面層侷限 6 .1289881 螺紋差排，及至少另一沉積在該界面層上之層 該多層結構表面不同之處，在於一特 紋差排之堆集、及低粗輪度。該多層*構之4螺紋差棑及螺 面層，其侷限與下方SiGe層之界面處切^徵為-料鍺之界 义〈螺紋差排。妹 相當少 之螺紋差排到達該界面層及沉積於其上 ° 〈孩至少另一層的表面。 本發明之標的亦為一製造多層結構之 ▲ 驟：提供^異縣晶沉積在—基材上方法包括以下步 夕，、鍺層（SiGe層），其組 成為Sii-xGex且其晶格常數與矽之晶袼當 ’、 Ο289881 IX. Description of the Invention: [Technical Field of the Invention] - The object of the present invention is a multilayer structure comprising a substrate and a heterogeneous epitaxial deposition on the substrate and a germanium layer (siGe layer) 'The lattice constant of this SiGe layer is different from the lattice constant of the substrate. The Shixia system deposited on this type of SiGe layer is biaxially strained. Since the mobility of the charge carriers in the strained stone is higher than that of the unstrained enthalpy, there is an increasing interest in electronic components that use strain enthalpy to increase the switching rate. φ [Prior Art] A SiGe layer composed of a mixture of cerium and lanthanum and having a cerium content of 20 to 50% and being as completely relaxed as possible is particularly suitable for depositing strain enthalpy. Because the lattice constant of the SiGe layer is larger than the lattice constant of the fragment, the dream lattice on this type of layer will expand, and the manufacturing layer should be changed. Usually, Shi Xi is also used as a substrate for a relaxed SiGe layer deposited thereon. Because of the different lattice constants, the growing heterogeneous epitaxial layer itself has been changed from the beginning. The strain phenomenon disappears after crossing the one-critical layer thickness, forming a dislocation _ (dislocations). The staggered row tends to continue in a plane along the growth direction of the growing layer. However, threading dislocations also form an extension of misfit dislocations. The thread difference rows extend along the growth direction of the SiGe layer to the surface of the layer as far as possible. This phenomenon is more serious if the deposited SiGe layer is relaxed during a simple heat treatment (annealing). The difference in the number of threads should be avoided as much as possible, as it is usually sustained in the layer deposited on the SiGe layer and the function of the electronic components integrated in the layer of this type is interrupted. The stacking of thread gaps is particularly harmful. Another important parameter for the quality of the SiGe layer is the surface roughness, which should be as low as possible. The difference 5 1289881 differential discharge produces a stress field and results in a local variation in the growth rate during the growth of the SiGe layer and the final surface topography, which is a known cross-line surface topography that is also transferred to the SiGe layer. Floor. The measurement of such cross-hatching is the surface root mean square roughness, as measured by atomic force microscopy (AFM). There has been a strategy to reduce the density of thread gaps. One possible option is to gradually or continuously increase the germanium concentration in the SiGe layer. Another method is to deposit the SiGe layer on another layer having a high concentration of point defects. The staggered row tends to form a closed-loop, which passes through the region of the high-density point defect and does not extend into the thread difference row facing the surface of the SiGe layer. The density of the thread difference of the surface of the substrate is still at least lxio7 thread difference/square centimeter, so the density is still too high for materials suitable for the manufacture of electronic components. US 2004/0067644 A1 discloses a method which reduces the thread difference density to below 1 x 1 〇 5 thread difference/square centimeter. The method essentially involves etching the surface of the SiGe layer while heat treating the relaxed SiGe layer (etch anneal). The beneficial side effect of this method is that the surface roughness can also be reduced. SUMMARY OF THE INVENTION φ The object of the present invention is to provide a multilayer structure and a simple method of fabricating the same, wherein the surface of the structure has a low roughness, a low thread difference density, and a low thread difference stack density. <Embodiment] The subject matter of the present invention is a multilayer structure comprising a substrate and a germanium and germanium layer (SiGe layer) deposited on the substrate by heteroepitaxial epitaxy, the SiGe layer being composed of SiNxGex and The lattice constant is different from the lattice constant of 矽, the multilayer structure includes a thin interfacial layer deposited on the SiGe layer and having a composition of Sii_yGey, the thin interfacial layer confined 6.1289881 thread difference row, and at least another A layer deposited on the interfacial layer differs in the surface of the multi-layer structure in a stack of special streaks and a low coarseness. The multi-layer* structure of the 4-thread difference and the screw layer, the limitation of the interface with the lower SiGe layer is defined as the definition of the material. A relatively small number of thread gaps reach the interface layer and deposit on it. <Children at least another layer of surface. The subject matter of the present invention is also a method for fabricating a multilayer structure: providing a method for depositing a heterogeneous crystal on a substrate comprises the following steps: a germanium layer (SiGe layer) having a composition of Sii-xGex and a lattice constant thereof With 矽之晶当当', Ο
㊆數不同；及沉積一薄界面 層於該SiGe層上，其組成為Sii-yGev，兮墙與r y成溥界面層侷限螺紋差排； 及沉積至少另一層於該界面層上。 該siGe層可為應變的或鬆弛的。該SiGe層亦可具有縣錯之 怪定濃度suexm内鍺濃度隨著該層厚度逐步或持續地 增加之層（遞級層）係較佳地，且層表面濃度為silxGex。該指數X 較佳為〇 · 2至〇 · 5之値。 較佳地，該SiGe層係位於作為基材之矽之表面上，特佳為位於 -石夕之半導體晶圓上或具-♦層及-其下方之氧化層之絕緣體二 覆矽（SOI)之層結構上。 依照本發明，-薄界面層係沉積在該siGe層上，此界面層偈限 在該SiGe層界面處之螺紋差排，所以相較於該SiGe層表面之螺 紋排差密度，該多層結構之表面上之此等螺紋差排密度係大幅地 減低。該多層結構表面上之螺紋差排密度(TDD)最多為ΐ 5χΐ〇:螺 紋差排坪方好，㈣為慨差排/平方衫。螺纹差 排堆集密度(PuD)較佳為最多丨公分/平方公分。該多層結構之表面 7 1289881 粗糙度較佳為最多2A均方根（1微米X1微米量測窗口）。界面層之 厚度以2至3G奈米為佳。如果界面層之厚度在較佳厚度範圍下限 值之下或上限值之上，則對界面層表面之粗棱度具有負面效應， 所以亦對多層結構表面具有負面效應。該界面層具有恆定組成 Sii_yGey ’其中指數y較佳與指數χ相同。 為 >儿積該界面層’該SiGe層係暴露於含有氫、鹵化氫化合物、 石夕化合物及錯化合物之氣態混合物。較佳在一遙晶反應器内完成 此項工作。氣態化合物之濃度係經設定使得組成SiwGey材料在選 ^ 定之壓力及溫度條件下發生淨沉積。較佳地，該沉積係在900至 1100 C間之溫度及大氣壓力下或較低之壓力下進行。沉積速率係 大於0奈米/分鐘且以最多50奈米/分鐘較佳。 合適之矽化合物包括SiH4及氯矽烷，其中以二氯矽烷較佳。合 適之鍺化合物為氯鍺烷及其烷基衍生物，及GeH4。以GeH4、GeCl4 及CHsGeCl3特佳。在該氣體氛圍中用作沉積界面層之矽化合物與 錯化合物之比率，係經設定以使生長之界面層具有所欲組成 φ Sll-yGey。於該氣體氛圍中，較佳之鹵化氫化合物為HC1。另一方 . 面’函化氮化合物與矽化合物及鍺化合物之比率較佳在100 : 1至 1 · 1之犯圍内。由於表面螺紋差排之低密度及界面層表面之低粗 糙度’其特別適於_—作為直接位於該界面層表面之另一層之 應、變矽層。雖然如此，尚可事先沉積一或多層其他層，舉例言之， #沉積該L夕層之前’可沉積—鬆弛之異質蠢晶層（具有怪定之 SiNzGez組成）在該界面層上作為緩衝層 ;於此情況下，指數z最好 推疋與&數y同値。該緩衝層之鬆弛度較佳係大於9〇%。該緩衝 8 1289881 層之厚度較佳為1至2微米。 比較實施例： 在單-晶圓磊晶反應器内減壓下處理矽基材晶圓，進行下述步 驟： • 第一步：反應器裝料 第二步··在1120QC溫度下，於氫存在下熱處理該基材晶圓（H2 烘培) 第三步：在800至900°C溫度下，沉積具有增加之鍺含量（0至 C 20%)之SiGe層（遞級層） 第四步：沉積具有恆定鍺含量20%及1微米厚之矽與鍺之緩衝 層（恒定組成層） 第五步··在700°C溫度下，沉積18奈米厚之應變矽層 第六步：自反應器卸載形成之多層結構 實施例： 與比較實施例相同類型之其他基材晶圓，如比較實施例在相同 φ 之反應器内處理之，但有一區別： 第一至三步：如比較實施例 第四步：藉由引進氯化氫、二氯矽烷及鍺烷之混合物，在1050QC 溫度下沉積一具有恆定鍺含量為20%之矽及鍺之界面層 第五至七步：與比較實施例第四至六步相同 檢驗形成之多層結構： 界面層之檢驗係用橫截面電子顯微儀（X-TEM)為之。第一圖明確 顯示遞級層（具差排網絡）與恆定組成層間之界面層。該界面層之厚 9 1289881 度约為2至3奈米。第二圖顯示如何在界面層内吸收來自 SiGe層之差排。该差排存在於該siGe層與該界面層間之邊界氐位 内且未進一步成長為緩衝層。，平面 界面層之沉積降低螺紋差排密度（TDD)，尤其是此種差排之堆隹 密度(PixD)，且亦降低均方根粗糙度，故可免除交插排線(c⑺木 結構。在沉積該介面層之期間，表面形態會因廣泛範圍内加工條 件之改變而受到影響。 、 比較實施例 ——---- 實施例 TDD/公分 4χ105 1.3χΐ〇4 PuD/公分a 18 1.0 RMS40微米χ40微米 6·5奈米 1.6奈米 RMS 1微米X 1微米 0.42奈米 0.14奈米 【圖式簡單說明】 第一圖顯示遞級層（具差排網絡）與恨定組成層間之界面層。界面 層之厚度約為2至3奈米。 第一圖顯示如何在界面層内吸收來自較低位SiGe層之差排。該 差排存在於该SiGe層與界面層間之邊界平面内並未進一步成長為 緩衝層。 【主要元件符號說明】The seven numbers are different; and a thin interfacial layer is deposited on the SiGe layer, the composition of which is Sii-yGev, the interfacial layer of the crucible wall and the r y interfacial layer are arranged with a difference in the thread; and at least another layer is deposited on the interfacial layer. The siGe layer can be strained or relaxed. The SiGe layer may also have a layer having a gradual or continuous increase in the concentration of the suexm in the gradual concentration of the layer, and the surface concentration of the layer is silxGex. The index X is preferably between 〇 2 and 〇 · 5. Preferably, the SiGe layer is located on the surface of the substrate as a substrate, particularly preferably on the semiconductor wafer of the Shi Xi, or the insulator layer (SOI) of the oxide layer under the layer - and below - The structure of the layer. According to the present invention, a thin interfacial layer is deposited on the siGe layer, and the interfacial layer is limited to the difference in the thread at the interface of the SiGe layer, so the multilayer structure is compared to the thread displacement density of the surface of the SiGe layer. The difference in the discharge density of these threads on the surface is greatly reduced. The thread difference density (TDD) on the surface of the multi-layer structure is at most ΐ 5χΐ〇: the swarf difference is good, and (4) is the difference/square. The thread difference packing density (PuD) is preferably at most 丨 cm/cm 2 . The surface of the multilayer structure 7 1289881 roughness is preferably up to 2A root mean square (1 micron X1 micron measurement window). The thickness of the interface layer is preferably 2 to 3G nanometers. If the thickness of the interface layer is below or above the lower limit of the preferred thickness range, it has a negative effect on the coarseness of the surface of the interface layer, and therefore has a negative effect on the surface of the multilayer structure. The interfacial layer has a constant composition Sii_yGey ' wherein the index y is preferably the same as the index χ. The interface layer is > the SiGe layer is exposed to a gaseous mixture containing hydrogen, a hydrogen halide compound, a compound of the compound, and a compound of a wrong compound. This is preferably done in a remote crystal reactor. The concentration of the gaseous compound is set such that the composition of the SiwGey material undergoes a net deposition under selected pressure and temperature conditions. Preferably, the deposition is carried out at a temperature between 900 and 1100 C and at atmospheric pressure or at a lower pressure. The deposition rate is greater than 0 nm/min and preferably at most 50 nm/min. Suitable rhodium compounds include SiH4 and chlorodecane, with dichloromethane being preferred. Suitable hydrazine compounds are chlorodecane and its alkyl derivatives, and GeH4. It is especially good with GeH4, GeCl4 and CHsGeCl3. The ratio of the ruthenium compound to the erbium compound used as the deposition interface layer in the gas atmosphere is set such that the grown interface layer has the desired composition φ Sll-yGey. Preferably, the hydrogen halide compound is HC1 in the gas atmosphere. The ratio of the surface functional nitrogen compound to the ruthenium compound and the ruthenium compound is preferably within the range of 100:1 to 1.9. Due to the low density of the surface thread difference and the low roughness of the surface of the interface layer, it is particularly suitable for _- as a layer of the other layer directly on the surface of the interface layer. Nevertheless, it is also possible to deposit one or more layers in advance, for example, before the deposition of the L-layer, a 'depositable-relaxed heterogeneous stray layer (with a composition of SiNzGez) can be used as a buffer layer on the interface layer; In this case, the index z is preferably pushed in the same way as the & number y. The relaxation of the buffer layer is preferably greater than 9%. The thickness of the buffer 8 1289881 layer is preferably from 1 to 2 microns. Comparative Example: The ruthenium substrate wafer was treated under reduced pressure in a single-wafer epitaxial reactor, and the following steps were performed: • First step: Reactor charging second step · At a temperature of 1120 QC, in hydrogen Heat treatment of the substrate wafer (H2 baking) in the presence of the third step: depositing a SiGe layer (transfer layer) having an increased germanium content (0 to C 20%) at a temperature of 800 to 900 ° C. : Depositing a buffer layer (constant composition layer) with a constant tantalum content of 20% and 1 micron thick. Step 5 · Depositing a strain of 18 nm thick at 700 ° C. Step 6: From Multilayer structure formed by reactor unloading: Other substrate wafers of the same type as the comparative examples were treated in the same φ reactor as in the comparative example, but with one difference: first to third steps: as compared Example 4: By introducing a mixture of hydrogen chloride, dichlorosilane and decane, a fifth to seventh step of depositing an interface layer of ruthenium and osmium having a constant yttrium content of 20% at a temperature of 1050 QC: Multilayer structure formed by the same test from four to six steps: Inspection system of interface layer Cross-sectional electron microscopy instrument (X-TEM) whom. The first figure clearly shows the interface layer between the hierarchical layer (with the difference network) and the constant composition layer. The interface layer has a thickness of 9 1289881 degrees of about 2 to 3 nm. The second figure shows how the difference from the SiGe layer is absorbed in the interfacial layer. The difference is present in the boundary between the siGe layer and the interfacial layer and does not further grow into a buffer layer. The deposition of the planar interface layer reduces the thread difference density (TDD), especially the stacking density (PixD) of the difference, and also reduces the root mean square roughness, so the interleaving cable (c(7) wood structure can be dispensed with. During the deposition of the interface layer, the surface morphology is affected by changes in processing conditions over a wide range. Comparative Example ——--- Example TDD/cm 4χ105 1.3χΐ〇4 PuD/cm a 18 1.0 RMS40 μm Χ40 micron 6.5 nanometer 1.6 nanometer RMS 1 micron X 1 micron 0.42 nanometer 0.14 nanometer [Simple description of the diagram] The first figure shows the interface layer between the hierarchical layer (with the difference network) and the hate layer. The thickness of the interfacial layer is about 2 to 3 nm. The first figure shows how the absorption from the lower SiGe layer is absorbed in the interfacial layer. The difference exists in the boundary plane between the SiGe layer and the interfacial layer without further Grow into a buffer layer. [Main component symbol description]