1289855 13064twf.d〇c/〇〇6 九、發明說明： 【發明所屬之技術領域】 有關ί發蚊義於—種轉錄記憶鮮元，且特別是 ί1 =種反賴單対__揮雜記_單元及ί ^方法、可編财法鱗取—賴單元之方法。-【先前技術】 變為電Ιίίί快速發展，_料儲存技術已 # "皿 11嵩式消費電子產品中，固態資料儲存 :更朝向小型化、簡單化、低成本的目標邁進。固離資 料儲存技術（例如為可抹除可編程唯讀記憶體（EPR0My 電子可抹除可編程唯讀記憶體（EEPR0M)等技術）將 常，合發展高速的應用裝置，尤其是具有複雜與昂貴程序 之馬速應用裝置。然而，就許多消f性電子產品而言，相 較於高速度，低成本之考量將更為重要。 所以，習知技術才發展出二極體可編程之唯讀記憶體 (diode programmable read oniy memories (DpR〇Ms)):由 於舄要深渠溝隔離與石夕蟲晶層，因此，此二極體可編程之 唯讀記憶體的製程乃過於複雜，故此二極體可編之 記憶體的生錢本將難崎低。 & 基於上述之觀點，故需要發展一種具有小型化、簡單 化、低生產成本的可編程非揮發性記憶體單元。 【發明内容】 本發明提供一種反溶絲單次可編程的非揮發性記憶 體單元及其製造方法、編程方法與讀取方法，以滿足其^ 1289855 13064twf.doc/006 平 ΊΕΝ* 土在观个〇 元，=ΓΐΓ種聽絲單次可編程非揮發性記恃體單 兀，可包括-基板、第三雜質摻雜區、 巧早 絕緣區與-第二絕緣區、一雜質摻‘二了 石夕化金屬層。其中基板具有—第及—多晶 質摻雜區，分別具有一第一極性。第三雜第二雜 近第-雜質摻㈣與第二雜質摻雜摻f區位於鄰 雜區具有與第-雜質摻雜區及第二雜質;雜雜質摻 ==。:熔絲乃是配置於第三雜質二， 弟絕緣&與一弟二絕緣區分別上 第二雜質摻雜區上。-雜質摻雜的多晶石H貝摻雜區與 絕緣區、第二絕緣區以及反炫絲置於第一 置於此雜質摻雜的多晶石夕層上。當此雜質:二if層配 可作為，元線。此第三雜質推雜區（位貝^雜區 板中並藉由第-雜質摻雜區與第巴可埋於基 反熔絲單次可編程非揮發性記憶體單元之此 依照本發_—實施例之反 。 記憶體單元，其中反熔絲之厚度介㈣生 間。f一實施例中，每一絕緣區具有介於約5=_之 3500A的厚度。在另—實施财，每— A至約 層與多晶石夕化金屬層的厚度介於約500A至多晶石夕 在另一實補卜基㈣_p絲板;之間。 第二雜質推雜區一且第三雜質1心 doc/006 區。在一實施例中，每一絕緣區為氧化物區與氮化物區的 其中之一。反熔絲之材質可以為二氧化矽、氧化物-氮化物 -氧化物(〇xide-nitride_oxide (ΟΝΟ))、ai2〇3、Zr〇x 與 Hf〇x 等，其中x代表一整數，為一化學方程數字。當然，在實 施例中，任何製造反熔絲的材質都將難以全部地條列出 來，故不限於上述之材質。 本發明另提出一種反熔絲單次可編程非揮發性記憶 體單元的編程方法。在編程期間，施加一正向編程偏壓於 • 反溶絲單次可編程非揮發性記憶體單元之字元線與位元 線之間。在一實細例中’此正向編程偏壓之範圍介於約My 至約15V之間。結果，將燒灼反熔絲單次可編程非揮發性 各己fe體單元之反溶絲，以形成一已編程區（連結），其可 作為一個二極體。 〃 依照本發明的一實施例所述之反炼絲單次可編程非 揮發性§己憶體單元的編程方法，更包括一反溶絲 程非揮發性記憶體單元的讀取方法，藉由施加一正向讀取 • 偏壓於反熔絲單次可編程非揮發性記憶體單元之位元線 與字元線之間。其中，此讀取偏壓之較佳範圍係介於約 1.2V至約5V之間。 、'’ 本發明並提出一種反熔絲單次可編程非揮發性 ，兀的製造方法，包括下列數個步驟。於一基板上形^一 第-雜質摻雜區。接著，於第一雜質摻雜區上形成一絕緣 二麻在冑⑯例巾’藉由—化學氣相沉積製程而形成此絕 緣層。钱刻此絕緣層之一中間部分直到在底部的第一雜質 1289855 13〇64twf.d〇c/〇〇6 換雜+區暴露出來，結果，將於絕緣層之中間部分形成一渠 屢。藉由剩餘的絕緣層而形成兩相互間隔的絕緣區。接著， 形成:反熔絲於渠溝之底部。之後，形成一第二雜質摻雜 區於^一雜質摻雜區之一部份，其位於反熔絲之底部。第 ^雜貪摻雜區具有與第一雜質摻雜區相反之極性。在形成 • 第—雜質摻雜區的步驟中，在植入雜質後，可藉由一快速 火製程而退火第二雜f摻雜區。然後，形成一雜質捧 亦隹夕曰日矽層於絕緣區與反溶絲上。接著，形成一多晶矽化 金^層於雜質摻雜多晶矽層上。在一實施例中，植入第一 雜貝摻雜區之材質為硼，且植入第二雜質摻雜區為砷與磷 的其中之一。 ^ 本發明之反熔絲單次可編程非揮發性記憶體單元的 尺寸較小、較為簡化，故可產生一微型的反熔絲單次可編 私非揮發性儲存陣列，以有效地節省其製造成本。 *為讓本發明之上述和其他功效、特徵和優點能更明顯 易懂，下文列舉一實施例，並配合所附圖式，作詳細說明 ^ 如下。 【實施方式】 圖1繪示為本發明一實施例之一種反熔絲單次可編程 的非揮發性儲存陣列100之俯視示意圖。首先，請參照圖 1，此反熔絲單次可編程的非揮發性儲存陣列（anti_fuse one-time-programmable (OTP) nonvolatile memory array)l〇0包含三條橫向的字元線u〇、兩條垂直的位元線 120、六個反熔絲130以及三個垂直的厚絕緣區14〇。這些 1289855 13064twf.doc/006 ’、口，子元、線i1〇之材質包括石夕化鶴與捧雜的多晶石夕， 而兩i、垂直的位元線12〇被植入N+離子，且每一厚絕緣 ，140之材質包括氧化物或氮化物的其中之—。此反溶絲 單次^編朗非揮贿儲存陣列·具有六個祕絲單次 可編程的非揮發性記憶體單元，位於這些橫向的字元線 110與垂直的位元線120間的交叉處。 圖2繪不為本發明一實施例之兩個反熔絲單次可編程 的_發性記㈣單元(記憶體料_1與記醜單元2) 之剖面示意圖。請參照圖2,三個P-摻雜區22〇植入於P 井基板210之頂部，以形成具有較佳隔離效果的n+摻雜 區24〇a與240b。埋入P井基板210内之N+摻雜區240a 與2働可分別作為記憶體單元—1與記憶體單元—2的位元 線。N+摻雜區240a與240b (位元線）可於位元線間距上 提供較低的阻抗與較佳的尺寸調整能力。 兩反熔絲280a及280b (如圖所示之材料層）乃分別 形成於兩N+摻雜區240a與240b上。每一反熔絲280a及 # 280b之厚度大於周邊元件的閘氧化層之厚度，使得周邊元 件可傳送一較高的偏壓於反熔絲單次可編程的非揮發性記 憶體單元，以於一編程操作中燒灼此反熔絲。在編程操作 中燒灼一反熔絲材料層將可降低此反溶絲的阻抗，因此， 在已編程之燒灼位置上連結(link)以形成電性連接。三個厚 絕緣區230形成於此三個p-摻雜區220上。在一實施例 中，此厚絕緣區230之材質包括氧化物或氮化物。 一斜向(hatched)影線之字元線290形成於三個厚絕緣 1289855 13064twf.doc/006 區230與兩反熔絲280a及28%上。 包含一 Ρ-摻雜之多晶，夕層25〇 二 ，其中多晶石夕化金屬層260位於ρ__〇 ^^屬^ 上。多晶石夕化金屬層260可用以降低字元線携之阻曰抗， 其中多晶魏金屬層26G可以為—_化鹤層。 2S0 ^^4 290 .^ 2術與位讀24Ga，同#地，記憶 ^約反^2。8%與"^線24% ’其中每一記憶體^元^ 此三厚絕緣區23〇乃是用以隔離n+推雜區（位元線） a及繼與字元線脈在—實施例中，此三厚絕緣區 可例如藉&化學氣相沉積法而形成。在反溶絲單次 可編程的非揮發性域料元之製程巾，此化學氣相沉積 广所需的較低溫度將可有效地降低熱預算咖刪i udget) °絲’相較於魏化隔離方^，由祕絲單次可 編程的非^發性域料元所構成之_密度將會上升。 〇 /σ著介於N+摻雜區（位元線）240a或240b與P-摻雜 區220之間的垂直接觸表面形成一隔離N+/ ρ·基板接合 (ju=tic^)270。在圖中’此隔離N+/ ?_基板接合27〇的區域 之一乃疋以虛線圓圈的方式來強調。此隔離]^+/1>_基板接 合270可隔離記憶體單元―丨與記憶體單元_2之位元線 240a及240b。因此，在記憶體單元」與記憶體單元_2之 間將不需要其他的隔離物，以有效地簡化其製程與製造成 本。 1289855 13064twf.doc/006 口圖3繪示為本發明一實施例之一種編程一選擇的反熔 絲單次可編程的非揮發性記憶體單元之方法。請參照圖 3,本實施例乃是編程位於左侧之已選擇的反熔絲單次可編 程的非揮發性記憶體單元（記憶體單元—1)。在此編程操 作過程中，一適當的編程偏壓施加於記憶體單元1之已選 擇^位元線240a與字元線290，以燒灼此反熔絲r28〇a。在 本貫施例之編程操作過程中，此P井基板21〇與記憶體單 元一2之未選擇的位元線240b乃是浮置的。在另一實施例 藝中，施加於字元線290的編程電壓約為lov且記憶體單元 一 1之位元線240a乃接地。 介於字元線290與位元線240a間的編程偏壓將燒毀 各己’丨思體單元—1之反熔絲280a。結果將在記憶體單元1之 位元線240a與字元線29〇之間形成一已編程區域（連結 (link)) 285。在記憶體單元一 1之讀取操作中，此讀取電流 將由字元線290流向其位元線240a。 相較於未燒毀之反溶絲280b，由於已燒毀之反炼絲 • 28如具有較低的阻抗，在記憶體單元J之反熔絲280a以 及e己丨思體單元一2之反熔絲280b之間的不同阻抗程度將使 得已編程之記憶體單元一丨呈現出邏輯“Γ，，相對地，未編 程之記憶體單元_2呈現出邏輯“〇，，。 圖4繪示為圖3已編程的反熔絲單次可編程非揮發性 &己憶體單元（如圖3之記憶體單元一 1 )之剖面示意圖及其 放大的已編程區域（連結(link)) 285。請參照圖4，已編 程之記憶體單元一 1呈現出邏輯“1”。此已編程區域（連結 11 1289855 13064twf.doc/006 (link)) 285 包含一 p-區塊(bl〇ck)410 與一 n+區塊 420，其 功能例如為一 P-/N+之二極體。由於施加正向編程偏壓， 此已編程區域（連結(link)) 285具有一空乏區（如圖4所 示）’其鄰近於介於P-區塊(bl〇ck)410與N+區塊420之間 的接觸面。1289855 13064twf.d〇c/〇〇6 IX. Invention Description: [Technical field of invention] The ί 蚊 蚊 于 — — 种 种 种 种 种 种 种 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Unit and ί ^ method, method of making money for the scale of the method. - [Prior Art] Turned into electricity Ι ίίί rapid development, _ material storage technology has been # " dish 11-inch consumer electronics products, solid-state data storage: more toward miniaturization, simplification, low-cost goals. Solid-state data storage technology (for example, technologies such as EPR0My Electronically Erasable Programmable Read-Only Memory (EEPR0M)) can be used to develop high-speed applications, especially complex Explosive application of the speed application device. However, for many consumer electronics products, compared with high speed, low cost considerations will be more important. Therefore, the conventional technology developed the diode programmable only Diode programmable read oniy memories (DpR〇Ms): Because of the deep trench isolation and the stone layer, the process of the binary read-only memory is too complicated. The memory of the memory that can be edited by the diode can be difficult to achieve. & Based on the above viewpoint, it is necessary to develop a programmable non-volatile memory unit with miniaturization, simplification, and low production cost. The present invention provides a non-volatile memory unit with a single-programmable anti-solving filament, a manufacturing method thereof, a programming method and a reading method thereof, so as to meet the requirements of the method: 1289855 13064twf.doc/006 A single-programmable non-volatile recording body, which can include a substrate, a third impurity doped region, a prioritized insulating region and a second insulating region, and an impurity doping The second layer of the metal layer, wherein the substrate has a -first-polycrystalline doped region, respectively having a first polarity. The third impurity second hetero-near- impurity doped (four) and the second impurity doped f-doped region Located in the adjacent impurity region and the first impurity-doped region and the second impurity; impurity impurity doping ==: the fuse is disposed in the third impurity two, the second insulation and the second impurity on the second insulating region On the doped region, the impurity-doped polycrystalline oxide H-doped region and the insulating region, the second insulating region, and the anti-spike are placed on the first polycrystalline layer doped with the impurity. Impurity: the second if layer can be used as the element line. The third impurity doping region (in the bit-to-noise region plate and by the first impurity doping region and the second bar can be buried in the base anti-fuse single programmable The non-volatile memory unit is in accordance with the present invention. The memory unit, wherein the thickness of the anti-fuse is interposed (iv), in an embodiment, An insulating region has a thickness of about 5 = _ 3500 A. In another implementation, the thickness of each of the A to about layers and the polycrystalline sinusoidal metal layer is between about 500 A and the polycrystalline stone. A second impurity etch region and a third impurity 1 doc/006 region. In one embodiment, each of the insulating regions is one of an oxide region and a nitride region. The material of the antifuse may be cerium oxide, oxide-nitride-oxide (〇xide-nitride_oxide (ΟΝΟ)), ai2〇3, Zr〇x and Hf〇x, etc., wherein x represents an integer, which is one. Chemical equation numbers. Of course, in the embodiment, any material for manufacturing the anti-fuse will be difficult to list all of the materials, and thus it is not limited to the above materials. The present invention further provides a method of programming an anti-fuse single-time programmable non-volatile memory cell. During programming, a forward programming bias is applied between the word line of the anti-solving single-programmable non-volatile memory cell and the bit line. In a practical example, this forward programming bias range is between about My and about 15V. As a result, the antifuse of the anti-fuse single-programmable non-volatile individual body unit will be cauterized to form a programmed region (link) which acts as a diode.编程 A method for programming a single-programmable non-volatile § memory unit of an anti-refining wire according to an embodiment of the invention, further comprising a method for reading a reverse-dissolved wire-length non-volatile memory unit, Apply a forward read • Bias between the bit line of the anti-fuse single-programmable non-volatile memory cell and the word line. Wherein, the preferred range of the read bias is between about 1.2V and about 5V. The invention also provides a method for manufacturing an anti-fuse single-programmable non-volatile, crucible comprising the following steps. Forming a first impurity-doped region on a substrate. Next, an insulating layer is formed on the first impurity doping region to form the insulating layer by a chemical vapor deposition process. The middle portion of the insulating layer is engraved until the first impurity 1289855 13〇64twf.d〇c/〇〇6 is replaced at the bottom, and as a result, a plurality of regions are formed in the middle portion of the insulating layer. Two spaced apart insulating regions are formed by the remaining insulating layer. Next, an antifuse is formed at the bottom of the trench. Thereafter, a second impurity doped region is formed in a portion of the impurity doped region, which is located at the bottom of the antifuse. The doped region has a polarity opposite to that of the first impurity doped region. In the step of forming the -first impurity doped region, after implanting the impurity, the second impurity-doped region can be annealed by a rapid fire process. Then, an impurity is formed on the insulating layer and the anti-solving wire. Next, a polycrystalline germanium layer is formed on the impurity doped polysilicon layer. In one embodiment, the material implanted in the first doped region is boron, and the implanted second impurity doped region is one of arsenic and phosphorous. The anti-fuse single-programmable non-volatile memory cell of the present invention is small in size and simple, so that a miniature anti-fuse single-packable non-volatile memory array can be produced to effectively save its manufacturing cost. The above and other advantages, features and advantages of the present invention will become more apparent from the following description. [Embodiment] FIG. 1 is a top plan view of an anti-fuse single-programmable non-volatile memory array 100 according to an embodiment of the invention. First, referring to FIG. 1, the anti-fuse one-time-programmable (OTP) nonvolatile memory array l〇0 includes three horizontal word lines u〇 and two Vertical bit line 120, six antifuse 130, and three vertical thick insulating regions 14A. These 1298855 13064twf.doc/006 ', mouth, sub-element, line i1 〇 material includes Shi Xihua crane and holding polycrystalline stone eve, while two i, vertical bit line 12 〇 is implanted with N+ ions, And for each thick insulation, the material of 140 includes one of oxide or nitride. The reverse-dissolving wire is a single-time non-scoring storage array. The non-volatile memory unit having six secret lines is programmable at a cross between the horizontal word line 110 and the vertical bit line 120. At the office. 2 is a cross-sectional view showing a single-time-programmable (four) unit (memory material_1 and ugly unit 2) of two anti-fuse according to an embodiment of the present invention. Referring to Figure 2, three P-doped regions 22 are implanted on top of the P-well substrate 210 to form n+ doped regions 24a and 240b having better isolation. The N+ doped regions 240a and 2働 buried in the P well substrate 210 can serve as bit lines of the memory cell-1 and the memory cell-2, respectively. The N+ doped regions 240a and 240b (bit lines) provide lower impedance and better dimensional adjustment capability over the bit line pitch. Two antifuse 280a and 280b (material layers as shown) are formed on the two N+ doped regions 240a and 240b, respectively. The thickness of each of the anti-fuse wires 280a and #280b is greater than the thickness of the gate oxide layer of the peripheral component, so that the peripheral component can transmit a higher bias voltage to the anti-fuse single-programmable non-volatile memory cell. The antifuse is cauterized during a programming operation. Cauterizing an antifuse material layer during a programming operation will reduce the impedance of the antifuse wire and, therefore, link at a programmed cauterization location to form an electrical connection. Three thick insulating regions 230 are formed on the three p-doped regions 220. In one embodiment, the material of the thick insulating region 230 comprises an oxide or a nitride. A hatched hatch line 290 is formed over three thick insulating 1289855 13064 twf.doc/006 regions 230 and two antifuse 280a and 28%. A ruthenium-doped polycrystal is included, and the polycrystalline layer 〇 金属 metal layer 260 is located on the ρ__〇^^ genus. The polycrystalline tempered metal layer 260 can be used to reduce the resistance of the word line, wherein the poly-Wei-metal layer 26G can be a _ _ _ layer. 2S0 ^^4 290 .^ 2 surgery and bit reading 24Ga, same as #地,记忆^约反^2.8% and "^线24% 'each of the memory ^ yuan ^ This three thick insulation zone 23〇 It is used to isolate the n+ dummy region (bit line) a and the subsequent word line. In the embodiment, the three thick insulating region can be formed, for example, by chemical vapor deposition. In the anti-solvent single-programmable non-volatile domain material processing towel, the lower temperature required for this chemical vapor deposition will effectively reduce the thermal budget, and the temperature will be reduced. The isolation level ^, the density of the single-programmable non-competitive domain element of the secret wire will increase. 〇 /σ forms an isolated N+/ρ·substrate bond (ju=tic^) 270 between the vertical contact surface between the N+ doped region (bit line) 240a or 240b and the P-doped region 220. In the figure, one of the areas where the N+/?_ substrate is bonded 27〇 is emphasized by a dotted circle. The isolation]^+/1>_substrate bond 270 isolates the bit lines 240a and 240b of the memory cell 丨 and memory cell_2. Therefore, no other spacers will be required between the memory unit and the memory unit_2 to effectively simplify the manufacturing process and manufacturing cost. 1289855 13064twf.doc/006 Figure 3 illustrates a method of programming a selected anti-fuse single-programmable non-volatile memory cell in accordance with one embodiment of the present invention. Referring to Figure 3, the present embodiment is a non-volatile memory unit (memory unit-1) programmed with a single anti-fuse programmable on the left side. During this programming operation, an appropriate programming bias is applied to the selected bit line 240a and word line 290 of the memory cell 1 to cauterize the antifuse r28〇a. During the programming operation of the present embodiment, the unselected bit line 240b of the P-well substrate 21 and the memory cell 2 is floating. In another embodiment, the programming voltage applied to word line 290 is approximately lov and bit line 240a of memory cell 1 is grounded. A programming bias between word line 290 and bit line 240a will burn out anti-fuse 280a of each of the body units. As a result, a programmed area (link) 285 is formed between the bit line 240a of the memory cell 1 and the word line 29A. In the read operation of memory cell one, this read current will flow from word line 290 to its bit line 240a. Compared with the unburned anti-solvent wire 280b, the anti-fuse wire 280a in the memory unit J and the anti-fuse wire in the memory unit J 2 due to the lower impedance of the burned anti-refining wire 28 The different levels of impedance between 280b will cause the programmed memory cells to present a logical "Γ, relatively, unprogrammed memory cell 2 exhibits a logical "〇,". 4 is a cross-sectional view of the programmed anti-fuse single-programmable non-volatile & memory cell unit of FIG. 3 (memory cell 1 of FIG. 3) and its enlarged programmed area (link ( Link)) 285. Referring to Figure 4, the programmed memory unit 1 exhibits a logic "1". The programmed area (link 11 1289855 13064twf.doc/006 (link)) 285 includes a p-block (bl〇ck) 410 and an n+ block 420, the function of which is, for example, a P-/N+ diode. . Due to the application of the forward programming bias, the programmed region (link) 285 has a depletion region (shown in Figure 4) which is adjacent to the P-block (bl〇ck) 410 and the N+ block. The contact surface between 420.
圖5a至5b繪示為本發明一實施例之六個反熔絲單次 可編程非揮發性記憶體單元在編程操作中與經編程操作後 的不意圖，其中這些反熔絲單次可編程非揮發性記憶體單 元乃疋連接於三條位元線與三條字元線。假定此六個未編 程的反熔絲單次可編程非揮發性記憶體單元具有多個N+ 摻雜區與P-摻雜區，以分別作為位元線與字元線。圖％ 繪示為六個未編程的反熔絲單次可編程非揮發性記憶體單 几，其分職接於-橫向的位元線與—垂直的字元線。在 這些未編㈣反熔絲單次可發性記髓單元的苴 中之-將被編程。在圖5a中，此選擇的未編程的反溶絲單 次可編程非揮發性記憶體單it將以虛線圓圈而圈出。 在本實施例之編程操作過程中，一編程電壓v卯乃是 ，加於此騎的反㈣單切編程_發性鋪體單元之 ^線，且其位凡線乃是接地。在圖5a中，其餘的字元線 =元線乃是浮置的。在另-實施财，此編程電壓vpp 的乾圍從約10V至約15V。 _ ^介於已敝熔料対細_發性記憶體單 二：二 線間的正向編程偏壓(、)的施加期 間’將燒毀已選擇的反麟、單次可編程轉發性記憶體單 1289855 13064twf.doc/006 二 溶糸以編程已選擇的反私絲早次可編程非揮發性 記憶體單元（邏輯“1”）。結果，一已編程之區域（連結(lin'k)) 將幵7成於此已選擇的反溶絲單次可編程非揮 =以作為二極體。在執行編心 二 中’此已編程的反熔絲單次可編程非揮發性記情體單 元乃是以虛線圓圈而指出。 w - 程至/Γ會示為本發明一實施例之反炼絲單次可編 法、單元的三種編程方法，其分別為菲力浦 性钟體單元法。假定每—反麟單対編程非揮發 盔;』早70具有- N+摻雜區與- P-摻雜區，以分別作 ^立1與字元線。在圖6a至6C中之垂直線代表字元線， 之’橫向線代表位元線。在圖6a至6 ，單次可編程非揮發性記憶體單元。當未 味ΪΓ未選擇的反熔絲單次可編程非揮= 體3:==保持不變時，這些已選擇的記憶 憶體單—反炫絲單次可編程非揮發性記 藉由如目6a所示之菲力浦法，當未選 接戈到-反向偏壓（-Vp)時，此，的4體早兀 :受到一正向偏壓（Vp)。如圖 i的正向偏壓（Vp)於已選擇的記 、 π兀 的正向偏壓（Vp/2 )於未選擇的記單_疋以及一已降低 法。如圖6c所示，當施加-已降己^體而執行此Μ 者是一反向鍾（·νρ/3)料選擇的記 13 1289855 13064twf.doc/006 ==(Vp)於已選擇的記憶體單元而執行此Μ法。 二=/2法中之已降低的正向偏壓(νρ/2)以及使用 ‘掉挪二土’已降低的正向偏壓（Vp/”不夠高時，將盔 反熔絲單次可編程非揮發性記憶體單ΐ 糸。在一貝施例中，此νΡ值的範圍由約i ο v至约 =他，擇的記憶體料未被干擾時，可藉由使用 編财法並施加—完整的正向偏壓（vP) 於1體早π，以選擇並編程為邏輯“Γ，。 正向與反向麟與—反熔絲單次可編程非揮發性 :it 元線與字元線的極性_·)有關。假如 Ρ 反料單対触轉發餘㈣單元具有一 推雜區以分別作為其位元線與字元線，當 線接地時，為了讓:::=2性記憶體單元之字元 之次可編程非揮發性記憶體單元 非揮發：：實施例之一種反熔絲單次可編程 的二==成:儲存陣列在經-讀取操作時 η n+摻雜區與-p-摻雜區以分別作 字元線。因此，當圖7所示之橫向線代表2 A ^ T、++直線代表字元線。如圖7所示’此反溶今單 次可編程非揮發性儲存陣列僅具有-已編程的：單：5a to 5b illustrate a schematic diagram of six anti-fuse single-time programmable non-volatile memory cells in a programming operation and a programmed operation, wherein the anti-fuse is single-programmable according to an embodiment of the invention. The non-volatile memory unit is connected to three bit lines and three word lines. It is assumed that the six unprogrammed anti-fuse single-time programmable non-volatile memory cells have a plurality of N+ doped regions and P-doped regions to serve as bit lines and word lines, respectively. Figure % is shown as six unprogrammed anti-fuse single-programmable non-volatile memory blocks that are subordinated to the horizontal bit line and the vertical word line. In these unscheduled (four) anti-fuse single-shot priming units, the 将 will be programmed. In Figure 5a, this selected unprogrammed anti-solvent single-programmable non-volatile memory single it will be circled with dashed circles. During the programming operation of this embodiment, a programming voltage v 卯 is added to the line of the anti-(four) single-cut programming _ genitive paving unit of the ride, and its bit line is grounded. In Figure 5a, the remaining word line = element line is floating. In another implementation, the programming voltage vpp has a dry circumference of from about 10V to about 15V. _ ^ Between the 敝 敝 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Single 1288855 13064twf.doc/006 Two solutions to program the selected anti-private silk early programmable non-volatile memory unit (logic "1"). As a result, a programmed region (link (lin'k)) will be 于此7 into this selected anti-solvent single-programmable non-volatile = as a diode. In the Execution Compilation 2, this programmed anti-fuse single-programmable non-volatile ticks unit is indicated by a dashed circle. w - Cheng to / Γ will be shown as one embodiment of the anti-refining wire single-programming and three programming methods of the unit, which are respectively the Philippine clock body unit method. It is assumed that each----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The vertical lines in Figs. 6a to 6C represent word lines, and the 'transverse lines represent bit lines. In Figures 6a through 6, a single programmable non-volatile memory cell. When the anti-fuse unselected anti-fuse single-programming non-volatile body 3:== remains unchanged, these selected memory memory single-anti-drawing silk single-programmable non-volatile recordings are as The Phillips method shown in Fig. 6a, when unselected to the reverse bias (-Vp), the 4 bodies are early and biased (Vp). The forward bias (Vp) of Figure i is the selected forward bias, π兀 forward bias (Vp/2) to the unselected __ and a reduced method. As shown in Fig. 6c, when the application is performed, the Μ is performed as a reverse clock (·νρ/3). The selection of the 13 13289855 13064 twf.doc/006 == (Vp) is selected. This method is performed by the memory unit. The reduced forward bias (νρ/2) in the two=/2 method and the reduced forward bias (Vp/" using 'drop two earth' are not high enough, the helmet anti-fuse can be single Programming a non-volatile memory unit 糸. In a case, the νΡ value ranges from about i ο v to about = he, when the selected memory material is not disturbed, Apply—complete forward bias (vP) to 1 body early π to select and program as logic “Γ. Forward and reverse Lin and – Anti-fuse single-programmable non-volatile: it line with The polarity of the word line is related to _·). If the 対 対 対 转发 转发 ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四Programming non-volatile memory cells are non-volatile: an anti-fuse of an embodiment is single-programmable two == into: the storage array is in the n-doped region and the -p-doped region during the read-and-read operation Separate word lines. Therefore, when the horizontal line shown in Fig. 7 represents 2 A ^ T, the ++ line represents the word line. As shown in Figure 7, this reverse-dissolved single-programmable non-volatile storage array has only - programmed: single:
14 1289855 13064twf.doc/006 :編程非揮發性記憶體單元（邏輯“1”），其以二極體符號 來代表，至於其餘的反熔絲單次可編程非揮發性記憶體單 兀1未編程（邏輯。當讀取此已編㈣反朗、單次可 、、扁私非揮發性記憶體單元時，施加一讀取電壓Vcc於其字 元線且將其位元線接地，至於其餘的位元線與字元線i浮 置的° ®7所示讀頭乃是代表此已編程的祕絲單次可 編程非，發性峨體單元之讀取電朗流向。在一實施例 中，此讀取電壓Vcc值的範圍由約12v至約5v。14 1289855 13064twf.doc/006 : Programming a non-volatile memory unit (logic "1"), represented by a diode symbol, as for the remaining anti-fuse single-programmable non-volatile memory unit 1 Programming (logic. When reading this edited (four) anti-lang, single-time, flat private non-volatile memory cell, apply a read voltage Vcc to its word line and ground its bit line, as for the rest The read bit shown by ° ® 7 is floating on the bit line i and the word line i. This is a read-only power flow of the single-programmable non-initial unit of the programmed secret wire. The read voltage Vcc value ranges from about 12v to about 5v.
圖8緣不為|發明一實施例之一種反溶絲單次可編程 2發性存_德—讀取操料，其如何預防產生讀 退漏電流的示意®。假定如圖8所示之每—反溶絲單次 :、扁％非揮發性$憶體單元具有—N+摻雜區與—換雜 別作為其位兀線與字元線。在圖8所示之九個反溶 ^早:人可編程非揮發性記紐單元巾，當反熔絲單次 揮^記憶體單元的其中之—為未編程之狀態 =輯G )時，其餘人個⑽絲單次可編雜揮發性記憶 ，早二為已編程之狀態（邏輯“r)。圖8中之垂直線代表 相反地，橫向線代表位元線。當讀取未編程之反 总絲早次可編程非揮發性記憶體單元時，—讀取電壓％ ^施加於其字元線謂其位元線連接至-❹m大器 (sense ampler (S/A)) , ^^Fig. 8 is not a schematic representation of how to prevent the generation of a readback leakage current by a single-programmable one-time memory. Assume that each of the -resolved filaments as shown in Fig. 8: the flat % non-volatile $ memory unit has -N + doped regions and - miscellaneous as its bit line and word line. In the nine reverse-dissolving early: human-programmable non-volatile counter unit wipes shown in Figure 8, when the anti-fuse single-swap memory unit is in an unprogrammed state = set G, The rest of the (10) silk can be programmed with a single memory, the second is the programmed state (logic "r). The vertical line in Figure 8 represents the opposite, the horizontal line represents the bit line. When reading unprogrammed When the anti-total filament is programmed for a non-volatile memory cell, the read voltage % ^ is applied to its word line, and its bit line is connected to the -sm ampler (S/A), ^^
貫施例中，此電壓Vee值的範圍由約UV 由於欲讀取之反溶絲 單次可編程非揮發性記憶體單元 15 1289855 13064twf.doc/006 為未編程狀態，故此未編程的反熔絲單次可編程非揮發性 記憶體單元之反熔絲乃未被燒毀。因此，連接於其位^線 之感測放大器將無法偵測到讀取電流的流動。由於已編程 的，域（連結(link))形成在此儲存陣列中之已編程的反= 絲單次可編程非揮發性記憶體單元内，以作為多個p_如+ 二極體，在圖8中以雙虛線圓圈圈出而強調之已編程的區 域（連結(link))將可預防任何之讀取漏電流流經1In the example, the voltage Vee value ranges from about UV. Since the anti-solving filament single-programmable non-volatile memory unit 15 1289855 13064twf.doc/006 to be read is in an unprogrammed state, the unprogrammed anti-melting is performed. The anti-fuse of the wire single-programmable non-volatile memory cell is not burned. Therefore, the sense amplifier connected to its bit line will not be able to detect the flow of the read current. Since programmed, domains (links) are formed in the programmed inverse-wire single-programmable non-volatile memory cells in the memory array as multiple p_eg + dipoles, The programmed area (link) highlighted in Figure 8 with a double dashed circle will prevent any read leakage current from flowing through
的，域（連結），在本實施例中，此已編程的區域'(連結^ 乃是作為一反向二極體(reverse diode)。因此，此反熔絲單 次可編程非揮發性儲存陣列將可防止在讀取操作中之漏電 ，的產生。當異於這些反熔絲單次可編程非揮發性記憶體 單，之其他記憶體單元使用於此儲存陣列中時，圖8中所 強調的路徑乃是顯示可能的讀取遺漏電流路徑。 。圖9a至％為本發明—實施例之—種㈣絲單次可編 私非揮發性憶體單元的製造方法。首先，請來昭圖， 提供一 p井基板910。接著，請參照圖％，藉由：；離子植 ^法而將-P·摻祕92〇形成於此p井基板⑽之上表 面、’其中-材質例如為硼乃被植人於p井基板91G之上表 面:成此P_掺雜區92G。請參照圖9e，配置—厚絕緣層 93=此P_摻雜區上。在一實施例中，此厚絕緣層謂 严化物層。在另-實施例中’此厚絕緣層％。為一 =化^。此外’例如可藉由1難程⑽成此厚絕 術\认’其中此沉積製程例如使用—化學氣相沉積技 另外，此厚絕緣層930之厚度範圍例如由約5〇〇A至 16 1289855 13064twf.doc/006 約3500A。只要能夠維持適當的極性，雖然可確定使用特 定的雜質，但亦可使用其他的雜質。, the domain (link), in this embodiment, the programmed region ' (the connection ^ is as a reverse diode. Therefore, the anti-fuse single-programmable non-volatile storage The array will prevent leakage during read operations. When these anti-fuse single-programmable non-volatile memory banks are used, other memory cells are used in this memory array, as shown in Figure 8. The emphasized path is to show the possible read missing current path. Fig. 9a to % are the manufacturing method of the (four) silk single-copyable non-volatile memory unit according to the invention - first embodiment, please come to Zhao In the figure, a p-well substrate 910 is provided. Next, referring to FIG. %, the -P·doping 92 〇 is formed on the upper surface of the p-well substrate (10) by means of ion implantation, and the material is, for example, Boron is implanted on the surface of the p-well substrate 91G: into the P-doped region 92G. Referring to Figure 9e, the configuration - thick insulating layer 93 = this P_ doped region. In an embodiment, this The thick insulating layer is called a fine layer. In another embodiment, 'this thick insulating layer %. is one = chemical ^. In addition, 'for example In addition, the thick insulating layer 930 has a thickness ranging from, for example, about 5 〇〇A to 16 1289855 13064 twf.doc/ by a hard process (10). 006 Approx. 3500 A. As long as the proper polarity can be maintained, although it is possible to determine the use of specific impurities, other impurities may be used.
請參照圖9d，钱刻並圖案化此厚絕緣層930直到底下 之P-摻雜區920暴露出來。結果，將形成多個渠溝94()與 多個分隔的厚絕緣層930,。請參照圖％，沉積多個反熔絲 950於這些渠溝940的底部。在一實施例中，每一反溶絲 950的厚度範圍由約10 A至約1〇〇人。另外，反熔絲95〇 的材質可以為二氧化矽、氧化物-氮化物-氧化物 (〇xide:mtride-oxide (ΟΝΟ))、a12〇3、ZrOx、HfOx 等，其 中x代表一整數，為一化學方程數字。當然，任何製造反 溶絲950的材質將難以全部地條列出來，故不限於上述之 材質。 请參照圖9f，將離子植入於位於這些反熔絲95〇下的 P_摻雜區920之部分，以形成多個N+摻雜區暢而作為多 條N+位兀線。然後，藉由一快速熱退火 anneal (RTA))製程而將此N+摻雜區96〇 (N+位元線）退 ^在-實施财，可於離子植人製程中使糾或填以形 此N+摻雜H 960。其餘的ρ·摻雜區92〇形成多數個p_ :才，區920，其用以隔離多個N+摻雜區_(n+位元線）。 2照圖％，最後，P_捧雜之多晶秒層970沉積於多個厚 全# _ 填入渠溝94G。一多晶石夕化 =層刪積於此p_摻雜之多晶㈣97。上。在一實施 二二，換雜之多晶石夕層970與多晶石夕化金屬層98〇 厗度粑圍從約500人至約細〇A。p_摻雜之多晶石夕層97〇 17 1289855 13064twf.doc/006 •與多晶矽化金屬層980可作為字元線。在一實施例中，多 晶矽化金屬層980可為一多晶矽化鎢層。 本發明之反熔絲單次可編程非揮發性記憶體單元使用 一反熔絲以儲存一邏輯狀態，且此反熔絲單次可編程非揮 發性圮憶體單元之尺寸約為4F2。此反熔絲單次可編程非 揮發性記憶體單元之位元線埋於基板中並由位於基板中之 兩鄰近的雜質摻雜區而隔開。由於本發明之反溶絲單次可 春編程非揮發性記憶體單元的結構簡單，故其生產成本較 低。此外，由於本發明之反熔絲單次可編程非揮發性記憶 體，元的尺寸較小且欲隔開兩記憶體單元間之隔離結構較 為簡化，因此，本發明之反溶絲單次可編程非揮發性記憶 體單7L所構成之儲存陣列將具有較高的密度。 ^ 雖然本發明已以一實施例揭露如上，然其並非用以限 =本發明’任何熟習此技藝者，在不脫離本發明之精神和 I巳，内’當可作些許之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 Φ 【圖式簡單說明】 圖1 %示為本發明一實施例之一種反熔絲單次可編程 的非揮發性儲存陣列100之俯視示意圖。 圖2緣示為本發明一實施例之兩個反熔絲單次可編程 的非揮發性記憶體單元(記憶體單元_1與記憶體單元_2) 之剖面示意圖。 — 么如圖3繪示為本發明一實施例之一種編程一選擇的反熔 、糸單-人可編程的非揮發性記憶體單元之方法。 18 1289855 13064twf.doc/006 二立圖:繪示為圖3已編程的反熔絲單次可編程非揮發性 記憶體單元（如圖3之記憶體單元J)之剖面示意圖。 圖5a至5b繪示為本發明一實施例之六個反熔絲單次 ^^揮發性Z憶體單元在編程操作巾與經編程操作後 罔⑽王〇cReferring to Figure 9d, the thick insulating layer 930 is engraved and patterned until the underlying P-doped region 920 is exposed. As a result, a plurality of trenches 94() and a plurality of spaced thick insulating layers 930 are formed. Referring to Figure %, a plurality of antifuse 950 are deposited at the bottom of these trenches 940. In one embodiment, each of the counter-solvent wires 950 has a thickness ranging from about 10 A to about 1 Torr. In addition, the material of the anti-fuse 95〇 may be cerium oxide, oxide-nitride-oxide (〇xide: mtride-oxide (ΟΝΟ)), a12〇3, ZrOx, HfOx, etc., where x represents an integer. A number for a chemical equation. Of course, any material from which the anti-solvent 950 is made will be difficult to list all of the materials, and thus is not limited to the above materials. Referring to Figure 9f, ions are implanted in portions of the P-doped region 920 under these antifuse 95 turns to form a plurality of N+ doped regions as a plurality of N+ germanium lines. Then, by using a rapid thermal annealing (RTA) process, the N+ doped region 96 〇 (N+ bit line) is retracted and implemented in the ion implantation process. N+ doped H 960. The remaining p-doped regions 92 are formed into a plurality of p_: regions 920 for isolating a plurality of N+ doped regions_(n+bit lines). 2 according to the figure %, finally, the P_ holding polycrystalline second layer 970 is deposited in a plurality of thick all # _ filled into the trench 94G. A polycrystalline stone = layer is decomposed in this p-doped polycrystal (IV) 97. on. In one implementation 22, the polycrystalline polycrystalline layer 970 and the polycrystalline lithiated metal layer 98 厗 粑 从 从 from about 500 to about 〇 A. P_Doped polycrystalline layer 97〇 17 1289855 13064twf.doc/006 • The polycrystalline germanium metal layer 980 can be used as a word line. In one embodiment, the polysilicon metallization layer 980 can be a polycrystalline tungsten oxide layer. The anti-fuse single-time programmable non-volatile memory cell of the present invention uses an anti-fuse to store a logic state, and the size of the anti-fuse single-programmable non-volatile memory cell is about 4F2. The bit lines of the anti-fuse single-programmable non-volatile memory cell are buried in the substrate and separated by two adjacent impurity doped regions located in the substrate. Since the anti-solvent filament of the present invention has a simple structure for programming a non-volatile memory unit, its production cost is low. In addition, due to the anti-fuse single-programmable non-volatile memory of the present invention, the size of the element is small and the isolation structure between the two memory cells is simplified, so that the anti-solving wire of the present invention can be single-time Programming a non-volatile memory single 7L storage array will have a higher density. Although the present invention has been disclosed in an embodiment of the present invention, it is not intended to limit the invention to those skilled in the art, and the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. Φ [Simplified Schematic Description] Fig. 1 is a top plan view showing an anti-fuse single-programmable non-volatile memory array 100 according to an embodiment of the present invention. 2 is a cross-sectional view showing two anti-fuse single-programmable non-volatile memory cells (memory cell_1 and memory cell_2) according to an embodiment of the present invention. - Figure 3 illustrates a method of programming a selected anti-melting, single-person programmable non-volatile memory cell in accordance with an embodiment of the present invention. 18 1289855 13064twf.doc/006 Two-figure diagram: A cross-sectional view of the programmed one-time anti-fuse single-programmable non-volatile memory cell (Figure 6, memory cell J). 5a to 5b illustrate six anti-fuse single-time volatile Z memory cells in a programmed operation wiper and a programmed operation according to an embodiment of the present invention.
八1小砀不赞昍一貫施例之反熔絲單次可編 =揮發性記憶體單元的三種編财法，其浦 法、V/2法與V/3法。 圖7緣示為本發明一實施例之一種反溶絲單次可編 記憶體單元所構成之儲存陣列在經—讀取操作時 圖8繪示為本發明—實施例之__種反熔絲單次 非揮發性儲存_在經—讀取操 = 取遺漏電流的示意圖。 〗XT預防產生項 圖9a至9g為本發明一實施例之一 程非揮發性記憶體單元的製造方法。早久可編 【主要元件符號說明】 發性儲存陣列 100 ··反熔絲單次可編程的非揮 110 :字元線 120 :位元線 130 :反熔絲 140 :厚絕緣區 210 ··基板 220 : P-摻雜區 19 1289855 13064twf.doc/006 230 :厚絕緣區 240a及240b ·· N+摻雜區 250 :多晶矽層 260 :多晶矽化金屬層 270 : N+/P-基板接合 280a、280b :反熔絲 285 :已編程區域 290 :字元線 410 · P-區塊 420 : N+區塊 910 :基板 920、920’ ： P-摻雜區 930、930’ ：厚絕緣層 940 :渠溝 950 :反熔絲 960 : N+摻雜區 970 :多晶矽層 980 :多晶矽化金屬層 Vpp :編程電壓 Vcc :讀取電壓 20Eighty-one small 砀 砀 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 昍 = = = = = = = = = = = = = = = = = = = = = = = = = FIG. 7 is a view showing a storage array formed by a single-dissolvable memory unit of an anti-solving wire according to an embodiment of the present invention. FIG. 8 is a view of the present invention. Wire single-time non-volatile storage _ in the warp-read operation = take a schematic diagram of the missing current. XT Prevention Generation Item Figs. 9a to 9g show a method of manufacturing a nonvolatile memory unit according to an embodiment of the present invention. Long-term can be edited [main component symbol description] hair storage array 100 · · anti-fuse single-programmable non-swing 110: word line 120: bit line 130: anti-fuse 140: thick insulation area 210 · Substrate 220: P-doped region 19 1289855 13064twf.doc/006 230: thick insulating regions 240a and 240b · N+ doped region 250: polysilicon layer 260: polycrystalline germanium layer 270: N+/P-substrate bond 280a, 280b : Anti-fuse 285: programmed area 290: word line 410 · P-block 420: N+ block 910: substrate 920, 920': P-doped region 930, 930': thick insulating layer 940: trench 950: anti-fuse 960: N+ doped region 970: polysilicon layer 980: polycrystalline germanide metal layer Vpp: programming voltage Vcc: read voltage 20