TWI289808B - Register-collecting mechanism, method for performing the same and pixel processing system employing the same - Google Patents

Abstract

The invention provides a pixel processing system and method. The system includes a register-collecting mechanism and a pixel coloring device. The register-collecting mechanism corrects a first program to a second program. The first program is disposed with a plurality of first registers. The second program is disposed with a portion of the first registers of the first program. The pixel coloring device executes the second program. The method includes loading the first instructions of the first program into the register-collecting mechanism; scanning the first instructions; decoding the first instructions to form the code for the first register; mapping the code for the first register to the code for the second register in the register mapping table; and correcting the first program to rearrange the code for the first register in the first program so as to form a second program with a plurality of second instructions. The invention makes use a specific amount of registers to process more pixels so as to improve the delay time for the material instruction.

Description

1289808, IX, invention description: [Technical field] The present invention relates to a scratchpad collection mechanism and method thereof, and a pixel processing system using the same and the method, and more particularly to a graphics processing A scratchpad collection mechanism of a Graphic Processor Unit (GPU) and a method thereof, and a pixel processing system using the same and the method. [Prior Art] φ Referring to Fig. 1, a block diagram of a pipeline architecture of a conventional graphics processing unit 2 is shown. The graphics processing unit 2 mainly includes a triangle setting unit 23, a pixel processing unit 24, and a depth processing unit 25, and the pixel processing unit 24 includes a pixel shader 2A and a texture unit 241 connected to the pixel shader 20 and color interpolation. Color Interp〇lator 242. The surface of the three-dimensional object is divided into a plurality of two-dimensional triangles arranged in a geometrical association and having an arbitrary size. Each triangle contains three vertices, and these vertex data are transferred to an angle setting unit 23 for outputting the parameters of the pixels to the pixel processing unit 70 24, wherein the parameters can be, for example, pixels in a triangle The position and the material coordinates of the vertices of the eleventh. The pixel processing unit 24 utilizes the material unit (Texture) depending on the position of the pixel and the vertex coordinates of the vertices.

Unit) 241 Internal = Material coordinates of the pixel, and then the material coordinates formed by the interpolation are input to the image color, 2 〇. Then the pixel shader 2 executes a load instruction, such as the teXld instruction of the DireCtX material' and returns the processed material coordinates to the label. The material ^...241 is based on the unprocessed material coordinates and the processed material holder and the material. f 7° early 241 samples the material color of the pixel in the material map, and _ $ color output to pixel coloring n 2〇. At the same time, depending on the position of the pixel and the material coordinates of the 8 1289808 vertex, the color interpolator 242 interpolates the vertex colors of all pixels and outputs the vertex colors to the pixel shader. The pixel shader 20 processes the material color and the vertex color of the pixel, and outputs the color value and the depth value to the depth processing unit 25 to form the displayed pixel color. The final color is then ejected to form the entire frame. Referring to Fig. 2, a block diagram of a pixel shader processing program in the graphics processing unit of Fig. 1 is illustrated. The pixel shader 20 mainly includes four types of registers: a general register (Γη) for storing temporary data, a material coordinate register (tn), a material number register (Sn), and a vertex color mixing register. (Vn) and the output register (〇cn)' and transfer the final converted pixel color to the depth processing unit 25. The processing flow of the pixel shader 20 mainly includes four stages: the coordinate calculation stage and the material loading stage. , color mixing stage and release stage. First, the pixel interpolated material coordinates from the material unit 241 are stored in the material coordinate register (tn). In the coordinate calculation phase, the material coordinate register (tn) and the general register (rn) are used for the interpolation of the material coordinates from the material unit 241 pixels, and the result of the calculation (the material coordinates after processing) is stored. In the general register (rn). In the material processing stage, according to the material coordinate register (tn) and the material coordinates in the general register (rn), the material load instruction is executed by the pixel shader 2, so that the material unit 241 is from the material number register ( Sn) Samples the material color in the specified material map and returns the sampled material color back to the general scratchpad (Γη). In the color mixing stage, the color of the material stored in the register (rn) and the color of the vertex from the color interpolator 242 are mixed by the pixel shader 20, and the result of the color mixing is stored in the vertex color mixing register (Vn). . In the issuance phase, the pixel shader 20 outputs the color value and the depth value to the depth processing unit 25. It should be noted that the coordinate meter 1289808 can be repeatedly combined in the P white material processing stage and the color mixing stage. The reference and control dependencies, that is, the previous instructions are used by the next instruction. After the pixel coloring = towel;; can only be executed after the first ♦ I, the execution delay time of the material loading instruction in the work and the color traits: because the delay time is much higher than the address transmission, memory access Take the giant. This delay time affects the performance of the system, which is a bit silly; #°This extended time, using the pipelined architecture to handle ν

俯 Γ : : 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在However, ‘N pixels are executed, and N sets of pixel shader instruction sets are required. ::: Medium: The scratchpad is stored in the pixel shader at the same time. Therefore, the pixel 20 of the conventional image must provide an additional register to store a significant amount of scratchpad cost to solve the problem of material load instruction delay time. In order to solve the above problem, U.S. Patent No. 5,652,774 discloses a central processing for renaming a scratchpad to reduce the cycle time required to execute an instruction. • The central processing unit includes a renamed scratchpad group to retain the previously executed register. Only " the information obtained. The renamed register group is used to execute the following instructions. These require the data to be loaded before, that is, the need to maintain the connection between the renamed register and the subsequent instructions, so it takes a long operation cycle, so that the name is temporarily changed. The memory cannot be released immediately, and the next instruction or more instructions cannot be executed. Therefore, the conventional central processing unit occupies more registers, and in the pixel processing process, the sampling step is to report complex interpolation operations, and the material is stored in the memory 'even if it is accelerated by Cache. It also takes a long period of time, especially when _S cache misses, it takes a long period of time to read the memory. 1289808 * In addition, in order to solve the above problem, another U.S. Patent No. 6,314,511 discloses a system for releasing a Renaming Register and an execution method thereof, which uses an instruction to redefine an architectural register (Architectural Register). Previously, the processor first configured a number of renamed registers to the structure register to cause the processor to execute several instructions in an out-of-order mechanism. Although the processor uses an indicator to release the renamed scratchpad, the processor uses a complex out-of-order mechanism. In other words, the instruction is fetched and decoded, and then the rename mechanism dynamically changes the scratchpad during program execution to reorder the buffer memory by the out-of-order machine, resulting in a more complicated process of renaming. Therefore, a new type of pixel processing system is needed to solve the above problems. SUMMARY OF THE INVENTION One object of the present invention is to provide a pixel processing system that processes more pixels with a specific number of registers by a scratchpad collection mechanism to improve the delay time of material instructions. Another object of the present invention is to provide a method of collecting the configuration to the pixel shader φ (4) memory 11 to process more pixels and to solve the delay time of the pixel material instructions. The pixelation system of the present invention primarily includes a pixel shader and a scratchpad collection mechanism coupled to the pixel shader. The scratchpad collection mechanism corrects the first program to two passes. The first program needs to use a specific number of scratchpads, and the second program only needs the aforementioned part of the scratchpad. The pixel shader fetches, executes the program ' and reconfigures the scratchpad in the first program to form the second program. The method of the present invention is used to collect a temporary storage 11 'the 'program' of the first & type containing a plurality of first instructions and using a plurality of 1289808 registers 'a part of the number in the pixel processing system The scratchpad is the scratchpad in use, and the other part is the unused unused scratchpad, but the unused scratchpad is occupied by the first program. The method of the present invention includes scanning a first instruction of the first program, then decoding the first instruction to obtain a plurality of registers, and then modifying the first program to a second program having a plurality of second instructions, and The second program uses only a portion of the specific scratchpad number, and another unused portion of the scratchpad is reassigned to other programs. The method of the present invention also includes providing a number corresponding to the physical register to display the number of physical registers used by the second program, and correcting the first temporary memory of the first program to correspond to the physical temporary storage. The number of II. In the preferred embodiment, (4) of the physical register is a continuous positive integer, which may be arranged in micro-elevation or power-down. The method of the present invention also includes notifying the total number of pixels processed by the pixel processing system to pixel shading. In addition, the pixel packet 3 processed by the pixel processing system of the present invention has a different pixel group, and each pixel group of the towel includes the same or a different number of pixels, and the indication value of the present invention can also indicate the pixel processing system. Which pixel group is being processed. [Embodiment] First, a block diagram of a register collection mechanism according to an embodiment of the present invention will be omitted. The temporary storage mechanism is set (4) to take the first program, and to set the data to be set to the decoding device that decodes the first program, and the collection mechanism is used to modify the first program to the second program. The second program == the number of registers is less than the number used by the first program. The first program includes a complex ^: command and has a plurality of unique registers, where the nominal register is defined as the temporary 12 1289808 stored in the first program before being processed by the processing device or the decoding device. For the sake of the device. Since the first program uses only a part of the nominal register, the other part of the named register is idle, but is occupied by the first program. For example, in Figure 4, the first program requires 16 registers, but in the first program instructions, only 4 registers r〇, ri, r3 are used to execute the program. The register nivri4 is in an interleaved state 'not used. The scratchpad collection mechanism 10 collects the idle unique scratchpads in these first programs so that the idle named registers can be effectively utilized to be reconfigured for use by more programs. The scratchpad collection mechanism 10 mainly includes an instruction scanning device U, a register pair table 12, an instruction correction device 13, and an instruction reporter 14. The instruction sweeping device 11 is configured to scan a first program having a plurality of first instructions and decode the first finger a to generate a plurality of first register numbers, the number being a unique name . The register corresponding table 12 is connected to the command scanning device n, and has a plurality of second register numbers corresponding to the first register number, wherein the second register number is a physical register number. The command correction device 13 is respectively connected to the command scanning device 11 and the register corresponding table 12 for correcting the first register number corresponding to the second register number to form a plurality of second instructions. The second program, wherein the second instruction is composed of the second temporary register number in the register corresponding table 12, and the second temporary register number is the number of temporary registers used by the second program. The indicator reporter 14 issues a quantity indication value of the second register that configures the second program. Referring to Figures 4A and 4B, a flow chart of performing a register collection mechanism in accordance with a first embodiment of the present invention is shown. At step 300, the first program is loaded into the scratchpad collection mechanism. Then, in step 301, the corresponding information in the register corresponding to the register is reset to reset the state of the corresponding data originally stored in the correspondence table 12 between the unique register number and the physical register number. Then in step 302, the finger 13 13289808 is used to make the scan command, for example, sweeping the plurality of first finger devices u ΐ撼 = broom to the last command in the first program from the _=^ mode, That is, the position of these first instructions in the instruction sweep--the first-&-sequence sweeps the cat 7 times. Then, in step 303, the step of solving the scan has been completed, so as to take the illusion of the syllabus, step 3. 3 is solved by two; In the embodiment, whether each of the unique register numbers in the corresponding table 12 corresponds to or not is stored, and when the unique register number and the register number of the temporary register number do not correspond, the new one is new. The increment corresponds to the nominal temporary storage, as shown in step 305. In step 305, the only state: = temporary number: = _ between the corresponding _ ^ proud μ should be Table 12. In the preferred embodiment of the present invention, the number of the temporary register can be, for example, a continuous positive integer, the number can be... or η' where η is the last number in the physical register number, and The number can be arranged in ascending or descending power. At step 306+, the value is sequentially indicated by the number of substantial register numbers in response to the above correspondence. When the determination is made in step 304, 'the name register number corresponds to the register corresponding to the register. . The real f scratchpad in 12 corrects the nominal register number to the physical register number to form a second instruction containing the real (four) register number to generate the second program\ as shown in step 307. Specifically, the unique register number is assigned to the existing continuous physical register number. In the embodiment, the second program is composed of a physical register number to replace the discontinuous unique register number and the second program can be used for the scratchpad or the surrounding memory. Inside. Next, in step 308, it is determined whether each of the nominal register numbers is a last name register number in an instruction of the 14th 1289808. If not, step 303 is performed to extract the next-named temporary number. Register number. After recording the (four) unique register number and finding the last-named scratchpad number of the first instruction, whether the mosquito is the last-first instruction in step 3G9, if not, executing step 302, Continue to sweep the next-first instruction of the first program in a static manner. After extracting each of the first instructions, find the last of the first _ program ^

In step 31, the number of indications that the reporter 14 issues the real f register number is not worth 'last - one consecutive physical register number is used to indicate the quantity indication value of the physical register', wherein these substantial temporary storage The device is configured for the second program, and the last-substantial scratchpad number is smaller than the last-named scratchpad number in the first program, which saves more registers. Referring to Fig. 5, the following description of the register collection mechanism ι〇 according to the present invention is performed by using the first embodiment shown in Fig. 4M4B; In this embodiment, the instructions of the first program require I6 registers, and the temporary storage 3! To r15, the first program in the first program and the list of the name register are held in the temporary Φ, ^ ^ ^ 4 隹 隹 隹 对应 对应 对应 左侧 左侧 左侧 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而 而In the crying sister's place, the right side of the table is the corresponding table. For example, in step 300, the program is loaded into the register collector 10, and then in step 30.., in the view, the register corresponding to the table 12 is cleared. The content and the number of indication values, then scan the first instruction of the first program "add 〇, Π, rls" in step 302, and then decode the other instructions in step 3. 3 and obtain the name of the mouth. The memory number r is cleared in the step 301 due to the temporary ^ ^, the hip-and-forth correspondence table 12 and the quantity indication value. When only the a 蕲 / real servant number cannot correspond to the page negative temporary storage in the register table of the register The number of the device is 305. In step 305, the physical temporary piracy code is corresponding to the only storage number, and the storage number is stored, and the corresponding state is stored in the device correspondence table 12. In step 3〇6, the number of the physical register number will not be added to the corresponding step. In step 307, the nominal register number r〇 is corrected to correspond to the physical register number r0. When the nominal register number r is not the last unique register number, the step is performed.

303, decoding the nominal register number ri of the next flute A, and correcting the nominal register number to correspond to the physical register number η, and then increasing the quantity indication value to 2.

When the unique register number ^ is processed, the physical register number ~ is generated to correspond to the second unique register number ~, and in the step, the unique register number r15 is modified to be a substantial temporary Register number η. Then in the step, since r15疋 the first instruction "add % η, ~," the last unique register number, then continue to process the next first instruction "r〇", and then in step 309 Whether the last first instruction has been processed, and then step 310 is performed. = In step 310, the quantity reporter 14 notifies that the value of the quantity indication value of 4 finally forms a second program with four physical registers, here In the embodiment, I: the program must occupy 16 registers. In other words, the scratchpad collection mechanism, the second program is modified into the second program, the second (four) only needs 4 physical temporary storage. The remaining 12 temporary registers It can be reconfigured for use by different programs. In addition to all the unique register numbers of the first instruction, the U can also decode all the unique register numbers at the same time, for example: the name of the instruction. The register numbers rQ, ri, and ~ are simultaneously in the step period. That is, after the step is judged that the unique register number is not a compilation, step 304 is performed. The first aspect according to the present invention A flow chart of the benefit collection mechanism in the example. In step 4, the 16 1289808 first program of the first instruction is loaded into the scratchpad collection mechanism. Then in step 4G1, the scratchpad correspondence table 12 is cleared. Corresponding information in the state to reset the state of the corresponding data originally stored in the corresponding table 12 between the temporary storage n number and the physical temporary register number. Then in step 402, the command_device n is used to statically sweep the data. All the first instructions in the first program. Then in step 4G3, the first instruction of the swept heart is decoded to form a plurality of unique register numbers, and the configuration is assigned to the first program. The total number of registers. Next, in step Yang, the setup-scratchpad correspondence table 12, the temporary storage n correspondence table 12 mainly includes a plurality of total numbers corresponding to the above-mentioned nominal registers. Then in step 4〇5 Determining whether each of the unique register numbers corresponds to the number of the physical register stored in the register corresponding table 12. When the determination is made in step 405, the unique register number corresponds to the register corresponding to the register. The physical register in Table 12 Step 4〇6 is executed to record the correspondence between the unique register number and the physical register number. Then, in step 407, the quantity indication value of the physical register number is incremented. Then, in step 408, it is determined. Whether each unique register number is the last unique register number in a first instruction, and if not, step 4〇5 is performed. In step 405, the unique register number and the temporary register are executed. If there is no corresponding physical scratchpad number in Table 12, there is no corresponding unique register number stored in the memory of the scratchpad collection mechanism. If the last name is determined in step 4〇8 The register number is executed in step 41. In step 41, except that the unique register number is the same as the physical register number, it will be stored in the memory of the scratchpad collection mechanism. The nominal register number corresponds to the physical register number in a random or sequential manner. Then step 411 is executed to increase the quantity indication value of the physical register number. The nominal register number is then modified to the physical register number, as shown in step 412, 17 1289808. Then, in step 41"', the quantity indication value of the physical register is issued. Finally, in step 414, a second program that can be executed is generated. Referring to Figure 7 'showing a block diagram of the scratchpad collection mechanism according to the present invention' A flowchart of executing the first program scratchpad collection mechanism by using the first embodiment shown in FIGS. 6A and 6B. In this embodiment, the first program instruction occupies a unique register, the first program The first register in the first instruction is in the left row of the wire 12, and the physical register series is in the right row of the register corresponding table 12.

The first program is modified to the second program, and the remaining 29 registers are in the other way. In other words, the scratchpad collection mechanism is 1〇, and the second program only needs a substantial temporary storage new configuration for different programs. ^Steps are complete, the first program containing the first instruction is loaded into the scratchpad mechanism. After that, in the step, the pair 2 in the register corresponding to the register is cleared. In order to reset the state of the corresponding data originally stored in the corresponding temporary storage device ^ temporary storage number in the corresponding table 12. Connected, real negative

Let _device η sweep (4) in the static mode, and use the finger, in step 403, to solve the command of the broom that has been completed. However, the first program with a total number of 6 is temporarily stored: in the temporary = correspondence table 12, the consecutive supervisor numbers of the six unique register numbers are also included, for example, from number i to number 6. (4) In step _ = quality register 2 (10) should be in the register of the register corresponding to the physical temporary storage = name register step 4. 6' to record the name of the register. The correspondence between the second and the second ri’s. Then in step 4〇7, the value of the actual (4) number is added and then the step is performed. When the number of the named temporary device is the last-named register number in the instruction, the execution is performed. Step 2 18 1289808 The name register numbers r2 and f5 correspond to the physical register numbers r2 and ι·5 in the register corresponding table 12. In step 408, the nominal register number r15 is the last unique register number corresponding to the physical register number. In step 405, when the nominal register numbers r8, r1G, and r35 do not correspond to the physical register numbers in the register corresponding table 12, step 409 is executed, and the unique register numbers r8 and r35 are executed. Temporarily stored in the memory of the scratchpad collection mechanism. In step 408, when the nominal register number r15 is the last unique register number corresponding to the physical register number, step 410 is performed. In step 410, in addition to the physical register numbers η, r2, and r5, the unique register numbers r8, ri, and r35 are correspondingly mapped to the physical register in a random or sequential manner. Number r8, and r35. Then, in step 411, the quantity indication value of the physical register number is increased to 6. The nominal register number is then modified to the physical register number to produce a second program having a physical register number, as shown in step 412. Then in step 413, the value of the physical register is indicated by a value of 6. Finally in step 414, a second program is executed that can be executed. Those skilled in the art will appreciate that the scratchpad collection mechanism 10 can be implemented, for example, in a hardware or software manner. When implemented in software, the scratchpad collection mechanism 10 can be a software utility program, a Program Loader, or a driver attached to a computer peripheral device of the program compiler being executed in the computer operating system. In the preferred embodiment, when implemented in a hardware manner, the scratchpad collection mechanism 10 is coupled to the program capture unit or the decoding unit, that is, before the instruction sorting unit 201 and the decoding unit 203 of the pixel shader 20, Or the scratchpad collection mechanism 10 is integrated into the pixel shader 20. The scratchpad collection mechanism 10 increases the availability of the physical scratchpad for pixels, primarily by re-generating the simplified second program by statically scanning the first program on 19 1289808. The pixel shader 20 of the present invention is defined in the DirectX specification. It should be noted that the Fragment Processor defined by the OpenGL protocol is also applicable to the present invention' and similar pixel shading systems are also applicable.

Referring to Figure 8, a pixel processing system using a scratchpad collection mechanism in accordance with one embodiment of the present invention is illustrated. The scratchpad collection mechanism 10 corrects the first program to the second program, by collecting the unique register configured to the first program, to reduce the register occupied by the first program, and making the pixel processing system specific The number of scratchpads to handle more pixels. The pixel management system is primarily for a graphics processing unit (GPU), including a pixel shader 20 and a scratchpad collection mechanism 10 coupled to the pixel shader 20. The pixel shader 20 mainly includes an instruction sorting unit 201, a program counter 202, a decoder 203, a plurality of registers 204, and an Arithmetic Logic Unit (ALU) 205. The instruction sorting unit 201 receives the second program from the scratchpad collection mechanism ι, and the program counter 202 retrieves the instructions of the second program from the instruction sorting unit 2〇1, and then the decoder 203 decodes the extracted instructions. The arithmetic logic unit 2〇5 controls the step of binding the decoded instruction, and the indicator 14 of the register collection mechanism 1 sends a quantity indication value of the register configuring the first program to the pixel shader to make the pixel processing system 1GG reconfigures the idle unused unused temporary storage in the first program according to the number $ indication value to other silent use, that is, the pixel processing system 100 of the present invention temporarily stores the crying goods with a minimum amount of substance. To execute the second program to simultaneously process the number of unique register registers defined in the first program input to the temporary program, and define the number of registers as r, and before the 1_mechanism collection mechanism 10, configure the first r, and the ratio i between the actual temporary allocations assigned to the second program is defined as r/r', used to use the state of the register of the second program of Table 20 1289808, where! For integers, # ‘軚佳. Taking the processing pixel as an example, when processing the first program, the pixel color 1 § 20 can only process 像素 pixels, and can be added to iN pixels after the processing of the register collecting mechanism 10 of the present invention. Referring to Fig. 9, a system 1 will show a pixel processing system using a scratchpad collector in accordance with another embodiment of the present invention. The pixel shader (9) uses a particular number of registers to execute the first program to process the pixels. The scratchpad collection mechanism 10 corrects the program to the second program. Since the second program only needs to use the original half (four), the other half of the temporary storage can be configured for use by another pixel. Therefore, in this embodiment In the pixel processing system, the number of processing for pixels is increased to 2 。. It should be appreciated that the indication value issued by the indicator reporter to the pixel shader 20 can be the number of physical registers required by the second program or the total number of pixels processed in the pixel processing system 1〇〇. When the pixel processed by the pixel processing system i 包含 includes a plurality of different pixel groups, wherein each pixel group contains pixels of the same or different numbers, the indication value of the present invention may also indicate the pixel processing system.哪 Which pixel group is being processed. While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the pipeline architecture of a conventional graphics processing unit. FIG. 2 is a block diagram showing the processing of the program using the pixel shader 21 1289808 in the graphics processing unit of FIG. 1. Figure 3 is a block diagram showing one of the present invention. 4A and 4B of the scratchpad collection mechanism of the embodiment illustrate a flow chart of a collection mechanism in accordance with the present invention. The execution flow of the first program register collection mechanism is implemented in the first embodiment of the embodiment.

The sixth and eighth prints show a flow chart of the first actual collection mechanism in accordance with the present invention. Figure 7 is a block diagram showing a scratchpad collection mechanism in accordance with the present invention, which is a flow chart for executing the first program scratchpad collection mechanism using the first embodiment shown in Figures 6 and 6. μ Figure 8 is a diagram showing a pixel processing system using a scratchpad collection mechanism in accordance with one embodiment of the present invention.

Figure 9 is a diagram showing a pixel processing system using a scratchpad collection mechanism in accordance with another embodiment of the present invention. 10 register collection mechanism 12 register correspondence table 14 indicator reporter 23 triangle setting unit 25 depth processing unit 201 instruction sorting unit [main element symbol description] 2 graphics processing unit 11 instructs the scanning device 13 to instruct the correcting device 20 pixel coloring 24 pixel processing unit 100 pixel processing system 22 1289808 202 program counter 203 204 register 205 241 material unit 242 decoder arithmetic logic unit color interpolator

twenty three

Claims (1)

1289808 X. Patent application scope: 1 · A pixel processing system, comprising at least: a scratchpad collection mechanism for modifying a first program into a second program, wherein the first program is provided with a plurality of first registers And the second program is part of the first register of the first program; and / / a pixel shader connected to the register collection_, fetching and executing the second program to reconfigure another A portion of the first, gg . . X- t η 3 4 is configured to be used by different programs. The pixel processing system of claim 1, wherein the pixel chromophore includes at least one instruction storage memory for storing the second s. The pixel processing system, wherein the two register collection mechanism is disposed in the input memory of the instruction storage memory, and is configured to be configured to the temporary program of the first program. Do not use a pixel processing system as described in item 1 of the patent scope, wherein the program contains at least a plurality of first instructions, and the first: "named register. 7, a plurality of |=Please apply the pixel processing described in item 4 of the patent (4), where 兮 = =: system contains at least - refers to TM'-::: 6 · The pixel processing as described in item 5 of the patent application makes the broom device sequentially Scan the second, 'where the finger' in the first program. The second brother - the static bit of the instruction. 7. The pixel processing as described in claim 5 of the patent application causes the broom to simultaneously scan the first of the first programs. Second - the static bit of the instruction 24 1289808 8 · If the patent collection scope storage mechanism contains at least The W I correction device is respectively connected to the command device and the register correspondence table for correcting the first temporary storage number corresponding to the second temporary register number to form a second with a plurality of second instructions The program, wherein the second fingers 7 are composed of the second temporary H number in the temporary storage correspondence table. The pixel processing system of claim 1, wherein the first processing unit of the first instruction is configured by a plurality of configurations. The first pass (four) is a temporary register. The pixel processing system of claim 9, wherein the second register number is a plurality of physical register numbers assigned to the second program. The pixel processing system of claim 10, wherein the register is corresponding to the second register of the towel as a continuous number. 12. The pixel processing system of claim 2, further comprising an indication reporter for issuing a quantity indication value of the second temporary register configured with the second program. The pixel processing system of the item, wherein a last number in the second register having consecutive numbers is equal to a quantity indication value of the second register, and the last number is equal to the first finger 1289808 The total number of first registers of the order. Quantity 2 =: The pixel processing system of claim 12, wherein the value is not the total number of second registers allocated to the second program. Production and drying, please refer to the pixel processing system described in item 12 of the patent scope. Reading the total number of pixels processed by the pixel processing system, for example, the pixel processing system described in claim 8 of the patent application, the temporary storage 15 collection mechanism is selected from the computer (4) system is executing the software ^: Additional to the program's power (10) 17. - The implementation of the scratchpad collection mechanism in the pixel processing system includes at least the following steps: Mechanism: The first program with a plurality of first instructions is loaded into the register for collection Scanning a first instruction located in the first program; decoding the first instruction to form a first register number; and assigning the first register number to a register corresponding table number; I correcting the first program to reconfigure a portion of the first register number ' of the first program to form a second program having a plurality of second instructions, wherein the other portion of the first register number is The configuration is not used by the program in the pixel shader, and the second register number of the second program is located in the skew table. $什斋对 18. The method of claim 17, in the method of scanning the first instruction in the program, further includes clearing the contents of the register corresponding table 26 1289808. 19. The method of claim 17, further comprising determining whether the first register number corresponds to a server number stored in the register corresponding to the register. The method of claim 19, wherein the step of scanning the first instruction in the first private mode further comprises sequentially scanning the static positions of the first instructions in the first program. 21. The method of claim 17, wherein when the first temporary device number is not identical to the second temporary register number stored in the register corresponding to the register, Further includes a re-mosquito-second register number to the second register number. 22. The method of claim 21, wherein in the step of reassigning another second register number to the second register number, the first register number and the second temporary storage The n-form _ corresponding g is stored in the register pair 23, as described in claim 22, The first = deposit (four) physical scratchpad grades are consecutive positive integers and; t consecutive numbers are arranged in ascending power. 24. The method of claim 23, wherein the second number in the second register is equal to the number indication value of the second program of the second program. 2^ The method of claim 24, further comprising issuing a configuration indicating the value of the second register of the first program to the pixel shader. In the step of decoding the first instruction, the method of decoding the first instruction includes forming the first register number. 27 1289808 Decoded: The method described in item 26, for the total number of values for the first instruction. &Package 3 obtains the configuration of the first register to the first program 28. As shown in the application scope of the 27th item of the patent scope, "including the establishment of the temporary register, ^ Qian μ containing Wei (four) should The first temporary q, the second register of the heart value. The method of claim 27, wherein the first temporary phase == is stored in the register of the register When the second register number is not=corresponding, it further includes the non-seven _th-storage register number set τ in the memory of the register corresponding table. 30. As described in claim 29 The method further includes reassigning the first register number that cannot be corresponding to the memory to the second register number in the register corresponding to the second register number corresponding to the corresponding register number: 3 The method of claim 17, further comprising notifying the total number of pixels processed by the pixel processing system.