TWI289325B - Planar double-gate transistor and method for fabricating a planar double-gate transistor - Google Patents
Planar double-gate transistor and method for fabricating a planar double-gate transistor Download PDFInfo
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1289325 五、發明說明(1) 【發明所屬之技術領域] 本發明與一種平坦化雙閘極電晶體,以及一種製造平 坦化雙閘極電晶體的方法有關。 【先前技術】 隨著矽技術中,傳統平坦化氧化金屬半導體場效電晶 體(MOSFETs )尺度的進步,該各自組件的效能則尤其受 到短通道效應所明顯影響。不希望的短通道效應像是:當 該閘極電壓增加時,在該汲極電流中的削弱增加,與該操 作點上門檻電壓的相關性,以及從該源極區域與汲極區域 φ的衝穿。 該雙閘極電晶體的組成,可能避免在此尺度中,來自 短通道效應所可能發生及產生限制的難處。如果該主動區 域’換§之該源極/汲極區域與該通道區域的範圍,是製 成有效的薄,短通道效應可以利用控制兩閘極或一圍繞閘 極的方式大大減少。因此,該雙閘極電晶體代表了 一種兆 位元整合基本元件的候選者。然而,可以用於製成一雙閘 ‘極電晶體,並以利用一簡單方式所實施的製造技術尚未建 立。 對於製造雙閘極電晶體而言,有許多概念被討論及測 。這些概念像是垂直電晶體、鰭型電晶體、或是具有一 替代閘極的平坦化結構。然而,這些所有的概念都使用複 雜的處理,其對於矽技術中的製造工程而言,到目前為止 都未被嘗試與測試。該總體製造處理也是複雜且昂貴。此 外’對一垂直電晶體而言便沒有產生該各自區域(例如間1289325 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to a planarized double gate transistor and a method of fabricating a flat double gate transistor. [Prior Art] With the advancement of the conventional planarization of oxidized metal semiconductor field effect transistors (MOSFETs) in the germanium technology, the performance of the respective components is particularly affected by the short channel effect. An undesirable short channel effect is as follows: as the gate voltage increases, the attenuation in the drain current increases, the correlation with the threshold voltage at the operating point, and the source region and the drain region φ Punch through. The composition of the double gate transistor may avoid difficulties in this scale that may occur from the short channel effect and create limitations. If the active region's the source/drain region and the region of the channel region are effectively thin, the short channel effect can be greatly reduced by controlling the two gates or a surrounding gate. Therefore, the dual gate transistor represents a candidate for a megabit integrated basic component. However, it can be used to make a double gate 'polar transistor, and the manufacturing technology implemented in a simple manner has not been established. There are many concepts discussed and tested for the manufacture of double gate transistors. These concepts are like vertical transistors, fin-type transistors, or flattened structures with an alternative gate. However, all of these concepts use complex processing that has not been tried and tested so far for manufacturing engineering in the technology. This overall manufacturing process is also complicated and expensive. In addition, the respective regions are not produced for a vertical transistor (for example,
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區域電流的損 極)的平坦化表面’因此造成流通過該各自 失0 此外,在製造平坦化雙閘極電晶 製造期間所需要的高度複雜方法步驟=問冑,是在其 體的尺寸是被進-步減少,對於該眾多古:该雙閘極電晶 之一、i知士协灿仏 承夕间度複雜製造步驟 : 且成摻雜物之-’例如產生源極區域與汲極區域 的方法令,將增加精確定位控制的要求。特別是在後續中 從該源極/汲極區域,擴散摻雜物至通道區域中,將造成 一主要問題。 _ 在製造平坦化雙閘極電晶體中的另一困難處,是確保 兩個別電極的正確對齊,換句話說,其必須確保兩電晶體 閘極彼此之間,是以一種固定的空間關係配置。在一種平 坦化雙閘極電晶體的情況中,該電晶體的兩閘極,是該電 晶體通道區域兩側上的基板相同位置處,將其十之一配置 在另一之上,其配置於該源極終端與汲極終端之間。換句 活說’该通道區域是配置在兩閘極之間。一般突出的閘極 長度是介於大概10奈米至20奈米之間的範圍,因此產生正 ^確對齊的高度要求。 DE 1 02 23 709 A1公開一種製造雙閘極電晶體的方 %,其在一第一晶圓的矽絕緣體上形成一電晶體,並在其 上形成一平坦表面。此外,在該第一晶圓的平坦表面上龜 合一第二晶圓,且在該矽絕緣體中,在該第一閘極區域董 面形成一第二閘極區域。 、 US 2002/0 1 05039 A1公開一種製造雙閘極電晶體的方The flattened surface of the region current's damage pole' thus causes the flow to pass through the respective losses. Furthermore, the highly complex method steps required during the manufacture of the planarized double-gate electro-optic crystal = the problem is that the size of the body is Being reduced by step-by-step, for this multi-old: one of the double-gate electro-crystals, i knows the singularity of the complex manufacturing steps: and into the dopant - 'for example, the source region and the bungee Regional method orders will increase the requirements for precise positioning control. Especially in the subsequent source/drain regions, diffusion of dopants into the channel region poses a major problem. _ Another difficulty in the fabrication of flattened double-gate transistors is to ensure proper alignment of the two other electrodes. In other words, it must ensure that the two transistor gates are in a fixed spatial relationship with each other. Configuration. In the case of a planarized double gate transistor, the two gates of the transistor are at the same position on the substrate on both sides of the transistor channel region, and one of the eleven is disposed on the other, and the configuration thereof Between the source terminal and the drain terminal. In other words, the channel area is placed between the two gates. The generally prominent gate length is in the range of between about 10 nm and 20 nm, thus creating a height requirement for positive alignment. DE 1 02 23 709 A1 discloses a method of manufacturing a double gate transistor which forms a transistor on a tantalum insulator of a first wafer and forms a flat surface thereon. In addition, a second wafer is bonded to the flat surface of the first wafer, and a second gate region is formed on the first gate region of the germanium insulator. US 2002/0 1 05039 A1 discloses a method for manufacturing a double gate transistor
法, 具有 域。 Ϊ289325 其具有前方多閘極與後方佈植區域 矽薄層的兩閘極介電質:兩閘極疋 具中則做為通道區 【發明内容】 本發明是基於提供一種平坦化雙 :及-種製造平坦化雙閑極電晶體的簡單=體=兄 況中隶m 係技術方法步驟,且在該情 中了達成一種兩閘極彼此之間的精確對 此問題是利用該平坦化雙閘極電晶體,以^ 一猶且有 •方1 ί二!請專利範圍特徵的平坦化雙閑極電晶體“造 乃去所解決。 在,據本發明的方法中,在一第一晶圓的矽絕緣體基 反上,定義一主動區域,接著在該第一晶圓的矽絕緣體基 反^ ’形成一第一閘極區域,而源極/汲極區域是在該主 動區域中,以一種利用矽與鍺製成材料層的方式所形成, 在源極/汲極區域之間剩餘的矽層,則明確地做為一通道 ‘區域。下一步驟是從該第一晶圓矽絕緣體基板的矽層,形 成一通道區域,之後在該矽絕緣體基板、該源極/汲極區 域與該第一閘極區域之上,形成具有一平坦表面的層。一 H 一晶圓是被黏合至該第一晶圓的平坦表面,並接著在該 第一閘極區域對面,形成一第二閘極區域。 ~平坦化雙閘極電晶體具有一源極區域與一汲極區 域’配置在該源極區域與汲極區域之間的通道區域,以及 精確配置在該通道區域的互相對面侧上的兩閘極。此外,Law, with domain. Ϊ289325 A two-gate dielectric having a thin layer of a front multi-gate and a rear implanted area: a two-gate cooker as a channel area. SUMMARY OF THE INVENTION The present invention is based on providing a flattening double: and - A simple method of fabricating a flattened double idler transistor, in which the method is followed by a technical method step, and in this case, achieving a two-gate polarity with respect to each other is the use of the flattening double gate Polar crystal, to ^ one and still have a square 1 ί two! In the method of the present invention, an active region is defined on the reverse side of the first insulator of the first wafer, and then in the first method. A germanium insulator base of a wafer forms a first gate region, and a source/drain region is formed in the active region by a layer of material made of tantalum and niobium, at the source The remaining germanium layer between the drain regions is explicitly used as a channel 'region. The next step is to form a channel region from the germanium layer of the first wafer germanium insulator substrate, and then on the germanium insulator substrate, Forming a layer having a flat surface over the source/drain region and the first gate region. An H-wafer is bonded to a flat surface of the first wafer, and then at the first gate Opposite to the pole region, a second gate region is formed. ~ The planarized double gate transistor has a source region and a drain region 'a channel region disposed between the source region and the drain region, and precise configuration On the opposite side of the channel area Two gates. In addition,
第8頁 1289325 五、發明說明(4) 該源極區域與沒極區域具有一種石夕與鍺所混合的材料,而 鍺的比例較佳的是介於原子比例為20 %與4〇 %之間。較佳 的是,該源極區域與汲極區域額外具有做為材料的碳。 以根據本發明的方法,可利用簡單及節省成本=方 式,以矽技術的已知方法步驟製造平坦化雙閘極電晶體, 其也可能有效地避免該摻雜原子擴散進入該通道區2。 、該獨立申請專利範圍顯示則本發明的較佳發展γ與形 成一雙閘極電晶體的方法有關的較佳發展,也可應用於根 據本發明的平坦化雙閘極電晶體。 修較佳的是,該矽鍺層具有額外的碳材料。這可容 解從該源極/汲極區域所形成的層,是由矽鍺碳〃 也就是說一種矽錯碳層。 、 以根據本發明的方法,可利用簡單及節省成本的方 ::以:夕技術的已知方法步驟製造平坦化雙閘極電晶體, :可,有效地避免該摻雜原+擴散進入該通道 Γ二:Π碳層(SiGe:c層)以形成該麟及極區 方面製造方法簡4匕’並可更彈性地進行,因為,- 的通i區ί效= ί雜物擴散進入該雙閘極電晶體 鲁面,已知=之:::在另- 驟與:製造方法所選用餘:二=度其造成_步 、夕錯所製ϊξ:料由帶有少量碳的 子比例介於例如2_二::::;:定=外=原」Page 8 1289325 V. Description of the invention (4) The source region and the non-polar region have a material mixed with a stone and a sputum, and the ratio of strontium is preferably between 20% and 4%. between. Preferably, the source region and the drain region additionally have carbon as a material. With the method according to the invention, a planarized double gate transistor can be fabricated using known method steps of the technique, using simple and cost effective methods, which may also effectively prevent diffusion of the dopant atoms into the channel region 2. The independent patent application scope shows that a preferred development of the preferred development of the present invention in relation to a method of forming a double gate transistor is also applicable to a planarized double gate transistor according to the present invention. Preferably, the layer of tantalum has additional carbon material. This can accommodate the layer formed from the source/drain region, which is a carbon-germanium layer, that is, a layer of faulty carbon. With the method according to the present invention, a simple and cost-effective method can be utilized: manufacturing a planarized double gate transistor by a known method step of: a technology, can effectively avoid the doping + diffusion into the Channel Γ 2: Π carbon layer (SiGe: c layer) to form the lining and polar regions manufacturing method can be more flexible, because, - the pass zone i effect = ί debris diffusion into the Double gate electrode crystal ramen, known =::: in another - step and: manufacturing method selected use: two = degree caused by _ step, eve error: material by a small amount of carbon with a sub-proportion Between for example 2_2::::;:定=外=原"
1289325 ---__ .五、發明說明(5)' ' •小$例的碳,較佳的是介於2 %至5 %之間的原子比例。石夕 f 乂可以存在為一種結晶結構,在此情況中是一種石夕結 -晶’其中某些矽原子由鍺原子所取代,並在其中结合一小 量的碳。 ° 、較佳的是,該矽絕緣體基板的絕緣體是由氧化矽所製 成’氧化矽可瞭解意指二氧化矽(S i 〇2 )。 在一發展中’在定義該主動區域的情況中,一種對應 該主動區域的平台結構,是從該第一晶圓矽絕緣體基板的 石夕層所形成。 φ 此清楚的意指該矽絕緣體基板矽層的部分區域,換+ 之,該矽絕緣體基板的上層,是以蝕刻方式所移除,而; 些對應於該定義主動區域的矽絕緣體基板矽層的部分區 域,則剩餘在該絕緣層之上。這些剩餘部分區域形成一種 結構,其與一種臺座或表袼類似,因此清楚地指為一種平 台結構。因此,形成該平台結構,牵涉到移除該矽絕緣體 基板的矽層,·以及將下方絕緣層變為未覆蓋,其較佳地是 以氧化矽(S1 〇2 )形成,之後在其上方將應用其他層。 較佳的是,在該第一晶圓的矽絕緣體基板上, 該平台結構所覆蓋的區域中,形成一第一絕緣層,該一 b緣層具有與該平台結構矽層的相同厚度。 此清楚的意指-絕緣層,較佳的是由氮化石夕 製成,並形成於未由矽平台結構所覆蓋的區域之中,^ 是說該平台結構完全地由具有與該矽層相同厚度的絕緣層 圍繞其周目。此絕緣層可以做為在猶後㈣步驟中的餘刻1289325 ---__ . V. Description of the invention (5) ' ' • Small carbon carbon, preferably between 2% and 5% atomic ratio. The stone f f 乂 can exist as a crystalline structure, in this case a diarrhea-crystal where some of the ruthenium atoms are replaced by ruthenium atoms and a small amount of carbon is incorporated therein. Preferably, the insulator of the tantalum insulator substrate is made of yttrium oxide. The yttria is understood to mean cerium oxide (S i 〇 2 ). In a development, in the case of defining the active region, a platform structure corresponding to the active region is formed from the layer of the first wafer germanium insulator substrate. φ This clearly means that a portion of the germanium insulator substrate layer is replaced, and the upper layer of the germanium insulator substrate is removed by etching, and the germanium insulator substrate layer corresponding to the defined active region A portion of the area remains above the insulating layer. These remaining partial regions form a structure similar to a pedestal or watch, and thus are clearly referred to as a platform structure. Therefore, the formation of the platform structure involves removing the germanium layer of the germanium insulator substrate, and changing the underlying insulating layer to uncovered, which is preferably formed by yttrium oxide (S1 〇2), and then above it. Apply other layers. Preferably, on the germanium insulator substrate of the first wafer, a first insulating layer is formed in a region covered by the platform structure, and the b-edge layer has the same thickness as the germanium layer of the platform structure. This clearly means that the insulating layer, preferably made of nitride nitride, is formed in a region not covered by the crucible structure, so that the platform structure is completely identical to the crucible layer. The thickness of the insulating layer surrounds its circumference. This insulating layer can be used as a remnant in the step of (II)
第10頁 J289325 五、發明說明(6) 終止層,並可以有效地在該平坦化雙閘極電晶體的兩閘極 • 區域之間形成絕緣,也就是說,用於將兩閘極區域彼此電 力去搞。特別的,該通道區域也利用該絕緣層的方法,與 該閘極區域及該源極/汲極區域絕緣。 在一發展中,在該矽絕緣體基板上的第一閘極區域形 成’具有以下的步驟··在該矽絕緣體基板上形成一第一閘 極絕緣層,並且形成並圖樣化在該第一閘極絕緣層上,由 一種電傳導材料所製成的第一層。此外,以非電傳導材料 部分地封裝該第一閘極區域。 φ 來自於該第一閘極絕緣層上層的電傳導材料,較佳地 是在該第一閘極區域後續形成之後,由多矽所形成。該第 一閘極區域的封裝,也就是說由傳導材料所製成的第一 層,可以由氧化矽及/或氮化矽所形成。該多矽可以在一 額外的子步驟中摻雜。 該第一閘極絕緣層較佳地可以從將該第一晶圓矽絕緣 體基板的矽層部分氧化所產生的氧化矽所形成。 , 利用較佳的熱處理方法,將該矽絕緣體基板的矽層部 分氧化的方式’形成一氧化矽層,對於形成一閘極絕緣層 Λ來說是更加有效的。 在發展中’該源極/沒極區域的形成,具有以下的 步驟··圖樣化該第一晶圓矽絕緣體基板的未覆蓋區域,將 該第一閘極區域的封裝使用為一遮罩,並將該第一絕緣層 圖樣化。此外,圖樣化該第一晶圓矽絕緣體基板的絕緣 層’並形成該源極/沒極區域的石夕錯碳層。Page 10 J289325 V. Description of the invention (6) Termination layer, and can effectively form insulation between the two gates of the flattened double gate transistor, that is, for the two gate regions to each other Power to engage. In particular, the channel region is also insulated from the gate region and the source/drain region by means of the insulating layer. In a development, the first gate region on the germanium insulator substrate is formed with the following steps: forming a first gate insulating layer on the germanium insulator substrate, and forming and patterning the first gate On the pole insulating layer, a first layer made of an electrically conductive material. Additionally, the first gate region is partially encapsulated with a non-electrically conductive material. The electrically conductive material from the upper layer of the first gate insulating layer is preferably formed of a plurality of turns after the subsequent formation of the first gate region. The encapsulation of the first gate region, that is, the first layer made of a conductive material, may be formed of tantalum oxide and/or tantalum nitride. The polysaccharide can be doped in an additional substep. The first gate insulating layer is preferably formed of yttrium oxide generated by partial oxidation of the tantalum layer of the first wafer-on-insulator substrate. The use of a preferred heat treatment method to form a tantalum oxide layer by oxidizing the tantalum layer portion of the tantalum insulator substrate is more effective for forming a gate insulating layer. In the development, the formation of the source/drain region has the following steps: patterning the uncovered region of the first wafer 矽 insulator substrate, and using the package of the first gate region as a mask, And patterning the first insulating layer. Further, the insulating layer ' of the first wafer-on-insulator substrate is patterned and the carbon-deposited carbon layer of the source/drain region is formed.
1289325 五、發明說明(7) ' 該石夕鍺碳層較佳的是從Sil xGexCy所形成,其中χ的數值 較佳的是位於0.2至0.4的範圍之間,而乂的數值較佳的是 位於0. 02至0· 05之間。 使用該第一閘極區域的封裝做為一遮罩,以圖樣化該 未覆蓋矽層,使其可能確保在一種簡單的方式中,於後續 形成的第一閘極區域,精確地位於該第一閘極區域下方, 也就是說’該加工方式是自我對齊的。 在後續的蝕刻步驟期間,該源極/汲極區域的矽鍺碳 層可以做為一触刻終止層。適當的蝕刻劑,對於矽鍺碳層 φ需具有選擇性’像是EDP (ethylene diamine pyrocatechol) 、TMAH (tetramethylammonium hydroxide)、氫氧化鉀(KOH,potassium hydroxide) 或膽鹼(cho 1 i ne )。高度的選擇性會使鍺的比例多於 20 % 〇 該矽鍺碳層的形成,可以使用選擇性磊晶的方式進 行。 選擇性磊晶利用達成該矽鍺碳層或矽鍺層的良好形成 控制的方式,而建構成一種方法,也就是說,藉由範例, 沈積層的厚度可以被非常正確地定義。此外,其可能考慮 該各自層的晶格方向,也就是說在一層形成本身以及在 其上所形成的第二層。 具有一平坦表面層的形成,可以利用在该源極/汲極 區域與該第一閘極區域上,該矽鍺碳層上的非電傳導材料 製成的一平坦第一層的形成方式實施。1289325 V. INSTRUCTIONS (7) 'The carbon layer of the stone is preferably formed from Sil xGexCy, wherein the value of χ is preferably between 0.2 and 0.4, and the value of 乂 is preferably It is located between 0.02 and 0. 05. Using the package of the first gate region as a mask to pattern the uncovered layer, making it possible to ensure that in a simple manner, in the subsequently formed first gate region, exactly Below a gate area, that is to say 'the processing method is self-aligned. The carbon layer of the source/drain region may serve as a etch stop layer during subsequent etching steps. A suitable etchant is required to have selectivity for the tantalum carbon layer φ such as EDP (ethylene diamine pyrocatechol), TMAH (tetramethylammonium hydroxide), potassium hydroxide (KOH) or choline (cho 1 i ne ). The high selectivity makes the proportion of niobium more than 20%. The formation of the niobium carbon layer can be carried out by selective epitaxy. Selective epitaxy is constructed by a method of achieving good formation control of the tantalum carbon layer or tantalum layer, that is, by way of example, the thickness of the deposited layer can be defined very accurately. Furthermore, it is possible to consider the lattice orientation of the respective layers, that is to say the formation itself and the second layer formed thereon. Forming a flat surface layer may be performed by forming a flat first layer of non-electrically conductive material on the germanium carbon layer on the source/drain region and the first gate region .
第12頁 .1289325 ^ 五、發明說明(8) 由於該表面的平坦化,之後在一後續晶圓黏合步驟 中,可以更容易地黏合一第二晶圓。該平坦化較佳的是以 。化學機械研磨法的方式實施。此外,在該平坦化之後,可 以實施一種化學及/或電漿活化步驟,藉此該後續的晶圓 ,黏合步驟可以更簡單有效的進行。以非電傳導材料製成的 第一層較佳的是由氧化石夕所製成。 在一發展中’違第二閘極區域的形成具有以下的步 驟:圖樣化該矽絕緣體基板的絕緣體與該矽絕緣體基板, 並將該矽絕緣體基板的矽層變為未覆蓋,以及從該矽絕緣 肇體基板矽層上的非傳導薄層,形成一閘極絕緣層。此外, 在由該源極/汲極區域矽鍺碳層製成的層上,形成一第二 非傳導薄層,並形成由一種非傳導材料製成的第二側壁 層0 該第二侧壁層的材料較佳的是氮化石夕及/或氧化石夕。 該非傳導薄層較佳的是利用將該矽絕緣體基板及該源極/ 汲極區域矽鍺碳層製成的層氧化所形成。 該矽層的氧化提供一種簡單的方式,以形成做為絕緣 的氧化矽層。利用將該源極/汲極區域的矽錯碳氧化方 ^,所形成的該非傳導薄層,可以做為一種在佈植摻雜物 霉月間,避免或至少減少摻雜物擴散的層。 車父佳的是’該第二閘極區域的形成,另外具有以下的 步驟:在該閘極絕緣層上,形成由一種電傳導材料製成的 第二層,對該源極/汲極區域的矽鍺碳層進行回韻,<以及 在該石夕絕緣體基板的完整晶圓上,形成一鈍態層,並將其Page 12 .1289325 ^ V. INSTRUCTION DESCRIPTION (8) Due to the planarization of the surface, a second wafer can be more easily bonded in a subsequent wafer bonding step. This planarization is preferably performed. The chemical mechanical polishing method is implemented. In addition, after the planarization, a chemical and/or plasma activation step can be performed whereby the subsequent wafer, bonding step can be performed more simply and efficiently. The first layer made of a non-electrically conductive material is preferably made of oxidized stone. In a development, the formation of the second gate region has the following steps: patterning the insulator of the germanium insulator substrate and the germanium insulator substrate, and changing the germanium layer of the germanium insulator substrate to uncovered, and from the germanium A non-conductive thin layer on the insulating germanium substrate layer forms a gate insulating layer. Further, on the layer made of the source/drain region carbon layer, a second non-conductive thin layer is formed, and a second sidewall layer 0 made of a non-conductive material is formed. The material of the layer is preferably nitrite and/or oxidized stone. Preferably, the non-conductive thin layer is formed by oxidizing a layer of the tantalum insulator substrate and the source/drain region carbon layer. Oxidation of the ruthenium layer provides a simple way to form a ruthenium oxide layer as an insulator. The non-conductive thin layer formed by the erroneous carbon oxidation of the source/drain region can be used as a layer to avoid or at least reduce dopant diffusion during implantation of the dopant mold. The father of the vehicle is 'the formation of the second gate region, and additionally has the following steps: forming a second layer made of an electrically conductive material on the gate insulating layer, the source/drain region Refraction of the carbon layer of the crucible, < and forming a passive layer on the complete wafer of the insulative substrate
第13頁 1289325Page 13 1289325
平面化。 該第二閘極絕緣層較佳的是由被摻雜的 =極==二閑極區域也由此形成。該丄層 的回蝕,使其可此確保利用一種簡單的方式,不在該源 極/汲極區域與該兩閘極區域之間形成一短路,也就/是電 傳導連接。該純態層較佳的是由氧化石夕所形成,並做為用 於將該平坦化雙閘極電晶體的絕緣,也就是說將該化 雙閘極電晶體與外界絕緣。 、在一發展中,該方法額外具有接觸連接該第一閘極區 φ域與接觸連接該第二閘極區域的步驟。 該第一閘極區域的接觸連接,可以具有以下的步驟: 移除部分的鈍態層,藉此將該第二閘極區域的部分區域變 為未覆蓋。移除在已經變為未覆蓋部分區域中的第二間極 區域方式,將該第一絕緣層的部分區域變為未覆蓋。移除 在已經變為未覆蓋部分區域中的第一絕緣層方式,將該第 一閘極區域的部分區域變為未覆蓋,以及形成該第一 ^極 .區域的接觸連接。 利用這些子步驟的方式,可形成一明顯的孔洞或溝 (渠,其使得該兩閘極可以朝向外侧接觸連接。該接觸連接 儀^者可以利用在孔洞中形成金屬層的方式作用。較佳的 是,在形成做為該接觸連接的金屬層之前,在該閘極區域 的未覆蓋區域中,形成以石夕化物製成的層,以減少該接觸 連接的接觸阻抗。 較佳的是,在移除該第一絕緣層之前,以將形成該第Planarization. The second gate insulating layer is preferably formed by the doped = pole == two idle regions. The etch back of the germanium layer allows it to ensure that a short circuit, i.e., a conductive connection, is not formed between the source/drain region and the two gate regions in a simple manner. The pure layer is preferably formed of oxidized oxide and serves to insulate the planarized double gate transistor, that is, to insulate the double gate transistor from the outside. In a development, the method additionally has the step of contacting the first gate region φ domain and the contact connecting the second gate region. The contact connection of the first gate region may have the following steps: removing a portion of the passive layer, thereby changing a portion of the second gate region to uncovered. The second inter-regional region in the region that has become uncovered is removed, and the partial region of the first insulating layer is changed to uncovered. The first insulating layer in the region that has become uncovered is removed, the partial region of the first gate region is changed to uncovered, and the contact connection of the first region is formed. By means of these sub-steps, a distinct hole or trench (drain can be formed which allows the two gates to be contact-connected towards the outside. The contact connector can be acted upon by forming a metal layer in the hole. Preferably, a layer made of a stellite is formed in the uncovered region of the gate region to reduce the contact resistance of the contact connection before forming the metal layer as the contact connection. Preferably, Before the first insulating layer is removed, the first
1289325 五、發明說明(10) 二閘極區域的第二傳導層未霜 非傳導層。 木復盍區域氧化的方式,形成一 藉由將形成該第二閘極區域一德 氧化的方式,彳以利用第—傳導層未覆盍£域 閑極區域與該第二閉極區域方式,形成介於該第- 接著被獨自地接觸連接,絕緣。該第二問極區域 第二問極區域,施加一不;的;:對該第-閑極區域與該 以彼此獨立控制。因此,以°㈣閘極區域因此可 晶體,可以做為-種儲4:方;所形成的一種雙問極電 >該描述用以製造一雙閘=訊的記憶晶片。 單、已知、嘗試試驗以及節省,以-種簡 平坦化雙問極電晶體乂=的加工步驟,提供-種 層,以及該石夕絕緣體絕;;;圖::該:絕緣體基板石夕 裝做為遮罩,該方法是=我;:該第-閘極區;的封 p A命斗始 種自我對齊的方法,而該第一閘 間極區域,是正確的彼此相對。 兮石夕頌緩ί 2使用矽鍺碳-其在先前技術中是未知的-與 可能提供一種方法,其利用-種簡單 有:::式’供應-平坦化雙閘極電晶體。 種製造平坦化雙閘極電極=體種r ;於:=”本的半導體技術子步驟。根據本發明, 由於該子乂驟疋疋以一種方式整合 晶體’其短通道效應是因為該兩閑極的=效 果而大大減少。特別的,該製造處理是以使用的方式以發1289325 V. INSTRUCTIONS (10) The second conductive layer of the second gate region is not frosted. The method of oxidizing the wood retanning region forms a method of oxidizing the second gate region by using a first conductive region to utilize the first conductive region and the second closed region. The formation is between the first and then connected by itself and insulated. The second interrogation region, the second interrogation region, is applied with a :; the first and the idle regions are controlled independently of each other. Therefore, the (4) gate region is thus crystallizable, and can be used as a type of memory: a double-question pole is formed; the description is used to fabricate a dual-gate memory chip. Single, known, tried and saved, with a simple flattening double-question transistor 乂 = processing steps, providing - seed layer, and the lithium insulator;;; Figure:: the insulator substrate Shi Xi As a mask, the method is =I;: the first gate region; the seal p A life begins to self-align, and the first gate region is correct relative to each other. The use of bismuth carbon - which is unknown in the prior art - and the possibility of providing a method that utilizes a simple type:::-supply-flattening double-gate transistor. Manufacturing a planarized double gate electrode = body species r; in: = "the semiconductor technology sub-step. According to the invention, the short channel effect is due to the sub-stepping of the crystal in one way because the two are idle The extreme effect is greatly reduced. In particular, the manufacturing process is based on the way of use.
晒 第15頁 1289325Sun on page 15 1289325
五、發明說明(11) 錯碳製成做為源極/汲極區域的方式所簡化-目前為止, 在雙閘極電晶體的製造是未知的-。無論如何,使用—種# 矽鍺層.,換言之一種不具有碳的層,也具有該矽鍺層能夠 大大地減少掺雜物擴散的優點。 特別是在使用矽鍺碳層時,對於傳統材料而言具有優 點。其一是該矽鍺碳層為一種能夠大大減少摻雜物擴散的 材料’也就是摻雜物擴散進入該平坦化雙閘極電晶體的通 道區域’藉此得到更佳及更可靠的通道區域控制。其二是 在製造加工中,提供額外的自由度,因為其可以使用對於 鍺碳具有選擇性作用的蝕刻劑。 根據本發明,本發法的額外優點,是在一石夕絕緣體層 基板晶圓的矽厚層上,形成該源極/汲極區域,也就是說 位於該絕緣層(载層)下方的層,然而在已知的方法中, 該源極/沒極區域是形成在該矽絕緣體基板的石夕薄層上, 也就是說該矽層是位於該絕緣層之上。此簡化了從該層產 生源極/汲極區域的形成,因此,藉由範例,可以減少在 該形成期間中的應力。 【實施方式】 根據本發明方法的子步驟,其用於製造根據本發明一 範實施例的平坦化雙閘極電晶體,將參考圖示詳細說 明。 第1圖顯示根據本發明一雙閘極電晶體丨〇 〇的概要配置 的概要平面圖示。第1圖主要用於描述該雙閘極電晶體1 0 0 的概要配置,以及描述在製造根據本發明雙閘極電晶體V. INSTRUCTIONS (11) Smelling of carbon as a source/drain region is simplified - so far, the manufacture of double-gate transistors is unknown. In any case, the use of a layer of 矽锗., in other words a layer without carbon, also has the advantage that the layer of ruthenium can greatly reduce the diffusion of dopants. Especially when using a tantalum carbon layer, it has advantages for conventional materials. One is that the tantalum carbon layer is a material that can greatly reduce dopant diffusion 'that is, the dopant diffuses into the channel region of the planarized double gate transistor', thereby obtaining a better and more reliable channel region. control. The second is to provide additional degrees of freedom in the manufacturing process because it can use an etchant that selectively acts on bismuth carbon. According to the present invention, an additional advantage of the present method is that the source/drain region, that is, the layer under the insulating layer (carrier layer), is formed on a thick layer of a silicon-on-insulator substrate wafer. However, in the known method, the source/no-polar region is formed on the thin layer of the tantalum insulator substrate, that is to say the tantalum layer is located above the insulating layer. This simplifies the formation of the source/drain regions from the layer, and therefore, by way of example, the stress during the formation can be reduced. [Embodiment] A sub-step of a method according to the present invention for fabricating a planarized double gate transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic plan view showing an outline configuration of a double gate transistor 根据 according to the present invention. Figure 1 is mainly used to describe the schematic configuration of the double gate transistor 100, and is described in the fabrication of a double gate transistor according to the present invention.
12893251289325
100的期間,在之後所敘述以光微影遮罩方式所定義的不 同光微影區域。為了強化清晰,在第丨圖中並未描述該完 整雙閘極電晶體100的封裝。 、根據本發明的雙閘極電晶體1〇〇,具有一下方閘極區 域,其在第1圖中是省略的,並只利用較佳的是以金屬製 成的,一接觸連接1 0 1所指明,而一第一接觸區域1 0 2,較 佳的是由矽化物所製成。此外,該雙閘極電晶體丨〇〇具有 一上方閘極區域1〇3,其較佳的是以多矽所形成。此外, ^第二接觸連接104與一第二接觸連接區域1〇5則用於描述 .該上方閘極區域103。該第二接觸連接1〇4較佳的是由一種 金屬所製成,而該第二接觸連接區域丨0 5較佳的是以矽化 物所形成。 在第1圖中顯示的雙閘極電晶體1〇〇,額外具有一封裝 106,其將該上方閘極區域丨03與該下方閘極區域1〇ι與外< 界電力絕緣。該封裝106較佳的是由氮化矽(si3M4 )所形 成。第1圖額外描述以氧化矽製成的一第一層丨〇 7。以氧化 石夕製成的該第一層107,是用於該下方閘極區域接觸連接 1 〇 1的封裝,其因此將該下方閘極區域與該上方閘極區域 1 0 3絕緣。 籲 此外,根據本發明的雙閘極電晶體1 00具有一没極區 域1 0 8與一源極區域1 〇 9 ’兩者都是由S i G ex Cy所形成,其 中x的數值較佳的是位於0·2至0·4的範圍之間,而y的數值 較佳的是位於0· 02至0· 05的範圍之間。在該源極區域1〇9 中,描述較佳的是由金屬所製成的一第三接觸連接11〇,During the period of 100, different light lithography regions defined by the photolithographic masking method will be described later. In order to enhance the clarity, the package of the complete double gate transistor 100 is not described in the figure. The double gate transistor 1A according to the present invention has a lower gate region which is omitted in FIG. 1 and is preferably made of metal, a contact connection 1 0 1 As indicated, a first contact area 102 is preferably made of a telluride. Further, the double gate transistor 丨〇〇 has an upper gate region 1 〇 3 which is preferably formed by a plurality of turns. In addition, the second contact connection 104 and a second contact connection region 1〇5 are used to describe the upper gate region 103. The second contact connection 1 4 is preferably made of a metal, and the second contact connection region 丨 0 5 is preferably formed of a bismuth. The dual gate transistor 1A shown in Fig. 1 additionally has a package 106 which insulates the upper gate region 丨03 from the lower gate region 1〇1 from the outer < The package 106 is preferably formed of tantalum nitride (si3M4). Figure 1 additionally describes a first layer of ruthenium 7 made of yttrium oxide. The first layer 107, made of oxidized stone, is a package for the lower gate region contact connection 1 , 1 which insulates the lower gate region from the upper gate region 103. In addition, the double gate transistor 100 according to the present invention has a non-polar region 1 0 8 and a source region 1 〇 9 ' both formed by S i G ex Cy , wherein the value of x is better. The value is between 0·2 and 0·4, and the value of y is preferably between 0·02 and 0.05. In the source region 1〇9, a third contact connection 11〇 made of metal is preferably described.
第17頁 1289325 五、發明說明(13) " — 以及一第三接觸區域111。該第三接觸區域U1較佳的是 矽化物所製成。在該汲極區域1 0 8中,則描述較佳的是 金属所製成的一第四接觸連接丨丨2,以及一第四接觸區 11 3。該苐四接觸區域11 3較佳的是由石夕化物所製成。1m s 第1圖也描述該主動區域的封裝114,換言之,該源 極/汲極區域與該通道區域(在第丨圖中未顯示)的封裝,Page 17 1289325 V. Invention Description (13) " — and a third contact area 111. The third contact region U1 is preferably made of a telluride. In the drain region 1 0 8 , a fourth contact port 2 made of metal and a fourth contact region 11 3 are preferably described. The crucible four contact regions 11 3 are preferably made of lithium. 1m s Figure 1 also depicts the package 114 of the active region, in other words, the source/drain region and the channel region (not shown in the figure),
其用以將該源極/汲極區域與外界電力絕緣。該封裝較^圭 的是由氧化矽的方式形成。 X 為了促進後續圖示與製造一平坦化雙閘極電晶體的瞭 參解,其將參考後續圖示所說明,第i圖額外描繪出沿著後” 續描述橫斷面圖示所採用的線,以及在再製造一平"坦化雙 閘極電晶體方法中,光微影步驟所實行的區域。一 ^具體的,其是沿著該平坦化雙閘極電晶體閘極區域所 前進的斷面線G-G,以及沿著該平坦化雙閘極電晶體源極/ 沒極區域所前進的斷面線S-D。此外,線段丨丨5是用以指明 在一第一光微影步驟中所使用的光微影遮罩,其中定義了 該主動區域,也就是該平坦化雙閘極電晶體的源極/汲極 區域與通道區域。線段11 6是用以指明在一第二光微影步 驟中所使用的光微影遮罩,其中定義了該平坦化雙閉^虽"電 _體的閘極區域。線段1 1 7是用以指明在一第三光微影步 驟中所使用的光微影遮罩,其中再一次定義了該主動區 域’也就是該平坦化雙閘極電晶體的源極/汲極區域與通 道區域。線段11 8是用以指明在一第四光微影步驟中所使 用的光微影遮罩,其中定義了該平坦化雙閘極電晶體下方 1289325 五、發明說明(14) 閘極區域的接觸孔洞。 第2圖顯示在根據本發明用以製造一平扫化 一 艾閣極電 晶體100的第一子步驟之後,一層配置200的橫斷面, 該橫斷面圖示與第3至第6圖的橫斷面圖示一樣,都二= 1圖中的線段S-D所顯示。該各自的子步驟在之後將蛘=敘 述。 、 根據本發明用以製造一平坦化雙閘極電晶體的開妒 點,是一種具有以矽製成的一第一層2 0 1 (載層)、以°氧 化矽製成的一第一層202 (絕緣體)以及一第二矽層2〇3的 鲁傳統矽絕緣體基板晶圓(SO I晶圓)。之後以一第一光微 影步驟的方法,定義該雙閘極電晶體的主動區域,也就是 說應用一蝕刻步驟,定義在後續子步驟終將形成該源極區 域與該没極區域的區域。在此情況中,應用一種光阻抗於 使用一第一遮罩的該第二矽層203,其對應於在第i圖中以 線段11 5所指明的遮罩。接著是以一第一钱刻步驟银刻該 第二矽層203,藉此形成該第二矽層203的一種平台結構, 也就是說形成該第二石夕層203的一種類臺座或是類表格, 該型式將對應於之後所形成的源極/汲極區域與通道區 域。接著去除該光阻抗的殘餘。該埋設的第一氧化矽層 .0 2可以在該第一姓刻步驟中做為一触刻終止層。 接著在該矽層2 0 3已經由該第一蝕刻步驟所移除的區 域中,形成一第一氮化矽層2 0 4。該第一氮化矽層2 0 4較佳 的是以磊晶的方式形成,並與該第二矽層203具有相同厚 度。該氮化矽層2 0 4用於第一絕緣。該第一氮化矽層2 0 4接It is used to insulate the source/drain region from external power. This package is formed by the method of yttrium oxide. X is intended to facilitate the subsequent illustration and fabrication of a planarized double gate transistor, which will be described with reference to the subsequent figures, which additionally depict the use of the cross-sectional illustration along the continuation of the description. The line, and the area in which the photolithography step is performed in the process of remanufacturing a flattened double gate transistor. Specifically, it is advanced along the planarized double gate transistor gate region. a section line GG, and a section line SD along which the source/nomogram area of the planarized double gate transistor is advanced. Further, the line segment 丨丨5 is used to indicate a first photolithography step. The photolithographic mask used, wherein the active region is defined, that is, the source/drain region and the channel region of the planarized double gate transistor. The line segment 116 is used to indicate a second light micro a photolithographic mask used in the shadowing step, wherein the planarized double-closed "electro-body gate region is defined. Line segment 1 17 is used to indicate a third photolithography step The light lithography mask used, which once again defines the active area 'that is the flat a source/drain region and a channel region of the double gate transistor. The line segment 11 8 is used to indicate a photolithographic mask used in a fourth photolithography step, wherein the planarization double gate is defined Under the polar transistor 1289325 V. Description of the invention (14) Contact hole in the gate region. Figure 2 shows a layer 200 configuration after the first sub-step of fabricating a flat-panel-electro-polar crystal 100 in accordance with the present invention. The cross-sectional view, which is the same as the cross-sectional illustration of Figures 3 through 6, is shown by the line segment SD in the second = 1. The respective sub-steps will be followed by 蛘 = description. The opening point for fabricating a planarized double gate transistor according to the present invention is a first layer 2 0 1 (carrier layer) made of tantalum, and a first layer made of yttrium oxide Layer 202 (insulator) and a second layer of germanium insulator substrate wafer (SO I wafer). The first photolithography step is then used to define the active of the double gate transistor. Region, that is to say applying an etching step, defining that the source will be formed at the end of the subsequent substeps a region of the domain and the immersed region. In this case, an optical impedance is applied to the second ruthenium layer 203 using a first mask, which corresponds to the mask indicated by line segment 115 in FIG. Then, the second layer 203 is silver engraved in a first step, thereby forming a platform structure of the second layer 203, that is, forming a pedestal of the second layer 203 or Is a class table, the pattern will correspond to the source/drain region and the channel region formed later. Then the residual of the optical impedance is removed. The buried first yttrium oxide layer .0 2 can be in the first surname step The middle layer is used as a touch stop layer. Then, a first tantalum nitride layer 2 0 4 is formed in a region where the germanium layer 2 0 3 has been removed by the first etching step. The first tantalum nitride layer 204 is preferably formed in an epitaxial manner and has the same thickness as the second tantalum layer 203. The tantalum nitride layer 220 is used for the first insulation. The first tantalum nitride layer is connected to the 2 0 4
第19頁 1289325 五、發明說明(15) =為了在該平坦化雙閘極電晶體的被形成源極/汲極區 U被形成下方閑極區域之間的電力絕緣,以及該兩閉 =之間的絕緣,而做為-種封裝。特別的,該第4 1 s 204也用^於絕緣與定義該通道區域,其是在後續的 =驟中從該第二發層2()3所形成。該第一氮化石夕層2〇4與 -矽層203具有相同的厚度,藉此避免造成不需要的間、 ,、’必簡化後續的平坦化步驟。如果該第二矽層2〇3以及 邊被形成的氮化矽層2〇4具有一種造成機械應力的大厚 度,便可以對該第一氮化矽層2〇4應用一種以氧化矽所製 儀0的層,藉此減少機械應力。該第一氮化矽層2〇4則在後 續方法步驟中,做為一蝕刻終止層。 接著該層配置的表面將被平坦化,而該第二矽層2 〇 3 則做為終止器。該平坦化較佳的是以化學機械研磨 (CMP )的方式實行。該平坦化確保產生一種表面高程, 且該第二矽層203與該第一氮化矽層204的厚度是相同的 在次一方法步驟中,該第二矽層203是被部分氧化, 因此形成一第二氧化矽層205,其接著將做為用於該下方 閘極區域的閘極絕緣層。以多矽製成的一第一層2〇6、以 氮化石夕製成的一第二層207,以及以氧化發製成的一第r 2 0 8,將依序形成。該下方閘極區域接著由該第一多石夕 層2 0 6形成,而接著則由該第二氮化矽層2 〇 7形成該下方 閘極區域的封裝。該第三氧化梦層2 0 8可以接著在姓刻步 驟中,做為該第二氮化矽層207的保護層。 接著實施一第二光微影步驟。為此目的,使用—第二Page 19 1289325 V. Description of the Invention (15) = In order to form the source/drain region U of the planarized double gate transistor to be electrically insulated between the lower idle regions, and the two closed = Insulation between, and as a kind of package. Specifically, the 4th s 204 is also used to insulate and define the channel region, which is formed from the second layer 2() 3 in the subsequent = step. The first nitride layer 2 〇 4 and the 矽 layer 203 have the same thickness, thereby avoiding unnecessary interfacial, and simplifies the subsequent planarization step. If the second tantalum layer 2〇3 and the tantalum nitride layer 2〇4 formed on the side have a large thickness causing mechanical stress, a first tantalum nitride layer 2〇4 may be used for the first tantalum nitride layer 2〇4. The layer of instrument 0, thereby reducing mechanical stress. The first tantalum nitride layer 2〇4 is used as an etch stop layer in the subsequent method step. The surface of the layer configuration will then be flattened and the second layer 2 〇 3 will act as a terminator. This planarization is preferably carried out by chemical mechanical polishing (CMP). The planarization ensures that a surface elevation is produced, and the thickness of the second tantalum layer 203 and the first tantalum nitride layer 204 are the same. In the next method step, the second tantalum layer 203 is partially oxidized, thus forming A second hafnium oxide layer 205, which will then serve as a gate insulating layer for the lower gate region. A first layer 2〇6 made of a plurality of tantalums, a second layer 207 made of nitride nitride, and a r 2 0 8 made of oxidized hair are sequentially formed. The lower gate region is then formed by the first Dolomite layer 206, and then the second gate layer 2? 7 forms a package for the lower gate region. The third oxidized dream layer 208 can then be used as a protective layer for the second tantalum nitride layer 207 in the surname step. A second photolithography step is then performed. For this purpose, use - second
第20頁 1289325 五、發明說明(16) 遮罩做為光阻抗,其對應於在第1圖中以線段〗丨6所指明的 區域。之後’該第三氧化矽層2〇8、該第二氮化矽層207以 及由該多矽20 6製成的該第一層,是在一第二蝕刻步驟中 蝕刻。該第二氧化矽層2〇5,其形成該下方閘極區域的閘 極絶緣層在此情況中式做為一種蝕刻終止。接著移除剩 餘的光阻抗。Page 20 1289325 V. INSTRUCTIONS (16) The mask acts as an optical impedance, which corresponds to the area indicated by the line segment 丨6 in Figure 1. Thereafter, the third yttria layer 2 〇 8 , the second tantalum nitride layer 207 , and the first layer made of the ruthenium 20 6 are etched in a second etching step. The second hafnium oxide layer 2, 5, which forms the gate insulating layer of the lower gate region, is treated as an etch stop in this case. The remaining optical impedance is then removed.
之後,形成以氮化矽製成的第三層2〇9,該形成較佳 的是以保角沈積的方式實施。該第三氮化石夕層接著在一第 餘刻步驟中,進行非等向性㈣,藉此形成 的間隔器209。該第- ϋ几&成ΟΛ[: + _ μ 衣 如做為-㈣終止層上化 將# I # # 氮化矽製成的間隔器209則用於 、以下甲1極封旋。該第二氧化矽層205接著在一第四巍 刻步驟中蝕刻;該下方閘極 209可以在此情況中做為一 我也就疋該間隔器 的是受到摻耗。〜遮罩…亥第-多矽層206較佳 以參考第—圖所敘述的子步驟,[ 閘極電晶體的下方閘極 v ^ ^形成該千坦化雙 封裝。 區域,以及在該矽絕緣體晶圓上的 μ之後將參考第3圖,說明用於製造該平ϋ雙閘朽雷 _體方法的子步驟,甘+ /卞坦化雙閘極電 汲極區域。 ,、要說明形成一通道區域與源極/ 不勒^ Ϊ2圖士描述的層序列開始’該第二石夕芦203是在楚 五蝕刻步驟中受到非笠 疋在一第 是該間隔器209則做A ° :蝕刻’該下方閘極區域,也就 文為一遮罩。該矽絕緣體晶圓的第—氧 1289325 ---------- 五、發明說明(17) '一"" -------- 一"'一" 以夕層2 0 2則做為一蝕刻終止層。該第一氮化矽層2 〇 4接著 種選擇性第六非等向性蝕刻步驟的方式,進行蝕刻。 二石夕、、邑緣體晶圓第一氧化矽層2 0 2則做為一蝕刻終止層。 猎由該笛上^ +丨!· 力^餘刻步驟,將從位於該下方閘極區域以下的區 ^^移除該完整的第一氮化矽層2〇4。在第3圖的視角 因為其位於該斷面線S-D之後,因此在第3圖中無法看 到該區城 + 二二该第一氮化矽層204的剩餘部分則用於將該之 ^幵》成的源極/汲極區域,與該平坦化雙閘極電晶體的閘 極”,緣,以及用於該通道區域的絕緣。 1列當實施該第六敍刻步驟時’其必須考量的是在該第六 二^驟期間’該間隔器2 〇 9也曝露於蝕刻劑之中,而其 1此仏成該間隔器2 0 9因為該蝕刻劑而蝕刻的結果,也就 二將移除部分以氮化矽製成的間隔器209。為了確保 _ Pi t 了方閘極區域的足夠封裝,換言之,絕緣,在形成 ^二隔器209的期間,即使在該第六蝕刻步驟之後,其仍 ^具有足夠的絕緣性質,也就是說,其是以一種足夠的 '二=形成。做為一替代,也可能在該間隔器2〇9上形成一 『化矽製成的薄層,其在該第六蝕刻步驟期間,護該 間隔器2 0 9。 矽芦在该第六蝕刻步驟之後,該矽絕緣體晶圓的第一氧化 2 疋在一第七餘刻步驟中進行餘刻。此較佳的是 矮縣種非等向性蝕刻實施。為了該第七蝕刻步驟,該矽絕 隔哭^圓的第一矽層2〇1可以做為一種蝕刻終止,而該間 隔器209可以再一次做為遮罩。Thereafter, a third layer 2〇9 made of tantalum nitride is formed, which is preferably carried out in a conformal deposition manner. The third layer of nitride nitride is then subjected to an anisotropic (four) in a subsequent step, whereby a spacer 209 is formed. The first &&; ΟΛ [: + _ μ clothing as - (four) termination layer up to # I # # 矽 矽 间隔 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 。 。 。 。 。 。 。 The second hafnium oxide layer 205 is then etched in a fourth engraving step; the lower gate 209 can be used as a one in this case. The mask is preferably a sub-step of the first embodiment, [the lower gate of the gate transistor v ^ ^ forms the tandem double package. The region, and the μ on the germanium insulator wafer, will refer to FIG. 3, illustrating a substep of the method for fabricating the germanium double gate, the gamma + / 卞 化 双 双 双 双. , to illustrate the formation of a channel region and the source / / ^ ^ 2 图 2 description of the layer sequence begins 'the second Shi Xi Lu 203 is in the Chu five etching step is not a 笠疋 in the first is the spacer 209 Then do A ° : etch 'the lower gate region, which is also a mask. The first insulator of the germanium insulator wafer - oxygen 1289325 ---------- five, invention description (17) 'a "" -------- a "'one" Layer 2 0 2 acts as an etch stop layer. The first tantalum nitride layer 2 〇 4 is etched in a manner selective to a sixth anisotropic etch step. The first ruthenium oxide layer of the Ershixi and 邑 体 body wafers is used as an etch stop layer. Hunting by the flute ^ + 丨! The force ^ residual step removes the complete first tantalum nitride layer 2〇4 from the region below the lower gate region. The angle of view in Fig. 3 is because it is located behind the section line SD, so the area of the area and the second part of the first layer of tantalum nitride 204 cannot be seen in Fig. 3 for the purpose of The source/drain region, the gate of the planarized double-gate transistor, the edge, and the insulation for the channel region. 1 column when implementing the sixth snippet step During the sixth two steps, the spacer 2 〇 9 is also exposed to the etchant, and the result of etching the etchant is as follows. Part of the spacer 209 made of tantalum nitride is removed. In order to ensure sufficient encapsulation of the square gate region, in other words, insulation, during the formation of the second spacer 209, even after the sixth etching step , which still has sufficient insulating properties, that is, it is formed by a sufficient 'two=. As an alternative, it is also possible to form a thin layer of bismuth on the spacer 2〇9. During the sixth etching step, the spacer 2 0 9 is protected. After the sixth etching step, The first oxidation of the germanium insulator wafer is performed in a seventh remaining step. This is preferably a non-isotropic etching implementation of the dwarf county. For the seventh etching step, the crucible is crying. The round first layer 2〇1 can be used as an etch stop, and the spacer 209 can be used as a mask again.
第22頁 1289325 五、發明說明(18) 之後在該主動區域中,選擇性地形成一種矽鍺碳層 3 1 0 ’也就是說在形成該源極區域與汲極區域的區域之 中。該石夕錯碳層的形成是由磊晶方式實施。該矽:鍺的原 子比例是介於4 : 1至3 ·· 2的範圍甲,而碳的比例則介於原 子比例為2 %至5 %之間。利用選擇性磊晶的形成方式,避 免在該第一石夕層20 1與該矽鍺碳層3丨〇之間形成的機械應 力’因為如果矽、鍺、碳是以一種適當方式選擇時,該兩 層材料的格柵常數將彼此相符,也就是說彼此並沒有很大 的差異。 • 之後,在該層序列上,形成以氧化矽製成的第四層 311,並接著進行平坦化。該平坦化較佳的是以化學機械 研磨的方式作用。 ^ "亥平坦化雙閘極電晶體的通道區域與源極/汲極區域 是以在第3圖中敘述的子步驟所形成。在此情況中,該通 道區域是由該矽絕緣體晶圓的第二矽層2〇3所形成。 曰之後將參考第4圖,說明用於製造該平坦化雙閘極電 晶體/方法的子步驟,其主要說明晶圓黏合的準備及實施。 從第3圖層序列的第四氧化矽層3丨i開始,在其已經平 ^化之後,利用化學或電漿的方法將其活化。一輔助晶圓 3具有-種以氧切製成的第五厚層413。如果該辅助晶 :)2的材料是矽,該第五氧化矽層41 3可以利用將該輔助 曰曰,41 2熱氧化所形成。在第3圖中描述的層序列是以該第 f化♦層311的平坦表面,黏合在該輔助晶圓412的第五 夕層41 3上。该層序列在後續子步驟中被反轉。因Page 22 1289325 V. INSTRUCTION DESCRIPTION (18) Thereafter, in the active region, a tantalum carbon layer 3 1 0 ' is selectively formed, that is, in a region where the source region and the drain region are formed. The formation of the carbon-wound carbon layer is carried out by epitaxy. The 矽: the atomic ratio of 锗 is in the range of 4:1 to 3 ·· 2, and the proportion of carbon is between 2% and 5%. Using the formation of selective epitaxy, avoiding the mechanical stress formed between the first layer of erecting layer 20 1 and the layer of tantalum carbon layer 3 because if yttrium, lanthanum, and carbon are selected in an appropriate manner, The grid constants of the two layers of material will coincide with each other, that is to say without a large difference from each other. • Thereafter, on the layer sequence, a fourth layer 311 made of yttrium oxide is formed and then planarized. Preferably, the planarization acts in a chemical mechanical polishing manner. ^ " The channel region and the source/drain region of the planarized double gate transistor are formed by the substeps described in Fig. 3. In this case, the channel region is formed by the second layer 2〇3 of the germanium insulator wafer. Next, a sub-step for fabricating the planarized double gate transistor/method will be described with reference to Fig. 4, which primarily illustrates the preparation and implementation of wafer bonding. Starting from the fourth yttrium oxide layer 3丨i of the third layer sequence, it is activated by chemical or plasma methods after it has been planarized. An auxiliary wafer 3 has a fifth thick layer 413 cut by oxygen. If the material of the auxiliary crystal :) 2 is ruthenium, the fifth ruthenium oxide layer 41 3 can be formed by thermal oxidation of the auxiliary ruthenium, 41 2 . The layer sequence described in Fig. 3 is bonded to the fifth layer 41 3 of the auxiliary wafer 412 by the flat surface of the f-th layer 311. This layer sequence is inverted in subsequent substeps. because
第23頁 1289325 五、發明說明(19) 此,從第4圖開始,該層序列在後續圖示中被旋轉顯示, 因此第4圖與第3圖相比之下,該頂部與底部是交換的。 之後將參考弟5圖’說明用於製造該平坦化雙閘極電晶體 方法的子步驟,其主要說明形成一第二閘極區域。 從第4圖’從該層序列移除該矽絕緣體晶圓的第一矽 層21 0 (載層)。此較佳的是以研磨的方法,或是一種智 慧切割的方法實施。之後,在一第八蝕刻步驟中,該第一 石夕層2 01的可能殘餘是以驗性溶液的方式進行選擇性地回 蝕。該回蝕可以利用像是EDP (ethylene diamine g^yrocatechol ) >TMAH (tetramethy1ammonium hydroxide)、氫氧化鉀(K〇H,p〇tassium hydr〇xide) 或膽鹼(choline )的方式實施。該列舉的蝕刻溶液,對 矽鍺來說當鍺比例高於20 %時具有高度選擇性。此外,矽 碳在多數的鹼性溶液中也適合做為一種蝕刻終止。此高度 選擇性以移除該第一矽層201可能殘餘的方式,大大地簡 :匕該第八蝕刻步驟。氮化矽與氡化矽也作用為一種蝕刻終 ,特別疋如果以鹼性溶液的方式進行蝕刻時。 接著在一第九蝕刻步驟中移除該第一氧化矽声 目的使用-種對於矽、矽鍺碳以及氮化矽而:且 是=姓刻劑。此步驟定義形成該第二閘 了就 =上方間極區域。該第九崎驟確 ;= =该下方閑極區域之上,是在此#刻步驟中:確:配 ''用做為一蝕刻終止:該通道區域的第二矽層2x03 1289325 五、發明說明(20) 成該源極/汲極區域的矽鍺碳層,以及仍然位在該下方閘 極區域2 0 6上方,在第5圖中因為在第5圖的方向中位於沿 著該層序列斷面所採用的斷面線後方,而無法辨別的第一 氮化矽層。在此情況中,如同已經敘述的,該第一氮化石夕 層204具有與該第二石夕層2 03 —樣的厚度。此是由該第一平 坦化步驟而得到保證。在此情況中,該矽鍺碳層31〇形成 該被餃刻區域的側向邊界,並以此定界支持該製造方法的 自我對齊。 '、 议可# Um步几挪列少鄉所蝕刻的區域中,來 •以氮化石夕製成的一第四層514 ^用於封裝該第二閘極區少风 域,也就是該上方閘極區域的間隔器,是由該第四氮 層514,以後續一種在第十蝕刻步驟中的非等向性蝕刻斤 形成。在形成以氮化矽製成的第四層5 乂 ^斤 在相同區域中先形成一氧化矽層。 别,較佳的是 接著實施一氧化步驟。該氧化步驟用 化矽層515,其利用將形成該雙閘極電 7 -第六氧 5石夕層2°3部分氧化的方式,做為-閑極絕的第 心夕薄侧,其可以在一推雜步驟=免=-第七氧 t數奈米的厚度。 免擴政’並僅具 之後,形成一第二多矽層517,复 佳的是以化學機械研磨法的方式進行、。者破平坦化,較 51 6可以在該平坦化步驟期間做為一 μ第七氧化矽薄層 層517形成該雙閘極電晶體的第二1、^ 士。該第二多石夕 他&域,也就是該上 1289325Page 23 1289325 V. INSTRUCTIONS (19) Therefore, starting from Fig. 4, the sequence of the layer is rotated and displayed in the subsequent illustration, so that the top and bottom are exchanged in comparison with Fig. 4 and Fig. 3. of. A sub-step of the method for fabricating the planarized double gate transistor will now be described with reference to Figure 5, which primarily illustrates the formation of a second gate region. The first germanium layer 21 0 (carrier layer) of the germanium insulator wafer is removed from the layer sequence from Fig. 4'. This is preferably carried out by a grinding method or a method of intelligent cutting. Thereafter, in an eighth etching step, the possible residue of the first layer 121 is selectively etched back in the form of an assay solution. The etch back can be carried out by means of EDP (ethylene diamine g^yrocatechol) > TMAH (tetramethy1ammonium hydroxide), potassium hydroxide (K〇H, p〇tassium hydr〇xide) or choline. The enumerated etching solution is highly selective for cerium when the cerium ratio is higher than 20%. In addition, 矽 carbon is also suitable as an etch stop in most alkaline solutions. This height selectivity is greatly simplified in such a way as to remove the possible residual of the first layer 201. Cerium nitride and antimony telluride also act as an etch finish, especially if etching is carried out as an alkaline solution. The first yttrium oxide is then removed in a ninth etching step for the purpose of ruthenium, osmium carbon and tantalum nitride: and is = surname. This step defines the formation of the second gate = the upper interpole region. The ninth is true; = = above the lower idler region, in this #刻 step: indeed: with '' used as an etch stop: the second layer of the channel region 2x03 1289325 Note (20) that the carbon layer of the source/drain region is still above the lower gate region 206, in Figure 5 because it is located along the layer in the direction of Figure 5 The first tantalum nitride layer that is indistinguishable from the section line used for the sequence section. In this case, as already described, the first layer of nitride layer 204 has a thickness similar to that of the second layer. This is ensured by this first flattening step. In this case, the tantalum carbon layer 31〇 forms the lateral boundary of the dumped region and serves to support the self-alignment of the manufacturing method. ', 议可# Um step a few in the area etched by Shaoxiang, a fourth layer 514 made of nitriding zepa is used to encapsulate the second wind region with less wind, that is, above The spacer of the gate region is formed by the fourth nitrogen layer 514 in a subsequent anisotropic etching in the tenth etching step. In forming a fourth layer of tantalum nitride, a layer of ruthenium oxide is first formed in the same region. Further, it is preferred to carry out an oxidation step. The oxidizing step uses a ruthenium layer 515, which is formed by the partial oxidation of the double gate electric 7 - sixth oxygen 5 stellite layer 2° 3 , as the first thin side of the idle In a push step = free = - seventh oxygen t number nanometer thickness. After the expansion of the government, and only after, a second multi-layer 517 is formed, which is carried out by means of chemical mechanical polishing. The flattening may be performed as a second layer of the seventh gate oxide layer 517 during the planarization step to form the second one of the double gate transistor. The second multi-stone eve his & field, that is, the above 1289325
方閘極,域。該第二多石夕層517,也就是該上方閉極區 域,接著較佳的是被輕微地回#,其可能避免在該上 極區域517與形成該源極/汲極區域的矽鍺碳層3ι〇之間, 所可能形成的短路。 4第了間極區域’也就是該上方閘極區域$ 1 7的形 成,是以第5圖中所敘述的子步驟方式所結束。 曰之後將參考第6圖,說明用於製造該平坦化雙閘極電 晶體方法的子步驟,其主要說明形成該雙閘極絕緣層的絕 i 接,,雜以該矽鍺碳層3 1 0所形成的源極/汲極區域, 以及以該第二多矽層5丨7所形成的上方閘極區域。在此情 況中,該源極/汲極區域是以有效能量遍及該第七氧化矽 薄層51 6而掺雜,該第七氧化矽薄層5丨6是做為一種所謂的 屏幕氧化物層,其在該源極/沒極區域中,可能可以達到 :種更均勻的摻雜原子分佈。該第七氧化矽薄層5丨6接著 是以一第十一選擇性蝕刻步驟所移除。 接著在一第十二蝕刻步驟中,實施該矽鍺碳層31 0的 一種輕微的選擇性回蝕。該第十二蝕刻步驟避免在該上方 ^甲1極區域51 7與形成該源極/汲極區域的矽鍺碳層3丨〇之 ’所可能形成的短路。 接著以重新定義該主動區域的方式,實施一第三光微 影步驟,並實施一第二絕緣,其形成該完整雙閘極電晶體 的=全絕緣。對於該第三光微影步驟,使用一第三遮罩做 為光阻抗,其對應於在第1圖中以線段丨17所指明的線段。Square gate, domain. The second multi-layer 517, that is, the upper closed region, is then preferably slightly backed #, which may avoid the upper pole region 517 and the germanium carbon forming the source/drain region A short circuit that may form between layers 3 ι. The formation of the fourth inter-polar region ', i.e., the upper gate region $17, ends in the sub-step manner described in FIG. Referring now to FIG. 6, a sub-step of a method for fabricating the planarized double gate transistor will be described, which mainly illustrates the formation of the double gate insulating layer, mixed with the tantalum carbon layer 3 1 A source/drain region formed by 0, and an upper gate region formed by the second plurality of germanium layers 5丨7. In this case, the source/drain region is doped with an effective energy throughout the seventh yttria thin layer 516, which is a so-called screen oxide layer. In the source/drain region, it is possible to achieve a more uniform doping atom distribution. The seventh tantalum oxide layer 5丨6 is then removed by an eleventh selective etching step. A slight selective etch back of the tantalum carbon layer 31 0 is then carried out in a twelfth etching step. The twelfth etching step avoids a short circuit which may be formed in the upper surface of the first electrode region 51 7 and the tantalum carbon layer 3B forming the source/drain region. A third photolithography step is then performed in a manner that redefines the active region, and a second insulation is formed which forms the full insulation of the complete dual gate transistor. For the third photolithography step, a third mask is used as the optical impedance, which corresponds to the line segment indicated by the line segment 丨 17 in Fig. 1.
1289325 五、發明說明(22) 在應用與發展該光阻抗之後,部分的矽鍺碳層3丨〇是在一 弟十二韻刻步驟中|虫刻。該第五氧化發層41 3則做為一钱 刻終止。之後,務除該光阻抗的殘餘,並在該層序列上沈 積以氧化矽製成的一第八厚層618。該第八氧化矽層618是 確保該完整雙閘極電晶體與外界絕緣的層。 之後將參考第7 A與7 B圖,說明該平坦化雙閘極電晶體 的兩閘極區域,如何可被接觸連接的替代方式。在第以與 7B圖中的橫斷面,在此情況中是沿著從第i圖中的G-G線段 所採用。 • 參考第7A圖’將說明一示範實施例,其中形成用於該 極區域517的第一接觸連接,以及形成用於該下方 2H206的第二接觸連接。因此,可以對該上方閘極 二二'、該下方閘極區域2 0 6施加不同電壓。這對於可以 此不同位元’使用做為-記憶晶片的平坦化雙間 極電晶體而言是有利的。 驟,ί Ϊ 6用„層序列開始,實施-第四光微影步 驟其使用一第四遮罩做為光 線段11 8。接著實絲一笛工L饥釕應於在弟1圖T的 該第八氧化石夕層618的部等向性蚀刻步驟,其移除 •問極區域2 0 6的接觸連C中接著實施用於該下 石夕層5丨7則做為一蝕刻線止芦成’該上方閘極區域第二多 上方閑極區域517的未覆匕:第二多石夕層517接著在該 性蝕刻步驟所移除,兮第备域中,是以一第十五非等向 止層。 该第—氣化矽層204則做為一蝕刻終1289325 V. INSTRUCTIONS (22) After applying and developing the optical impedance, part of the carbon layer 3丨〇 is in the 12th step of the 12th rhyme. The fifth oxidized layer 41 3 is terminated as a moment. Thereafter, the residual of the optical impedance is removed, and an eighth thick layer 618 made of yttrium oxide is deposited on the layer sequence. The eighth ruthenium oxide layer 618 is a layer that ensures that the complete double gate transistor is insulated from the outside. Reference will now be made to Figures 7A and 7B to illustrate an alternative to how the two gate regions of the planarized double gate transistor can be contacted. The cross section in the first and seventh diagrams, in this case, is taken along the G-G line from the i-th diagram. • Referring to Figure 7A, an exemplary embodiment will be described in which a first contact connection for the pole region 517 is formed and a second contact connection for the lower 2H206 is formed. Therefore, different voltages can be applied to the upper gate 22' and the lower gate region 206. This is advantageous for a flattened dual-electrode transistor that can be used as a memory chip with this different bit'. Step ί Ϊ 6 begins with the „layer sequence, the implementation-fourth photolithography step uses a fourth mask as the light segment 11 8 . Then the silk a flute L hunger should be in the brother 1 T The partial isotropic etching step of the eighth oxidized layer 618, the contact connection C of the removal/question pole region 206 is then carried out for the lower layer 5 丨 7 as an etch line Re-supplied with the second plurality of upper idle regions 517 of the upper gate region: the second multi-layer 517 is then removed in the sexual etching step, in the first field, a fifteenth Non-isotropic stop layer. The first gasification layer 204 is used as an etch stop.
$ 27頁 1289325 五、發明說明(23) 夕石々移仍然存在的光阻抗殘餘。之後,實施該第二 二:方丨丰的受控制熱氧化,其氧化該第二多矽層以該第 ^五姓刻步驟的方式而變為未覆蓋的區域,以形成-第九 = Γ,9。該第九氧化石夕層719做為-種用㈣第-閉 ° ^ 對於该第二閘極區域的絕緣,因此在該兩閘極 區域之間不造成短路,並因此可對該兩閘極區域施加不同 的電壓。 之後,在第十五蝕刻步驟中變為未覆蓋的該第一氮化 發層204區域,是在一第十六非等向性步驟中移&,造成 『亥下方閘極區域2 〇 6 ,也就是該第一多矽層2 〇 6的部分變為 未覆蓋。該下方閘極區域的第一多矽層2〇6是在此第十六 蝕刻步驟中,是做為一蝕刻終止。之後,在該下方閘極區 域206由該第十六蝕刻步驟變為未覆蓋的區域上,形成一 金屬薄層,並將該下方閘極區域2 〇 6的第一多矽層2 〇 6石夕 化,藉此形成一第一矽化物層720,其減少該下方閘極區 域2 0 6接觸連接的接觸阻抗。接著在該第一石夕化物層γ 2 〇上 形成一第一金屬層721,該第一金屬層721代表至該下方閘 極區域2 0 6的接觸。 該下方閘極區域2 0 6的接觸連接,是以所敘述的子步 方式結束。 接著以一種相同的方式,形成該第二多碎層517,也 就是該上方閘極區域51 7的接觸連接,以及形成一第二石夕 化物層722與一第二金屬層723。 為了形成該上方閘極區域517的接觸連接,實施一第$27页 1289325 V. INSTRUCTIONS (23) The remaining light impedance remains in the eve of the stone. Thereafter, the second two: controlled thermal oxidation of Fang Fufeng is performed, which oxidizes the second multi-layer to become an uncovered region in the manner of the fifth step to form - ninth = Γ, 9 . The ninth oxidized stone layer 719 is used as a kind of (four) first-closed ^ ^ for the insulation of the second gate region, so that no short circuit is caused between the two gate regions, and thus the two gates can be Different voltages are applied to the area. Thereafter, the region of the first nitride layer 204 that becomes uncovered in the fifteenth etching step is shifted in a sixteenth anisotropy step, resulting in "the lower gate region 2 〇 6 That is, the portion of the first multi-layer 2 〇 6 becomes uncovered. The first multi-layer 2 〇 6 of the lower gate region is in this sixteenth etching step as an etch stop. Thereafter, a thin metal layer is formed on the lower gate region 206 from the sixteenth etching step to an uncovered region, and the first plurality of germanium regions 2 〇6 of the lower gate region 2 〇6 are formed. In the evening, a first vaporization layer 720 is formed which reduces the contact resistance of the contact connection of the lower gate region 206. Next, a first metal layer 721 is formed on the first lithi layer γ 2 ,, and the first metal layer 721 represents contact to the lower gate region 206. The contact connection of the lower gate region 206 is terminated by the substep described. Next, in a similar manner, the second multi-fracture layer 517, that is, the contact connection of the upper gate region 517, and a second lithium layer 722 and a second metal layer 723 are formed. In order to form the contact connection of the upper gate region 517, a first implementation is implemented.
第28頁 1289325 五、發明說明(24) 五光微影步驟。為此目的,使用一第二遮罩做為光阻抗, 其基本上對應於在第1圖中該第二接觸區域1 〇 5的等高線。 接著實施一第十七非等向性蝕刻步驟,其移除該第五氣化 石夕層513的部分區域,其中接著實施用於該上方閘極區域 51 7的接觸連接形成,該上方閘極區域的第二多石夕層5丨7則 做為一银刻終止層。 接著在該上方閘極區域51 7由該第十七蝕刻步驟而變 為未覆蓋的區域上’形成一金屬薄層,並石夕化該上方閑極 £域的第一多碎層517 ’精此形成一第二硬化物層722,4 •咸少該上方閘極區域5 1 7接觸連接的接觸阻抗。接著在該 第二矽化物層722上形成一第二金屬層,該第二金屬層^ 表至該上方閘極區域5 1 7的接觸。 以製造一平坦化雙閘極電晶體方式的子步驟,所形成 的平坦化雙閘極電晶體,便如同參考第7A圖所敘述的相 同0 參考第7B圖,將說明一示範實施例,其中形成用於該 上方閘極區域517與該下方閘極區域2〇6的一共同接觸連 接。因此,可以對該上方閘極區域517與該下方閘極區域 f 6施加一相同電壓,並可以為了該通道區域,使用兩閘 囑k區域的控制效果。 從第6圖描述的層序列開始,實施一第六光微影步 驟,其使用一第四遮罩做為光阻抗,對應於在第i圖中的 線段11 8。接著實施一第十八非等向性蝕刻步驟,其移除 該第五氧化石夕層513的部分區域,其中接著實施用於該兩Page 28 1289325 V. INSTRUCTIONS (24) Five-light lithography steps. For this purpose, a second mask is used as the optical impedance, which substantially corresponds to the contour of the second contact region 1 〇 5 in FIG. Next, a seventeenth anisotropic etching step is performed, which removes a partial region of the fifth gasification layer 513, wherein a contact connection formation for the upper gate region 51 7 is subsequently performed, the upper gate region The second multi-stone layer 5丨7 is used as a silver engraving stop layer. Then, a thin metal layer is formed on the upper gate region 517 by the seventeenth etching step to become an uncovered region, and the first multi-layer 517 of the upper idle region is formed. This forms a second layer of hardened layer 722, 4 which is less than the contact resistance of the upper gate region 5 17 contact connection. A second metal layer is then formed on the second germanide layer 722, the second metal layer being in contact with the upper gate region 516. To form a planarized double gate transistor sub-step, the resulting planarized double gate transistor is as described with reference to FIG. 7A. Referring to FIG. 7A, an exemplary embodiment will be described in which an exemplary embodiment is described. A common contact connection is formed for the upper gate region 517 and the lower gate region 2〇6. Therefore, the same voltage can be applied to the upper gate region 517 and the lower gate region f 6 , and the control effect of the two gates k region can be used for the channel region. Starting from the layer sequence depicted in Fig. 6, a sixth photolithography step is performed which uses a fourth mask as the optical impedance, corresponding to line segment 117 in Fig. i. An eighteenth anisotropic etch step is then performed, which removes a portion of the fifth oxidized layer 513, which is then implemented for the two
第29頁 1289325 五、發明說明(25)Page 29 1289325 V. Description of invention (25)
閘極區域的接觸連接形成,該上方閘極區域第二 517則做為一蝕刻終止層。該第二多矽層 B 閘極區域的未覆蓋區域中,是以一第 ,f在該上方 八 驟所移除,該第一氮化石夕層2〇4則做為_敍刻終止層步 接著移除仍然存在的光阻抗殘餘。之後,對該第二夕 石夕層517的未覆蓋區域施加—第三金屬薄層,並石夕化該夕 二多石夕層517的未覆蓋區域,藉此形成一第三石夕化物層 714 ,其減^少該上方閘極區域5丨7接觸連接的接觸阻抗。 接著以一第十九非等向性姓刻步驟,移除在該第 #虫刻步驟中變為未覆蓋的第一氮化矽層2〇4區域,因此該 :方閘極,也就是說該第一多矽層206的部分是變為未覆 蓋的。該下方閘極區域第一多矽層2 〇 6在此第十九蝕刻步 驟中則做為一種蝕刻終止。之後,在該下方閘極區域已經 由第十九蝕刻步驟變為未覆蓋的區域上,形成一金屬薄 層’並矽化該下方閘極區域的第一多矽層2 〇 6,藉此形成 一第四矽化物層7 2 5,其減少該下方閘極區域2 〇 6接觸連接 的接觸阻抗。接著在該第四矽化物層725上形成一第三金 屬層726,該第三金屬層代表至該下方閘極區域2〇6的接 觸。做為該兩分離矽化步驟的替代,也可以利用一單一加 _步驟,也就是說以一種單一矽化步驟的方式,形成該第 二石夕化物層724與該第四矽化物層7 25,也就是說在該第十 九非等向性蝕刻步驟之前,並不實施該第三矽化物層724 的形成。 利用敘述子步驟的方式,將完成該兩閘極區域的接觸A contact connection is formed in the gate region, and the second gate region 517 is used as an etch stop layer. In the uncovered region of the gate region of the second plurality of germanium layers B, the first is removed, and the first nitrided layer is removed as the upper eight steps. The residual optical impedance remaining is then removed. Thereafter, a third metal thin layer is applied to the uncovered region of the second eve layer 517, and the uncovered region of the eve of the celestial layer 517 is formed, thereby forming a third ruthenium layer 714, which reduces the contact resistance of the upper gate region 5丨7 contact connection. Then, a nineteenth anisotropic first step is performed to remove the first tantalum nitride layer 2〇4 region which becomes uncovered in the first insect step, so the square gate, that is, The portion of the first multi-layer 206 is rendered uncovered. The lower gate region first multi-layer 2 〇 6 is used as an etch stop in this nineteenth etch step. Thereafter, on the region where the lower gate region has been changed from the nineteenth etching step to the uncovered region, a thin metal layer is formed and the first plurality of germanium layers 2 〇 6 of the lower gate region are deuterated, thereby forming a The fourth vaporization layer 7 2 5 reduces the contact resistance of the contact region of the lower gate region 2 〇6. A third metal layer 726 is then formed over the fourth germanide layer 725, the third metal layer representing contact to the lower gate region 2〇6. As an alternative to the two separate deuteration steps, a single addition step can also be utilized, that is, the second lithiation layer 724 and the fourth vaporization layer 7 25 are formed in a single deuteration step. That is, the formation of the third vaporized layer 724 is not performed before the nineteenth anisotropic etching step. The contact between the two gate regions will be completed by means of a sub-step
第30頁 1289325Page 30 1289325
五、發明說明(26) 連接’並形成該平坦化雙閘極電晶體。 參考第8與第9圖,將敘述一替代方式。 在此敘述的替代方法步驟,與參考第2 方法步驟相同。只有對於第6與第7B圖敘述的方法而」〔古的 :斤改變。在此敘述的替代方法,基本上的差別在於二 ,步驟中,實施,下方閘極區域206與該上方閘極區在域 7,利用鍺矽碳310製成層的結合矽化。為此目― ,該第八氧化石夕層618之前,利用該第—多石夕層2()6 ^ =分區域所完成的該第一多矽層2〇6,也就是該下方 域2 0 6的接觸連接方式,實施一蝕刻步驟。 甲° 去二在一結合矽化步驟中’在該第-多矽層206的 禾覆盍區域、該矽鍺碳層31〇與該第二多矽層517上, 一矽化層827。接著形成該第八氧化矽層618, ^ ' 第8圖t所描述的層序列800。 U此士成在 在此敘述替代方法的額外步驟,是根據以上參 圖所敘述的方法實施。從此形成的雙閘極場效電晶體於 9圖一致,並根據第1圖中的橫斷面圖示G一〇。 、 總結來說,本發明與一種製造平坦化自我對齊雙閘極 ^晶體的方法有關,其具有半導體技術的已知、簡單二及 •省成本的方法。本發明的各自子步驟整合,所製造的平 垣化雙閘極電晶體,其短通道效應是因為該兩閘極的控制 效果而大大減少。此外,該製造步驟可因為使用矽鍺^層 做為源極/曰汲極區域而簡化,此使用在之前雙閘極電晶體曰 的製造中是未知的。矽鍺的使用以及特別是矽鍺碳的使V. INSTRUCTIONS (26) Connect 'and form the planarized double gate transistor. Referring to Figures 8 and 9, an alternative will be described. The alternative method steps described herein are the same as the reference to the second method step. Only for the methods described in Figures 6 and 7B" [Ancient: Jin changes. In the alternative method described herein, the basic difference is that in the second step, the lower gate region 206 and the upper gate region are in the domain 7, and the layer of tantalum carbon 310 is used to form a layer of germanium. For this purpose, before the eighth oxidized stone layer 618, the first multi-layer 2〇6, which is the lower domain 2, is completed by using the first-to-the-story layer 2()6^=sub-region A contact connection of 0 6 is performed by performing an etching step. In a combined deuteration step, a deuterated layer 827 is formed on the crucible region of the first multi-layer 206, the tantalum carbon layer 31 and the second multi-layer 517. A layer sequence 800 of the eighth yttria layer 618, ^ 'Fig. 8 t, is then formed. U. This is an additional step in the description of the alternative method, which is carried out according to the method described in the above reference. The double gate field effect transistor thus formed is identical in Fig. 9, and is shown in Fig. 1 in a cross section. In summary, the present invention relates to a method of fabricating a planarized self-aligned double gate crystal having known, simple, and cost effective methods of semiconductor technology. The respective sub-steps of the present invention are integrated, and the resulting short-channel effect of the double-gate transistor is greatly reduced by the control effect of the two gates. Moreover, this fabrication step can be simplified by using the germanium layer as the source/drain region, which is unknown in the fabrication of the previous double gate transistor. Use of bismuth and especially carbon
第31頁 1289325Page 31 1289325
用 對於傳統材料而言具有優勢。 Μ 1其一是該矽鍺碳層為一種能夠避免或至少大大、減W、娘 雜物擴散的材料,也就^ Μ Α ^ ^ 也就疋摻雜物擴散進入该平坦化雙閘極 】晶:的,域,藉此得到更佳及更可靠的通道= 一疋在製造加工中所提供的可能性,因為其可以使 用對於矽鍺碳具有選擇性作用的蝕刻劑。在製造步驟中, 使用對於矽鍺碳具有選擇性的蝕刻劑,開放了新的自由 度0 根據本發明,本發法的額外優點是在一矽絕緣體層基 j反晶圓的矽厚層上,形成該源極/汲極區域,也就是說位 於該絕緣層(載層)下方的層,然而在已知的方法中,該 源極/汲極區域是形成在該矽絕緣體基板的矽薄層上,也 就是說該矽層是位於該絕緣層之上。此簡化了從從該層產 生源極/汲極區域的形成,因此,藉由範例,在該形成期 間應力得以減少。It has advantages for traditional materials. Μ 1 The first is that the carbon layer is a material that can avoid or at least greatly reduce W and diffuse the impurities. That is, ^ Μ Α ^ ^ also diffuses the dopant into the flattened double gate. Crystal, the domain, thereby obtaining a better and more reliable channel = a possibility offered in the manufacturing process, because it can use an etchant that has a selective action on germanium carbon. In the manufacturing step, a new degree of freedom is opened using an etchant selective for ruthenium carbon. According to the present invention, an additional advantage of the present method is that on a thick layer of an anti-wafer layer of an insulator layer j Forming the source/drain region, that is, the layer under the insulating layer (carrier layer), however, in the known method, the source/drain region is formed on the germanium insulator substrate On the layer, that is to say the layer is located above the insulating layer. This simplifies the formation of the source/drain regions from the layer, and therefore, by way of example, the stress is reduced during the formation.
第32頁 1289325 圖式簡單說明 第1圖顯示一平坦化雙閘極電晶體的概要平面圖,說明 根據本發明一雙閘極電晶體的概要配置; 第2圖顯示在根據本發明一第一實施例方法的子步驟之 後,根據本發明層配置的概要橫斷面表示,其主要說明形 成該雙閘極電晶體的一第一閘極區域; 第3圖顯示在根據本發明一第一實施例方法的額外子步 驟之後,根據本發明層配置的概要橫斷面表示,其主要說 明形成一通道區域與源極/汲極區域; 第4圖顯示在根據本發明一第一實施例的方法額外子步 響驟之後,根據本發明層配置的概要橫斷面表示,其主要說 明一晶圓黏合; 第5圖顯示在根據本發明一第一實施例方法的額外子步 驟之後’根據本發明層配置的概要橫斷面表示,其主要 明形成一第二閘極區域; ’、 1 後 成 第6圖顯示在根據本發明一第一實施例方法的子步驟之 ,根據本發明層配置的概要橫斷面表示,其主要說 該雙閘極絕緣層的絕緣; 市 第7A圖顯示在根據本發明一第一實施例方法子的 2,根據本發明層配置的概要橫斷表 :之 用於該雙閑極電晶體閑極區=接二τ其要說明形 第7 B圖顯示在根據本發明_ 一 ^根據本發明層配置的概要以=方==之 成用於忒雙閘極電晶體閘極區域的接點;°形 第8圖顯示在根據本發明替代方法的子步驟之後,根據Page 32 1289325 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a schematic plan view of a planarized double gate transistor illustrating an overview of a dual gate transistor in accordance with the present invention; and Figure 2 shows a first implementation in accordance with the present invention. After a sub-step of the method, a schematic cross-sectional representation of a layer configuration in accordance with the present invention, which primarily illustrates forming a first gate region of the dual gate transistor; FIG. 3 shows a first embodiment in accordance with the present invention After an additional sub-step of the method, a schematic cross-sectional representation of a layer configuration in accordance with the present invention, which primarily illustrates forming a channel region and a source/drain region; FIG. 4 shows an additional method in accordance with a first embodiment of the present invention. Sub-steps, a schematic cross-sectional representation of a layer configuration in accordance with the present invention, which primarily illustrates a wafer bond; Figure 5 shows a layer in accordance with the present invention after additional sub-steps of the method in accordance with a first embodiment of the present invention. A schematic cross-sectional representation of the configuration, which primarily forms a second gate region; ', 1 and 6 are shown in a sub-step of the method according to a first embodiment of the present invention, According to a schematic cross-sectional view of the layer arrangement of the present invention, it is mainly said that the double gate insulating layer is insulated; FIG. 7A shows a schematic diagram of a layer configuration according to the present invention in accordance with a first embodiment of the present invention. Transverse table: used for the double idle pole crystal idle region = connected to the second τ, which is illustrated in Figure 7B, which is shown in the outline of the layer configuration according to the present invention according to the present invention, with = square == a contact for the gate region of the double gate transistor; FIG. 8 shows the substeps of the alternative method according to the present invention, according to
第33頁 1289325Page 33 1289325
圖式簡單說明 本發明層配置的概要橫斷面表示,其主要說明形成一矽化 物層;以及 第9圖顯示在根據本發明替代方法的子步驟之後,根據 本發明層配置的概要橫斷面表示,其主要說明形成用於該 雙閘極電晶體閘極區域的接點。 元件符號簡單說明: 1 0 0平坦化雙閘極電晶體 1 0 2第一接觸區域矽化物 _〇4第二接觸連接金屬 1 0 6以氮化石夕製成的封裝 1 0 8汲極區域 110第三接觸連接 11 2第四接觸連接 114以氧化矽製成的源極/ 11 5第一光微影遮罩 117第三光微影遮罩 2 0 0層配置 2 0 2第一氧化矽層 4第一氮化矽層 1 〇 1第一接觸連接金屬 103上方閘極多矽 105第二接觸區域石夕化物 107以氧化矽製成的封 1 〇 9源極區域 111第三接觸區域 11 3第四接觸區域 沒極區域封裝 11 6第二光微影遮罩 11 8第四光微影遮罩 2 0 1第一矽層 2 〇 3第二矽層 ) 第三氧化矽層 2 0 5第二氧化矽層(閘極氧化物 2 0 6第一多矽層(第一閘極) 207第一氮化秒層 208 2 0 9第二氮化石夕層(間隔器)The drawings briefly illustrate a schematic cross-sectional representation of a layer configuration of the present invention, which primarily illustrates the formation of a vaporized layer; and FIG. 9 shows a schematic cross-section of a layer configuration in accordance with the present invention after sub-steps in accordance with the alternative method of the present invention. Indicates that it primarily describes the formation of contacts for the gate region of the dual gate transistor. Brief description of the component symbol: 1 0 0 flattening double gate transistor 1 0 2 first contact region germanide _ 〇 4 second contact connection metal 1 0 6 package made of nitride nitride 1 0 8 drain region 110 Third contact connection 11 2 fourth contact connection 114 source made of yttria / 11 5 first photolithographic mask 117 third photolithographic mask 200 layer configuration 2 0 2 first ruthenium oxide layer 4 first tantalum nitride layer 1 〇1 first contact connection metal 103 upper gate electrode 105 second contact region austenite 107 is made of yttrium oxide yttrium 9 source region 111 third contact region 11 3 The fourth contact region has no polar region encapsulation 116. The second photolithographic mask 11 8 the fourth photolithography mask 2 0 1 the first 矽 layer 2 〇 3 the second 矽 layer) the third ruthenium oxide layer 2 0 5 Cerium oxide layer (gate oxide 2 0 6 first multi-layer (first gate) 207 first nitriding layer 208 2 0 9 second nitride layer (spacer)
第34頁 1289325 圖式簡單說明 31 0以矽鍺碳製成的層 41 2輔助晶圓 51 4第四氮化矽層 51 5第六氧化矽層 第七氧化矽層 第八氧化矽層 第一石夕化物層 第二矽化物層 第三矽化物層 第三金屬層 Ϊ28金屬層 3 11第四氧化矽層 41 3第五氧化矽層 516 618 720 722 724 ^26 閘極氧化物) 5 1 7第二多矽層 71 9第九氧化矽層 721第一金屬層 723第二金屬層 725第四矽化物層 8 2 7矽化物層 G -G、S-D 斷面線Page 34 1289325 Schematic description 31 0 layer made of germanium carbon 41 2 auxiliary wafer 51 4 fourth tantalum nitride layer 51 5 sixth layer of tantalum oxide layer seventh layer of tantalum oxide layer first layer Shixi compound layer second telluride layer third telluride layer third metal layer Ϊ28 metal layer 3 11 fourth ruthenium oxide layer 41 3 fifth ruthenium oxide layer 516 618 720 722 724 ^26 gate oxide) 5 1 7 Second multi-layer 719 9 ninth yttrium oxide layer 721 first metal layer 723 second metal layer 725 fourth vapor layer 8 2 7 bismuth layer G - G, SD section line
第35頁Page 35
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