TWI289325B - Planar double-gate transistor and method for fabricating a planar double-gate transistor - Google Patents

Abstract

The invention relates to a method for fabricating a double-gate transistor, having the following steps of: defining an active area on an SOI substrate. Forming a first gate region on the SOI substrate. Forming source/drain regions made of silicon-germanium in the active area. Forming a channel region from the silicon layer of the SOI substrate. Forming a layer having a plane surface above the SOI substrate, the source/drain regions and the first gate region. Bonding a second wafer to the plane surface and forming a second gate region opposite the first gate region.

Description

1289325 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to a planarized double gate transistor and a method of fabricating a flat double gate transistor. [Prior Art] With the advancement of the conventional planarization of oxidized metal semiconductor field effect transistors (MOSFETs) in the germanium technology, the performance of the respective components is particularly affected by the short channel effect. An undesirable short channel effect is as follows: as the gate voltage increases, the attenuation in the drain current increases, the correlation with the threshold voltage at the operating point, and the source region and the drain region φ Punch through. The composition of the double gate transistor may avoid difficulties in this scale that may occur from the short channel effect and create limitations. If the active region's the source/drain region and the region of the channel region are effectively thin, the short channel effect can be greatly reduced by controlling the two gates or a surrounding gate. Therefore, the dual gate transistor represents a candidate for a megabit integrated basic component. However, it can be used to make a double gate 'polar transistor, and the manufacturing technology implemented in a simple manner has not been established. There are many concepts discussed and tested for the manufacture of double gate transistors. These concepts are like vertical transistors, fin-type transistors, or flattened structures with an alternative gate. However, all of these concepts use complex processing that has not been tried and tested so far for manufacturing engineering in the technology. This overall manufacturing process is also complicated and expensive. In addition, the respective regions are not produced for a vertical transistor (for example,

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The flattened surface of the region current's damage pole' thus causes the flow to pass through the respective losses. Furthermore, the highly complex method steps required during the manufacture of the planarized double-gate electro-optic crystal = the problem is that the size of the body is Being reduced by step-by-step, for this multi-old: one of the double-gate electro-crystals, i knows the singularity of the complex manufacturing steps: and into the dopant - 'for example, the source region and the bungee Regional method orders will increase the requirements for precise positioning control. Especially in the subsequent source/drain regions, diffusion of dopants into the channel region poses a major problem. _ Another difficulty in the fabrication of flattened double-gate transistors is to ensure proper alignment of the two other electrodes. In other words, it must ensure that the two transistor gates are in a fixed spatial relationship with each other. Configuration. In the case of a planarized double gate transistor, the two gates of the transistor are at the same position on the substrate on both sides of the transistor channel region, and one of the eleven is disposed on the other, and the configuration thereof Between the source terminal and the drain terminal. In other words, the channel area is placed between the two gates. The generally prominent gate length is in the range of between about 10 nm and 20 nm, thus creating a height requirement for positive alignment. DE 1 02 23 709 A1 discloses a method of manufacturing a double gate transistor which forms a transistor on a tantalum insulator of a first wafer and forms a flat surface thereon. In addition, a second wafer is bonded to the flat surface of the first wafer, and a second gate region is formed on the first gate region of the germanium insulator. US 2002/0 1 05039 A1 discloses a method for manufacturing a double gate transistor

Law, with domain. Ϊ289325 A two-gate dielectric having a thin layer of a front multi-gate and a rear implanted area: a two-gate cooker as a channel area. SUMMARY OF THE INVENTION The present invention is based on providing a flattening double: and - A simple method of fabricating a flattened double idler transistor, in which the method is followed by a technical method step, and in this case, achieving a two-gate polarity with respect to each other is the use of the flattening double gate Polar crystal, to ^ one and still have a square 1 ί two! In the method of the present invention, an active region is defined on the reverse side of the first insulator of the first wafer, and then in the first method. A germanium insulator base of a wafer forms a first gate region, and a source/drain region is formed in the active region by a layer of material made of tantalum and niobium, at the source The remaining germanium layer between the drain regions is explicitly used as a channel 'region. The next step is to form a channel region from the germanium layer of the first wafer germanium insulator substrate, and then on the germanium insulator substrate, Forming a layer having a flat surface over the source/drain region and the first gate region. An H-wafer is bonded to a flat surface of the first wafer, and then at the first gate Opposite to the pole region, a second gate region is formed. ~ The planarized double gate transistor has a source region and a drain region 'a channel region disposed between the source region and the drain region, and precise configuration On the opposite side of the channel area Two gates. In addition,

Page 8 1289325 V. Description of the invention (4) The source region and the non-polar region have a material mixed with a stone and a sputum, and the ratio of strontium is preferably between 20% and 4%. between. Preferably, the source region and the drain region additionally have carbon as a material. With the method according to the invention, a planarized double gate transistor can be fabricated using known method steps of the technique, using simple and cost effective methods, which may also effectively prevent diffusion of the dopant atoms into the channel region 2. The independent patent application scope shows that a preferred development of the preferred development of the present invention in relation to a method of forming a double gate transistor is also applicable to a planarized double gate transistor according to the present invention. Preferably, the layer of tantalum has additional carbon material. This can accommodate the layer formed from the source/drain region, which is a carbon-germanium layer, that is, a layer of faulty carbon. With the method according to the present invention, a simple and cost-effective method can be utilized: manufacturing a planarized double gate transistor by a known method step of: a technology, can effectively avoid the doping + diffusion into the Channel Γ 2: Π carbon layer (SiGe: c layer) to form the lining and polar regions manufacturing method can be more flexible, because, - the pass zone i effect = ί debris diffusion into the Double gate electrode crystal ramen, known =::: in another - step and: manufacturing method selected use: two = degree caused by _ step, eve error: material by a small amount of carbon with a sub-proportion Between for example 2_2::::;:定=外=原"

1289325 ---__ . V. Description of the invention (5) ' ' • Small carbon carbon, preferably between 2% and 5% atomic ratio. The stone f f 乂 can exist as a crystalline structure, in this case a diarrhea-crystal where some of the ruthenium atoms are replaced by ruthenium atoms and a small amount of carbon is incorporated therein. Preferably, the insulator of the tantalum insulator substrate is made of yttrium oxide. The yttria is understood to mean cerium oxide (S i 〇 2 ). In a development, in the case of defining the active region, a platform structure corresponding to the active region is formed from the layer of the first wafer germanium insulator substrate. φ This clearly means that a portion of the germanium insulator substrate layer is replaced, and the upper layer of the germanium insulator substrate is removed by etching, and the germanium insulator substrate layer corresponding to the defined active region A portion of the area remains above the insulating layer. These remaining partial regions form a structure similar to a pedestal or watch, and thus are clearly referred to as a platform structure. Therefore, the formation of the platform structure involves removing the germanium layer of the germanium insulator substrate, and changing the underlying insulating layer to uncovered, which is preferably formed by yttrium oxide (S1 〇2), and then above it. Apply other layers. Preferably, on the germanium insulator substrate of the first wafer, a first insulating layer is formed in a region covered by the platform structure, and the b-edge layer has the same thickness as the germanium layer of the platform structure. This clearly means that the insulating layer, preferably made of nitride nitride, is formed in a region not covered by the crucible structure, so that the platform structure is completely identical to the crucible layer. The thickness of the insulating layer surrounds its circumference. This insulating layer can be used as a remnant in the step of (II)

Page 10 J289325 V. Description of the invention (6) Termination layer, and can effectively form insulation between the two gates of the flattened double gate transistor, that is, for the two gate regions to each other Power to engage. In particular, the channel region is also insulated from the gate region and the source/drain region by means of the insulating layer. In a development, the first gate region on the germanium insulator substrate is formed with the following steps: forming a first gate insulating layer on the germanium insulator substrate, and forming and patterning the first gate On the pole insulating layer, a first layer made of an electrically conductive material. Additionally, the first gate region is partially encapsulated with a non-electrically conductive material. The electrically conductive material from the upper layer of the first gate insulating layer is preferably formed of a plurality of turns after the subsequent formation of the first gate region. The encapsulation of the first gate region, that is, the first layer made of a conductive material, may be formed of tantalum oxide and/or tantalum nitride. The polysaccharide can be doped in an additional substep. The first gate insulating layer is preferably formed of yttrium oxide generated by partial oxidation of the tantalum layer of the first wafer-on-insulator substrate. The use of a preferred heat treatment method to form a tantalum oxide layer by oxidizing the tantalum layer portion of the tantalum insulator substrate is more effective for forming a gate insulating layer. In the development, the formation of the source/drain region has the following steps: patterning the uncovered region of the first wafer 矽 insulator substrate, and using the package of the first gate region as a mask, And patterning the first insulating layer. Further, the insulating layer ' of the first wafer-on-insulator substrate is patterned and the carbon-deposited carbon layer of the source/drain region is formed.

1289325 V. INSTRUCTIONS (7) 'The carbon layer of the stone is preferably formed from Sil xGexCy, wherein the value of χ is preferably between 0.2 and 0.4, and the value of 乂 is preferably It is located between 0.02 and 0. 05. Using the package of the first gate region as a mask to pattern the uncovered layer, making it possible to ensure that in a simple manner, in the subsequently formed first gate region, exactly Below a gate area, that is to say 'the processing method is self-aligned. The carbon layer of the source/drain region may serve as a etch stop layer during subsequent etching steps. A suitable etchant is required to have selectivity for the tantalum carbon layer φ such as EDP (ethylene diamine pyrocatechol), TMAH (tetramethylammonium hydroxide), potassium hydroxide (KOH) or choline (cho 1 i ne ). The high selectivity makes the proportion of niobium more than 20%. The formation of the niobium carbon layer can be carried out by selective epitaxy. Selective epitaxy is constructed by a method of achieving good formation control of the tantalum carbon layer or tantalum layer, that is, by way of example, the thickness of the deposited layer can be defined very accurately. Furthermore, it is possible to consider the lattice orientation of the respective layers, that is to say the formation itself and the second layer formed thereon. Forming a flat surface layer may be performed by forming a flat first layer of non-electrically conductive material on the germanium carbon layer on the source/drain region and the first gate region .

Page 12 .1289325 ^ V. INSTRUCTION DESCRIPTION (8) Due to the planarization of the surface, a second wafer can be more easily bonded in a subsequent wafer bonding step. This planarization is preferably performed. The chemical mechanical polishing method is implemented. In addition, after the planarization, a chemical and/or plasma activation step can be performed whereby the subsequent wafer, bonding step can be performed more simply and efficiently. The first layer made of a non-electrically conductive material is preferably made of oxidized stone. In a development, the formation of the second gate region has the following steps: patterning the insulator of the germanium insulator substrate and the germanium insulator substrate, and changing the germanium layer of the germanium insulator substrate to uncovered, and from the germanium A non-conductive thin layer on the insulating germanium substrate layer forms a gate insulating layer. Further, on the layer made of the source/drain region carbon layer, a second non-conductive thin layer is formed, and a second sidewall layer 0 made of a non-conductive material is formed. The material of the layer is preferably nitrite and/or oxidized stone. Preferably, the non-conductive thin layer is formed by oxidizing a layer of the tantalum insulator substrate and the source/drain region carbon layer. Oxidation of the ruthenium layer provides a simple way to form a ruthenium oxide layer as an insulator. The non-conductive thin layer formed by the erroneous carbon oxidation of the source/drain region can be used as a layer to avoid or at least reduce dopant diffusion during implantation of the dopant mold. The father of the vehicle is 'the formation of the second gate region, and additionally has the following steps: forming a second layer made of an electrically conductive material on the gate insulating layer, the source/drain region Refraction of the carbon layer of the crucible, < and forming a passive layer on the complete wafer of the insulative substrate

Page 13 1289325

Planarization. The second gate insulating layer is preferably formed by the doped = pole == two idle regions. The etch back of the germanium layer allows it to ensure that a short circuit, i.e., a conductive connection, is not formed between the source/drain region and the two gate regions in a simple manner. The pure layer is preferably formed of oxidized oxide and serves to insulate the planarized double gate transistor, that is, to insulate the double gate transistor from the outside. In a development, the method additionally has the step of contacting the first gate region φ domain and the contact connecting the second gate region. The contact connection of the first gate region may have the following steps: removing a portion of the passive layer, thereby changing a portion of the second gate region to uncovered. The second inter-regional region in the region that has become uncovered is removed, and the partial region of the first insulating layer is changed to uncovered. The first insulating layer in the region that has become uncovered is removed, the partial region of the first gate region is changed to uncovered, and the contact connection of the first region is formed. By means of these sub-steps, a distinct hole or trench (drain can be formed which allows the two gates to be contact-connected towards the outside. The contact connector can be acted upon by forming a metal layer in the hole. Preferably, a layer made of a stellite is formed in the uncovered region of the gate region to reduce the contact resistance of the contact connection before forming the metal layer as the contact connection. Preferably, Before the first insulating layer is removed, the first

1289325 V. INSTRUCTIONS (10) The second conductive layer of the second gate region is not frosted. The method of oxidizing the wood retanning region forms a method of oxidizing the second gate region by using a first conductive region to utilize the first conductive region and the second closed region. The formation is between the first and then connected by itself and insulated. The second interrogation region, the second interrogation region, is applied with a :; the first and the idle regions are controlled independently of each other. Therefore, the (4) gate region is thus crystallizable, and can be used as a type of memory: a double-question pole is formed; the description is used to fabricate a dual-gate memory chip. Single, known, tried and saved, with a simple flattening double-question transistor 乂 = processing steps, providing - seed layer, and the lithium insulator;;; Figure:: the insulator substrate Shi Xi As a mask, the method is =I;: the first gate region; the seal p A life begins to self-align, and the first gate region is correct relative to each other. The use of bismuth carbon - which is unknown in the prior art - and the possibility of providing a method that utilizes a simple type:::-supply-flattening double-gate transistor. Manufacturing a planarized double gate electrode = body species r; in: = "the semiconductor technology sub-step. According to the invention, the short channel effect is due to the sub-stepping of the crystal in one way because the two are idle The extreme effect is greatly reduced. In particular, the manufacturing process is based on the way of use.

Sun on page 15 1289325

V. INSTRUCTIONS (11) Smelling of carbon as a source/drain region is simplified - so far, the manufacture of double-gate transistors is unknown. In any case, the use of a layer of 矽锗., in other words a layer without carbon, also has the advantage that the layer of ruthenium can greatly reduce the diffusion of dopants. Especially when using a tantalum carbon layer, it has advantages for conventional materials. One is that the tantalum carbon layer is a material that can greatly reduce dopant diffusion 'that is, the dopant diffuses into the channel region of the planarized double gate transistor', thereby obtaining a better and more reliable channel region. control. The second is to provide additional degrees of freedom in the manufacturing process because it can use an etchant that selectively acts on bismuth carbon. According to the present invention, an additional advantage of the present method is that the source/drain region, that is, the layer under the insulating layer (carrier layer), is formed on a thick layer of a silicon-on-insulator substrate wafer. However, in the known method, the source/no-polar region is formed on the thin layer of the tantalum insulator substrate, that is to say the tantalum layer is located above the insulating layer. This simplifies the formation of the source/drain regions from the layer, and therefore, by way of example, the stress during the formation can be reduced. [Embodiment] A sub-step of a method according to the present invention for fabricating a planarized double gate transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic plan view showing an outline configuration of a double gate transistor 根据 according to the present invention. Figure 1 is mainly used to describe the schematic configuration of the double gate transistor 100, and is described in the fabrication of a double gate transistor according to the present invention.

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During the period of 100, different light lithography regions defined by the photolithographic masking method will be described later. In order to enhance the clarity, the package of the complete double gate transistor 100 is not described in the figure. The double gate transistor 1A according to the present invention has a lower gate region which is omitted in FIG. 1 and is preferably made of metal, a contact connection 1 0 1 As indicated, a first contact area 102 is preferably made of a telluride. Further, the double gate transistor 丨〇〇 has an upper gate region 1 〇 3 which is preferably formed by a plurality of turns. In addition, the second contact connection 104 and a second contact connection region 1〇5 are used to describe the upper gate region 103. The second contact connection 1 4 is preferably made of a metal, and the second contact connection region 丨 0 5 is preferably formed of a bismuth. The dual gate transistor 1A shown in Fig. 1 additionally has a package 106 which insulates the upper gate region 丨03 from the lower gate region 1〇1 from the outer < The package 106 is preferably formed of tantalum nitride (si3M4). Figure 1 additionally describes a first layer of ruthenium 7 made of yttrium oxide. The first layer 107, made of oxidized stone, is a package for the lower gate region contact connection 1 , 1 which insulates the lower gate region from the upper gate region 103. In addition, the double gate transistor 100 according to the present invention has a non-polar region 1 0 8 and a source region 1 〇 9 ' both formed by S i G ex Cy , wherein the value of x is better. The value is between 0·2 and 0·4, and the value of y is preferably between 0·02 and 0.05. In the source region 1〇9, a third contact connection 11〇 made of metal is preferably described.

Page 17 1289325 V. Invention Description (13) " — and a third contact area 111. The third contact region U1 is preferably made of a telluride. In the drain region 1 0 8 , a fourth contact port 2 made of metal and a fourth contact region 11 3 are preferably described. The crucible four contact regions 11 3 are preferably made of lithium. 1m s Figure 1 also depicts the package 114 of the active region, in other words, the source/drain region and the channel region (not shown in the figure),

It is used to insulate the source/drain region from external power. This package is formed by the method of yttrium oxide. X is intended to facilitate the subsequent illustration and fabrication of a planarized double gate transistor, which will be described with reference to the subsequent figures, which additionally depict the use of the cross-sectional illustration along the continuation of the description. The line, and the area in which the photolithography step is performed in the process of remanufacturing a flattened double gate transistor. Specifically, it is advanced along the planarized double gate transistor gate region. a section line GG, and a section line SD along which the source/nomogram area of the planarized double gate transistor is advanced. Further, the line segment 丨丨5 is used to indicate a first photolithography step. The photolithographic mask used, wherein the active region is defined, that is, the source/drain region and the channel region of the planarized double gate transistor. The line segment 116 is used to indicate a second light micro a photolithographic mask used in the shadowing step, wherein the planarized double-closed "electro-body gate region is defined. Line segment 1 17 is used to indicate a third photolithography step The light lithography mask used, which once again defines the active area 'that is the flat a source/drain region and a channel region of the double gate transistor. The line segment 11 8 is used to indicate a photolithographic mask used in a fourth photolithography step, wherein the planarization double gate is defined Under the polar transistor 1289325 V. Description of the invention (14) Contact hole in the gate region. Figure 2 shows a layer 200 configuration after the first sub-step of fabricating a flat-panel-electro-polar crystal 100 in accordance with the present invention. The cross-sectional view, which is the same as the cross-sectional illustration of Figures 3 through 6, is shown by the line segment SD in the second = 1. The respective sub-steps will be followed by 蛘 = description. The opening point for fabricating a planarized double gate transistor according to the present invention is a first layer 2 0 1 (carrier layer) made of tantalum, and a first layer made of yttrium oxide Layer 202 (insulator) and a second layer of germanium insulator substrate wafer (SO I wafer). The first photolithography step is then used to define the active of the double gate transistor. Region, that is to say applying an etching step, defining that the source will be formed at the end of the subsequent substeps a region of the domain and the immersed region. In this case, an optical impedance is applied to the second ruthenium layer 203 using a first mask, which corresponds to the mask indicated by line segment 115 in FIG. Then, the second layer 203 is silver engraved in a first step, thereby forming a platform structure of the second layer 203, that is, forming a pedestal of the second layer 203 or Is a class table, the pattern will correspond to the source/drain region and the channel region formed later. Then the residual of the optical impedance is removed. The buried first yttrium oxide layer .0 2 can be in the first surname step The middle layer is used as a touch stop layer. Then, a first tantalum nitride layer 2 0 4 is formed in a region where the germanium layer 2 0 3 has been removed by the first etching step. The first tantalum nitride layer 204 is preferably formed in an epitaxial manner and has the same thickness as the second tantalum layer 203. The tantalum nitride layer 220 is used for the first insulation. The first tantalum nitride layer is connected to the 2 0 4

Page 19 1289325 V. Description of the Invention (15) = In order to form the source/drain region U of the planarized double gate transistor to be electrically insulated between the lower idle regions, and the two closed = Insulation between, and as a kind of package. Specifically, the 4th s 204 is also used to insulate and define the channel region, which is formed from the second layer 2() 3 in the subsequent = step. The first nitride layer 2 〇 4 and the 矽 layer 203 have the same thickness, thereby avoiding unnecessary interfacial, and simplifies the subsequent planarization step. If the second tantalum layer 2〇3 and the tantalum nitride layer 2〇4 formed on the side have a large thickness causing mechanical stress, a first tantalum nitride layer 2〇4 may be used for the first tantalum nitride layer 2〇4. The layer of instrument 0, thereby reducing mechanical stress. The first tantalum nitride layer 2〇4 is used as an etch stop layer in the subsequent method step. The surface of the layer configuration will then be flattened and the second layer 2 〇 3 will act as a terminator. This planarization is preferably carried out by chemical mechanical polishing (CMP). The planarization ensures that a surface elevation is produced, and the thickness of the second tantalum layer 203 and the first tantalum nitride layer 204 are the same. In the next method step, the second tantalum layer 203 is partially oxidized, thus forming A second hafnium oxide layer 205, which will then serve as a gate insulating layer for the lower gate region. A first layer 2〇6 made of a plurality of tantalums, a second layer 207 made of nitride nitride, and a r 2 0 8 made of oxidized hair are sequentially formed. The lower gate region is then formed by the first Dolomite layer 206, and then the second gate layer 2? 7 forms a package for the lower gate region. The third oxidized dream layer 208 can then be used as a protective layer for the second tantalum nitride layer 207 in the surname step. A second photolithography step is then performed. For this purpose, use - second

Page 20 1289325 V. INSTRUCTIONS (16) The mask acts as an optical impedance, which corresponds to the area indicated by the line segment 丨6 in Figure 1. Thereafter, the third yttria layer 2 〇 8 , the second tantalum nitride layer 207 , and the first layer made of the ruthenium 20 6 are etched in a second etching step. The second hafnium oxide layer 2, 5, which forms the gate insulating layer of the lower gate region, is treated as an etch stop in this case. The remaining optical impedance is then removed.

Thereafter, a third layer 2〇9 made of tantalum nitride is formed, which is preferably carried out in a conformal deposition manner. The third layer of nitride nitride is then subjected to an anisotropic (four) in a subsequent step, whereby a spacer 209 is formed. The first &&; ΟΛ [: + _ μ clothing as - (four) termination layer up to # I # # 矽 矽 间隔 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 209 。 。 。 。 。 。 。 The second hafnium oxide layer 205 is then etched in a fourth engraving step; the lower gate 209 can be used as a one in this case. The mask is preferably a sub-step of the first embodiment, [the lower gate of the gate transistor v ^ ^ forms the tandem double package. The region, and the μ on the germanium insulator wafer, will refer to FIG. 3, illustrating a substep of the method for fabricating the germanium double gate, the gamma + / 卞 化 双 双 双 双. , to illustrate the formation of a channel region and the source / / ^ ^ 2 图 2 description of the layer sequence begins 'the second Shi Xi Lu 203 is in the Chu five etching step is not a 笠疋 in the first is the spacer 209 Then do A ° : etch 'the lower gate region, which is also a mask. The first insulator of the germanium insulator wafer - oxygen 1289325 ---------- five, invention description (17) 'a "" -------- a "'one" Layer 2 0 2 acts as an etch stop layer. The first tantalum nitride layer 2 〇 4 is etched in a manner selective to a sixth anisotropic etch step. The first ruthenium oxide layer of the Ershixi and 邑 体 body wafers is used as an etch stop layer. Hunting by the flute ^ + 丨! The force ^ residual step removes the complete first tantalum nitride layer 2〇4 from the region below the lower gate region. The angle of view in Fig. 3 is because it is located behind the section line SD, so the area of the area and the second part of the first layer of tantalum nitride 204 cannot be seen in Fig. 3 for the purpose of The source/drain region, the gate of the planarized double-gate transistor, the edge, and the insulation for the channel region. 1 column when implementing the sixth snippet step During the sixth two steps, the spacer 2 〇 9 is also exposed to the etchant, and the result of etching the etchant is as follows. Part of the spacer 209 made of tantalum nitride is removed. In order to ensure sufficient encapsulation of the square gate region, in other words, insulation, during the formation of the second spacer 209, even after the sixth etching step , which still has sufficient insulating properties, that is, it is formed by a sufficient 'two=. As an alternative, it is also possible to form a thin layer of bismuth on the spacer 2〇9. During the sixth etching step, the spacer 2 0 9 is protected. After the sixth etching step, The first oxidation of the germanium insulator wafer is performed in a seventh remaining step. This is preferably a non-isotropic etching implementation of the dwarf county. For the seventh etching step, the crucible is crying. The round first layer 2〇1 can be used as an etch stop, and the spacer 209 can be used as a mask again.

Page 22 1289325 V. INSTRUCTION DESCRIPTION (18) Thereafter, in the active region, a tantalum carbon layer 3 1 0 ' is selectively formed, that is, in a region where the source region and the drain region are formed. The formation of the carbon-wound carbon layer is carried out by epitaxy. The 矽: the atomic ratio of 锗 is in the range of 4:1 to 3 ·· 2, and the proportion of carbon is between 2% and 5%. Using the formation of selective epitaxy, avoiding the mechanical stress formed between the first layer of erecting layer 20 1 and the layer of tantalum carbon layer 3 because if yttrium, lanthanum, and carbon are selected in an appropriate manner, The grid constants of the two layers of material will coincide with each other, that is to say without a large difference from each other. • Thereafter, on the layer sequence, a fourth layer 311 made of yttrium oxide is formed and then planarized. Preferably, the planarization acts in a chemical mechanical polishing manner. ^ " The channel region and the source/drain region of the planarized double gate transistor are formed by the substeps described in Fig. 3. In this case, the channel region is formed by the second layer 2〇3 of the germanium insulator wafer. Next, a sub-step for fabricating the planarized double gate transistor/method will be described with reference to Fig. 4, which primarily illustrates the preparation and implementation of wafer bonding. Starting from the fourth yttrium oxide layer 3丨i of the third layer sequence, it is activated by chemical or plasma methods after it has been planarized. An auxiliary wafer 3 has a fifth thick layer 413 cut by oxygen. If the material of the auxiliary crystal :) 2 is ruthenium, the fifth ruthenium oxide layer 41 3 can be formed by thermal oxidation of the auxiliary ruthenium, 41 2 . The layer sequence described in Fig. 3 is bonded to the fifth layer 41 3 of the auxiliary wafer 412 by the flat surface of the f-th layer 311. This layer sequence is inverted in subsequent substeps. because

Page 23 1289325 V. INSTRUCTIONS (19) Therefore, starting from Fig. 4, the sequence of the layer is rotated and displayed in the subsequent illustration, so that the top and bottom are exchanged in comparison with Fig. 4 and Fig. 3. of. A sub-step of the method for fabricating the planarized double gate transistor will now be described with reference to Figure 5, which primarily illustrates the formation of a second gate region. The first germanium layer 21 0 (carrier layer) of the germanium insulator wafer is removed from the layer sequence from Fig. 4'. This is preferably carried out by a grinding method or a method of intelligent cutting. Thereafter, in an eighth etching step, the possible residue of the first layer 121 is selectively etched back in the form of an assay solution. The etch back can be carried out by means of EDP (ethylene diamine g^yrocatechol) > TMAH (tetramethy1ammonium hydroxide), potassium hydroxide (K〇H, p〇tassium hydr〇xide) or choline. The enumerated etching solution is highly selective for cerium when the cerium ratio is higher than 20%. In addition, 矽 carbon is also suitable as an etch stop in most alkaline solutions. This height selectivity is greatly simplified in such a way as to remove the possible residual of the first layer 201. Cerium nitride and antimony telluride also act as an etch finish, especially if etching is carried out as an alkaline solution. The first yttrium oxide is then removed in a ninth etching step for the purpose of ruthenium, osmium carbon and tantalum nitride: and is = surname. This step defines the formation of the second gate = the upper interpole region. The ninth is true; = = above the lower idler region, in this #刻 step: indeed: with '' used as an etch stop: the second layer of the channel region 2x03 1289325 Note (20) that the carbon layer of the source/drain region is still above the lower gate region 206, in Figure 5 because it is located along the layer in the direction of Figure 5 The first tantalum nitride layer that is indistinguishable from the section line used for the sequence section. In this case, as already described, the first layer of nitride layer 204 has a thickness similar to that of the second layer. This is ensured by this first flattening step. In this case, the tantalum carbon layer 31〇 forms the lateral boundary of the dumped region and serves to support the self-alignment of the manufacturing method. ', 议可# Um step a few in the area etched by Shaoxiang, a fourth layer 514 made of nitriding zepa is used to encapsulate the second wind region with less wind, that is, above The spacer of the gate region is formed by the fourth nitrogen layer 514 in a subsequent anisotropic etching in the tenth etching step. In forming a fourth layer of tantalum nitride, a layer of ruthenium oxide is first formed in the same region. Further, it is preferred to carry out an oxidation step. The oxidizing step uses a ruthenium layer 515, which is formed by the partial oxidation of the double gate electric 7 - sixth oxygen 5 stellite layer 2° 3 , as the first thin side of the idle In a push step = free = - seventh oxygen t number nanometer thickness. After the expansion of the government, and only after, a second multi-layer 517 is formed, which is carried out by means of chemical mechanical polishing. The flattening may be performed as a second layer of the seventh gate oxide layer 517 during the planarization step to form the second one of the double gate transistor. The second multi-stone eve his & field, that is, the above 1289325

Square gate, domain. The second multi-layer 517, that is, the upper closed region, is then preferably slightly backed #, which may avoid the upper pole region 517 and the germanium carbon forming the source/drain region A short circuit that may form between layers 3 ι. The formation of the fourth inter-polar region ', i.e., the upper gate region $17, ends in the sub-step manner described in FIG. Referring now to FIG. 6, a sub-step of a method for fabricating the planarized double gate transistor will be described, which mainly illustrates the formation of the double gate insulating layer, mixed with the tantalum carbon layer 3 1 A source/drain region formed by 0, and an upper gate region formed by the second plurality of germanium layers 5丨7. In this case, the source/drain region is doped with an effective energy throughout the seventh yttria thin layer 516, which is a so-called screen oxide layer. In the source/drain region, it is possible to achieve a more uniform doping atom distribution. The seventh tantalum oxide layer 5丨6 is then removed by an eleventh selective etching step. A slight selective etch back of the tantalum carbon layer 31 0 is then carried out in a twelfth etching step. The twelfth etching step avoids a short circuit which may be formed in the upper surface of the first electrode region 51 7 and the tantalum carbon layer 3B forming the source/drain region. A third photolithography step is then performed in a manner that redefines the active region, and a second insulation is formed which forms the full insulation of the complete dual gate transistor. For the third photolithography step, a third mask is used as the optical impedance, which corresponds to the line segment indicated by the line segment 丨 17 in Fig. 1.

1289325 V. INSTRUCTIONS (22) After applying and developing the optical impedance, part of the carbon layer 3丨〇 is in the 12th step of the 12th rhyme. The fifth oxidized layer 41 3 is terminated as a moment. Thereafter, the residual of the optical impedance is removed, and an eighth thick layer 618 made of yttrium oxide is deposited on the layer sequence. The eighth ruthenium oxide layer 618 is a layer that ensures that the complete double gate transistor is insulated from the outside. Reference will now be made to Figures 7A and 7B to illustrate an alternative to how the two gate regions of the planarized double gate transistor can be contacted. The cross section in the first and seventh diagrams, in this case, is taken along the G-G line from the i-th diagram. • Referring to Figure 7A, an exemplary embodiment will be described in which a first contact connection for the pole region 517 is formed and a second contact connection for the lower 2H206 is formed. Therefore, different voltages can be applied to the upper gate 22' and the lower gate region 206. This is advantageous for a flattened dual-electrode transistor that can be used as a memory chip with this different bit'. Step ί Ϊ 6 begins with the „layer sequence, the implementation-fourth photolithography step uses a fourth mask as the light segment 11 8 . Then the silk a flute L hunger should be in the brother 1 T The partial isotropic etching step of the eighth oxidized layer 618, the contact connection C of the removal/question pole region 206 is then carried out for the lower layer 5 丨 7 as an etch line Re-supplied with the second plurality of upper idle regions 517 of the upper gate region: the second multi-layer 517 is then removed in the sexual etching step, in the first field, a fifteenth Non-isotropic stop layer. The first gasification layer 204 is used as an etch stop.

$27页 1289325 V. INSTRUCTIONS (23) The remaining light impedance remains in the eve of the stone. Thereafter, the second two: controlled thermal oxidation of Fang Fufeng is performed, which oxidizes the second multi-layer to become an uncovered region in the manner of the fifth step to form - ninth = Γ, 9 . The ninth oxidized stone layer 719 is used as a kind of (four) first-closed ^ ^ for the insulation of the second gate region, so that no short circuit is caused between the two gate regions, and thus the two gates can be Different voltages are applied to the area. Thereafter, the region of the first nitride layer 204 that becomes uncovered in the fifteenth etching step is shifted in a sixteenth anisotropy step, resulting in "the lower gate region 2 〇 6 That is, the portion of the first multi-layer 2 〇 6 becomes uncovered. The first multi-layer 2 〇 6 of the lower gate region is in this sixteenth etching step as an etch stop. Thereafter, a thin metal layer is formed on the lower gate region 206 from the sixteenth etching step to an uncovered region, and the first plurality of germanium regions 2 〇6 of the lower gate region 2 〇6 are formed. In the evening, a first vaporization layer 720 is formed which reduces the contact resistance of the contact connection of the lower gate region 206. Next, a first metal layer 721 is formed on the first lithi layer γ 2 ,, and the first metal layer 721 represents contact to the lower gate region 206. The contact connection of the lower gate region 206 is terminated by the substep described. Next, in a similar manner, the second multi-fracture layer 517, that is, the contact connection of the upper gate region 517, and a second lithium layer 722 and a second metal layer 723 are formed. In order to form the contact connection of the upper gate region 517, a first implementation is implemented.

Page 28 1289325 V. INSTRUCTIONS (24) Five-light lithography steps. For this purpose, a second mask is used as the optical impedance, which substantially corresponds to the contour of the second contact region 1 〇 5 in FIG. Next, a seventeenth anisotropic etching step is performed, which removes a partial region of the fifth gasification layer 513, wherein a contact connection formation for the upper gate region 51 7 is subsequently performed, the upper gate region The second multi-stone layer 5丨7 is used as a silver engraving stop layer. Then, a thin metal layer is formed on the upper gate region 517 by the seventeenth etching step to become an uncovered region, and the first multi-layer 517 of the upper idle region is formed. This forms a second layer of hardened layer 722, 4 which is less than the contact resistance of the upper gate region 5 17 contact connection. A second metal layer is then formed on the second germanide layer 722, the second metal layer being in contact with the upper gate region 516. To form a planarized double gate transistor sub-step, the resulting planarized double gate transistor is as described with reference to FIG. 7A. Referring to FIG. 7A, an exemplary embodiment will be described in which an exemplary embodiment is described. A common contact connection is formed for the upper gate region 517 and the lower gate region 2〇6. Therefore, the same voltage can be applied to the upper gate region 517 and the lower gate region f 6 , and the control effect of the two gates k region can be used for the channel region. Starting from the layer sequence depicted in Fig. 6, a sixth photolithography step is performed which uses a fourth mask as the optical impedance, corresponding to line segment 117 in Fig. i. An eighteenth anisotropic etch step is then performed, which removes a portion of the fifth oxidized layer 513, which is then implemented for the two

Page 29 1289325 V. Description of invention (25)

A contact connection is formed in the gate region, and the second gate region 517 is used as an etch stop layer. In the uncovered region of the gate region of the second plurality of germanium layers B, the first is removed, and the first nitrided layer is removed as the upper eight steps. The residual optical impedance remaining is then removed. Thereafter, a third metal thin layer is applied to the uncovered region of the second eve layer 517, and the uncovered region of the eve of the celestial layer 517 is formed, thereby forming a third ruthenium layer 714, which reduces the contact resistance of the upper gate region 5丨7 contact connection. Then, a nineteenth anisotropic first step is performed to remove the first tantalum nitride layer 2〇4 region which becomes uncovered in the first insect step, so the square gate, that is, The portion of the first multi-layer 206 is rendered uncovered. The lower gate region first multi-layer 2 〇 6 is used as an etch stop in this nineteenth etch step. Thereafter, on the region where the lower gate region has been changed from the nineteenth etching step to the uncovered region, a thin metal layer is formed and the first plurality of germanium layers 2 〇 6 of the lower gate region are deuterated, thereby forming a The fourth vaporization layer 7 2 5 reduces the contact resistance of the contact region of the lower gate region 2 〇6. A third metal layer 726 is then formed over the fourth germanide layer 725, the third metal layer representing contact to the lower gate region 2〇6. As an alternative to the two separate deuteration steps, a single addition step can also be utilized, that is, the second lithiation layer 724 and the fourth vaporization layer 7 25 are formed in a single deuteration step. That is, the formation of the third vaporized layer 724 is not performed before the nineteenth anisotropic etching step. The contact between the two gate regions will be completed by means of a sub-step

Page 30 1289325

V. INSTRUCTIONS (26) Connect 'and form the planarized double gate transistor. Referring to Figures 8 and 9, an alternative will be described. The alternative method steps described herein are the same as the reference to the second method step. Only for the methods described in Figures 6 and 7B" [Ancient: Jin changes. In the alternative method described herein, the basic difference is that in the second step, the lower gate region 206 and the upper gate region are in the domain 7, and the layer of tantalum carbon 310 is used to form a layer of germanium. For this purpose, before the eighth oxidized stone layer 618, the first multi-layer 2〇6, which is the lower domain 2, is completed by using the first-to-the-story layer 2()6^=sub-region A contact connection of 0 6 is performed by performing an etching step. In a combined deuteration step, a deuterated layer 827 is formed on the crucible region of the first multi-layer 206, the tantalum carbon layer 31 and the second multi-layer 517. A layer sequence 800 of the eighth yttria layer 618, ^ 'Fig. 8 t, is then formed. U. This is an additional step in the description of the alternative method, which is carried out according to the method described in the above reference. The double gate field effect transistor thus formed is identical in Fig. 9, and is shown in Fig. 1 in a cross section. In summary, the present invention relates to a method of fabricating a planarized self-aligned double gate crystal having known, simple, and cost effective methods of semiconductor technology. The respective sub-steps of the present invention are integrated, and the resulting short-channel effect of the double-gate transistor is greatly reduced by the control effect of the two gates. Moreover, this fabrication step can be simplified by using the germanium layer as the source/drain region, which is unknown in the fabrication of the previous double gate transistor. Use of bismuth and especially carbon

Page 31 1289325

It has advantages for traditional materials. Μ 1 The first is that the carbon layer is a material that can avoid or at least greatly reduce W and diffuse the impurities. That is, ^ Μ Α ^ ^ also diffuses the dopant into the flattened double gate. Crystal, the domain, thereby obtaining a better and more reliable channel = a possibility offered in the manufacturing process, because it can use an etchant that has a selective action on germanium carbon. In the manufacturing step, a new degree of freedom is opened using an etchant selective for ruthenium carbon. According to the present invention, an additional advantage of the present method is that on a thick layer of an anti-wafer layer of an insulator layer j Forming the source/drain region, that is, the layer under the insulating layer (carrier layer), however, in the known method, the source/drain region is formed on the germanium insulator substrate On the layer, that is to say the layer is located above the insulating layer. This simplifies the formation of the source/drain regions from the layer, and therefore, by way of example, the stress is reduced during the formation.

Page 32 1289325 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a schematic plan view of a planarized double gate transistor illustrating an overview of a dual gate transistor in accordance with the present invention; and Figure 2 shows a first implementation in accordance with the present invention. After a sub-step of the method, a schematic cross-sectional representation of a layer configuration in accordance with the present invention, which primarily illustrates forming a first gate region of the dual gate transistor; FIG. 3 shows a first embodiment in accordance with the present invention After an additional sub-step of the method, a schematic cross-sectional representation of a layer configuration in accordance with the present invention, which primarily illustrates forming a channel region and a source/drain region; FIG. 4 shows an additional method in accordance with a first embodiment of the present invention. Sub-steps, a schematic cross-sectional representation of a layer configuration in accordance with the present invention, which primarily illustrates a wafer bond; Figure 5 shows a layer in accordance with the present invention after additional sub-steps of the method in accordance with a first embodiment of the present invention. A schematic cross-sectional representation of the configuration, which primarily forms a second gate region; ', 1 and 6 are shown in a sub-step of the method according to a first embodiment of the present invention, According to a schematic cross-sectional view of the layer arrangement of the present invention, it is mainly said that the double gate insulating layer is insulated; FIG. 7A shows a schematic diagram of a layer configuration according to the present invention in accordance with a first embodiment of the present invention. Transverse table: used for the double idle pole crystal idle region = connected to the second τ, which is illustrated in Figure 7B, which is shown in the outline of the layer configuration according to the present invention according to the present invention, with = square == a contact for the gate region of the double gate transistor; FIG. 8 shows the substeps of the alternative method according to the present invention, according to

Page 33 1289325

The drawings briefly illustrate a schematic cross-sectional representation of a layer configuration of the present invention, which primarily illustrates the formation of a vaporized layer; and FIG. 9 shows a schematic cross-section of a layer configuration in accordance with the present invention after sub-steps in accordance with the alternative method of the present invention. Indicates that it primarily describes the formation of contacts for the gate region of the dual gate transistor. Brief description of the component symbol: 1 0 0 flattening double gate transistor 1 0 2 first contact region germanide _ 〇 4 second contact connection metal 1 0 6 package made of nitride nitride 1 0 8 drain region 110 Third contact connection 11 2 fourth contact connection 114 source made of yttria / 11 5 first photolithographic mask 117 third photolithographic mask 200 layer configuration 2 0 2 first ruthenium oxide layer 4 first tantalum nitride layer 1 〇1 first contact connection metal 103 upper gate electrode 105 second contact region austenite 107 is made of yttrium oxide yttrium 9 source region 111 third contact region 11 3 The fourth contact region has no polar region encapsulation 116. The second photolithographic mask 11 8 the fourth photolithography mask 2 0 1 the first 矽 layer 2 〇 3 the second 矽 layer) the third ruthenium oxide layer 2 0 5 Cerium oxide layer (gate oxide 2 0 6 first multi-layer (first gate) 207 first nitriding layer 208 2 0 9 second nitride layer (spacer)

Page 34 1289325 Schematic description 31 0 layer made of germanium carbon 41 2 auxiliary wafer 51 4 fourth tantalum nitride layer 51 5 sixth layer of tantalum oxide layer seventh layer of tantalum oxide layer first layer Shixi compound layer second telluride layer third telluride layer third metal layer Ϊ28 metal layer 3 11 fourth ruthenium oxide layer 41 3 fifth ruthenium oxide layer 516 618 720 722 724 ^26 gate oxide) 5 1 7 Second multi-layer 719 9 ninth yttrium oxide layer 721 first metal layer 723 second metal layer 725 fourth vapor layer 8 2 7 bismuth layer G - G, SD section line

Page 35

Claims (1)

1289325 Case No. 94322767 Amendment - VI. Patent Application No. 1. A method of manufacturing a planarized double gate transistor having the following steps: defining an active region on a germanium insulator substrate of a first wafer. Forming a first -p 3 ' 耷 in the active region of the wafer, the source region is formed by a layer made of germanium, and the remaining between the source and the gate region is formed. The 矽 layer is imitation", the track area; ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ formed on the 矽 insulator substrate, the source / the second region of the region has a flat The layer of the surface / the inner layer of the Ϊ :: two; 曰; round bonded to the flat surface of the first wafer; and contains carbon. , spoon method, in which the layer made of tantalum 3 · as claimed in the scope of the r The insulator of the step substrate is a method of oxidizing, wherein the germanium insulator 4 is as described in the patent application, the method of the active layer 5 of the insulating substrate, the first wafer of the first wafer Taiwan (MESA) structure. The area 'has a form similar to the tabular form of the patent. The fourth section of the patent, the Shishiyuan body substrate, is not 'no', 'where the first insulating layer is formed in the first wafer, In the coverage area of the second 3 platform structure, the thickness of the shape...the insulating layer has a 128-9325 _ case number 94122767 with the platform structure 六 layer, and the first gate region is formed on the edge substrate of the patent application scope. The following steps: forming a first gate insulating layer on the germanium insulator substrate; on the first gate insulating layer, the #1 is opened, patterned and patterned into a first electrically conductive material a layer; and ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Ί bamboo ^ partially encapsulates the first gate region from a non-electrically conductive material. 7. If the prescription of the sixth item of the patent scope is from the 兮 日 3 α 屉 e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e e The basin p is formed by oxidized sand. ^,, produced by the dream layer emulsification of the corpus callosum The method of claim 7, wherein the forming the source/drain region has the following steps: patterning an uncovered layer of the germanium insulator substrate of the first wafer, using the first gate The encapsulation of the region is used as a mask; the first insulating layer is patterned; the insulating layer of the germanium insulator substrate of the first wafer is patterned; and the carbon/carbon layer of the source/> and the polar region is formed. 9. The method of claim 8, wherein the formation of the tantalum carbon layer is carried out in a selective epitaxial manner. The method of claim 8, wherein forming a layer having a flat & tan surface is formed by using a source carbon layer on the source/drain region and the first gate region Implemented as a flat first layer of non-electrically conductive material. The method of claim 255, wherein the forming of the second gate region has the following steps: patterning an insulator of the dream insulator substrate and insulating the mineral insulator base Page 37 1289325 1289325 —-— Case No. 94122767 VI. Patent Application _ Domain Mode, the part of the first insulating layer is removed, and the part that has become unpaid #A becomes uncovered; The pole "forms the first gate region contact ^= is accepted as uncovered; and - before the insulating layer, the first _ _ /;, in the removal of the first covering region is oxidized to form a non-transfer ^ ^ The second conductive layer of the morphological domain is not in the form of a selective epitaxial manner. / V,, ^ Formation of 矽锗 layer 1 8 · A planarized double gate transistor having: a source region and a drain region; a channel region disposed between the source region and the drain region · precisely disposed in the channel region Two gates on opposite sides: the source region and the non-polar region have a carbon material, and the ratio of germanium