TWI284364B - Method of forming a contact window - Google Patents

Abstract

A method of forming a contact window is described. A substrate having several gate structures thereon is provided. Then, a liner is formed on the sidewall surfaces of the gate structures and the substrate that are not covered by the gate structures. A dopant is implanted in the liner of the sidewall surfaces of the gate structures to make the liner on the sidewall surfaces of the gate structures and the substrate have different etch selectivity. A thinning process is performed to remove partial the liner, and the remained liner located on the substrate is thicker than that located on the sidewall surfaces of the gate structures. Then, spacers are formed on sides of above gate structures. An insulating layer is formed over the substrate, and then patterning the insulating layer to form a self-aligned contact between two adjacent gate structures.

Description

1284364

TECHNICAL FIELD The present invention relates to a semiconductor process, and more particularly to a method of fabricating a contact opening. Previously, with the advancement of semiconductor technology, the size of components has continued to shrink, and it has entered the field of deep submicron. As the integration of integrated circuits increases, the surface of the wafer can no longer provide enough surface to make the required interconnects, so the added interconnects are added to match the components. Line requirements, the design of two or more layers of multi-layer metal 7 wires has become a must for ultra-large integrated circuit (VLSI) technology. On the other hand, if a different metal layer is to be turned on, it is necessary to form an opening in the insulating layer between the two metal layers and fill the conductive material ' to form a plug structure for conducting the two metal layers. ^ In order to overcome the ever-increasing line width and prevent misalignment of the contact window, many semiconductor components are usually designed with self-aligned contact windows. Particularly in memory devices, the manner in which the doped regions in the substrate are electrically connected to the bit lines formed over the substrate is typically a self-aligned contact window design. 1A to 1F are schematic cross-sectional views showing a manufacturing process of a contact opening in a memory device. Referring to FIG. 1A, a substrate 1 is provided. A gate structure 112 having a cap layer 110 is formed on the substrate 1 and each gate structure 112 includes an interlayer dielectric layer 104 and a polysilicon layer. 1 〇6 and metal telluride layer 1 0 8. It allows the substrate 100 to be divided into a memory cell region 102 and a peripheral circuit region 103.

1284364 V. DESCRIPTION OF THE INVENTION (2) The memory cell region 1 0 2 is a pattern dense region, that is, the gap between adjacent two gate structures 11 2 is small. The peripheral circuit area 1 〇 3 is a pattern loose area, that is, the gap between the adjacent two gate structures 11 2 is large. Next, referring to FIG. 1B, an etching step of the metal telluride layer 1 〇8 is performed to remove a part of the thickness of the sidewall of the metal telluride layer 1 〇8, so that the metal telluride layer 10 8 a is recessed compared with other layers. . Then, please refer to Figure 1 C for a thermal oxidation process to form an oxide layer on the sidewall of the gate structure 112 and the surface of the substrate which is not covered by the gate structure 丨丨2. Liner) 114. Since the thickness of the sidewall of the metal telluride layer 1 〇 8 has been removed in the previous step, the metal bismuth layer 丨〇 8a can be prevented from being laterally convex due to grain growth during the thermal oxidation process. ). Subsequently, please refer to FIG. 1D to form a photoresist layer 11 6 over the substrate 1 〇 以 to cover the peripheral circuit region 1 〇 3. Next, a sidewall oxide layer (S i d e w a 1 a 〇 X i d e, S W 0 X ) is etched to thin the underlying oxide layer 11 4 exposed by the photoresist layer η β to form a lining oxide layer a 4 a. Here, the purpose of thinning the lining oxide layer 中4 in the memory cell region 102 is to increase the width (opening) of the space (opening) and reduce the aspect ratio thereof to increase the processing window for subsequent etching or deposition. (process, please, according to FIG. 1E, after removing the photoresist layer 116, a gap nib 8 is formed on the sidewalls of the gate structure 112 and the cap layer 1 1 。. The method for forming the spacers 118 is After the tantalum nitride layer is formed on the structure formed above (not shown), the spacer layer 118 is formed by anisotropic etching of the tantalum nitride layer. However, since the thickness of the liner oxide layer 114a in the region 102 is relatively high.

11676twf.ptd Page 8 1284364 V. INSTRUCTIONS (3) Thin, so at this time, during the anisotropic etching process, the exposed oxide layer 11 4 a may be partially removed or even completely It is removed to expose the surface of the substrate 100. In May, referring to Figure 1F, an insulating layer 12 2 沉积 is deposited on the substrate 1 〇 . Then, 'performing the ink engraving process' to pattern the insulating layer 1 2 〇, and forming a corresponding one of the adjacent two gate structures 丨丨 2 in the cell region 102 to align the contact window opening (self-aligned contact. It is worth noting that since the surface of the substrate 100 in the region 1〇2 may have been exposed in the previous step, and to ensure that other contact window openings (not shown) expose the substrate 1〇 〇, therefore, during the etching process of self-aligning the contact opening 122, it will be directly etched to the surface of the substrate, so that damage ln will be caused in the region 1〇2. A doped region (not shown) is formed in the substrate 1 at the damage 117, so if it is damaged, it may cause a problem of junction leakage of the component. Therefore, in order to remedy the substrate The damage of the surface of the 100 causes insufficient concentration of the doping region, and usually requires an additional ion implantation step to ensure that the concentration of the doping region is sufficient. Thus, the process steps are complicated and may cause short channels. In view of the above, it is an object of the present invention to provide a method for manufacturing a contact opening to solve the problem of easy damage to the surface of the substrate during the process of opening the contact opening. The problem of junction leakage is another object of the present invention is to provide a method for manufacturing a contact opening, 11676 twf. ptd, page 9, 1284364. V. Description of the invention (4) To solve the complicated process of the contact opening of the conventional bit line Disadvantages of the Invention The present invention provides a method of fabricating a contact opening by first providing a substrate on which a plurality of gate structures have been formed. Thereafter, a sidewall is formed on the sidewall of the pole structure and the substrate not covered by the gate structure Liner. Next, the lining of the sidewall of the gate structure is implanted with a dopant, and the lining on the sidewall of the gate structure and the lining on the surface of the substrate are η: selective. The method of implanting the lining of the sidewall of the pole structure is, for example, performing a tilt ion implantation step, and the implant material is, for example, accelerated to be located in the gate structure. The nature of the removal of the lining of the wall, such as nitrogen ions or inert gas ions. After the thinning step, the thinning step is performed to remove a portion of the liner. The +, leaving the liner on the surface of the substrate The thickness is greater than the thickness of the sidewalls of the gate structure. Next, spacers are formed on both sides of the gate structure. Subsequently, a dielectric layer is squared on the substrate, and the insulating layer is patterned to form self-aligned contacts between the phases Window opening. Mn gate structure Since the present invention first processes the liner of the sidewall of the gate structure = the subsequent step of the thinning step, the rate of the layer on the sidewall of the gate structure is greater than that on the surface of the substrate The lining layer is removed κ so that a wider gap between adjacent two open-pole structures can be added to increase the process window for subsequent etching or deposition. 由于You are using the method of the present invention. After the thinning step, the thickness of the unremoved liner on the bottom surface is thicker, so that the spacers can be formed on both sides of the gate, and the spacers can be formed on both sides of the structure and subsequently self-aligned. 11676twf.ptd Page 10 I284364

In the case of the 2-window process, the surface of the substrate is damaged by the etching process, and further, since the method of the present invention can avoid damage to the surface of the substrate (doped region), it is possible to prevent leakage of the junction. In addition, with the manufacturing method of the present invention, it is also possible to make up the process steps by eliminating the need for additional ion implantation steps to complement the doping concentration. Another method for fabricating a contact opening is provided by the present invention. The method first provides a substrate having a memory cell region and a peripheral circuit region, and a plurality of gate structures are formed on the substrate. Thereafter, a lining is formed on the sidewalls of the gate structure and the substrate not covered by the gate structure. Next, the liner is subjected to a dopant implantation step to provide a different etch selectivity to the liner of the liner of the gate structure on the surface of the substrate. The doping implantation step is, for example, performing a tilt ion implantation step to implant a dopant into the liner of the sidewall of the gate, and the implanted dopant is, for example, having a sidewall on the gate structure. The nature of the removal rate of the liner, which is, for example, nitrogen ions or inert gas ions. Then, a thinning step is performed to remove a portion of the liner. Wherein, the remaining liner has a thickness on the surface of the substrate that is greater than the thickness of the sidewall of the gate structure. Next, spacers are formed on both sides of the gate structure. Subsequently, an insulating layer is formed over the substrate, and the insulating layer is patterned to form a self-aligned contact opening between two adjacent gate structures in the memory cell region. Since the present invention first performs a tilt ion implantation step on the liner of the sidewall of the gate structure, so that the liner located on the sidewall of the gate structure is removed at a higher rate than the substrate surface during the subsequent thinning step. Liner

1284364 V. Description of invention (6)

The rate at which it was removed. The wider gap, in addition, is located on the surface of the substrate to avoid the problem of injury during the gate contact window process. Therefore, it is possible to have a process window for increasing subsequent etching or deposition between adjacent two gate structures. After the thinning step is performed, the thickness of the untreated liner is thicker, so that the spacers can be formed on both sides of the structure and subsequently self-aligned, and the surface of the substrate is damaged by the etching process. The loss of the method of the present invention can avoid the surface of the substrate (doped region), which can prevent the leakage of the junction. In addition, the manufacturing method of the present invention can further simplify the process steps without additional steps, so that the above and other objects, features and advantages of the present invention can be made clearer. The following is a detailed description of the preferred embodiment, and is described in detail with reference to the accompanying drawings: Embodiments 2A to 2G show a preferred embodiment of the present invention. A cross-sectional view of a manufacturing process of a contact window opening. Referring to FIG. 2A, a substrate 20 is first provided, and a plurality of gate structures 21 2 are formed on the substrate 2 , and a top portion of the gate structure 2 1 2 is also formed. There is a cap layer 210. The substrate 200 can be divided into a memory cell region 2〇2 and a peripheral circuit region 2 0 3 . The memory cell region 2 0 2 is a pattern dense region, that is, adjacent two gate structures 2 The gap between 1 and 2 is small, and the peripheral circuit area 2 〇3 is a pattern loose area, that is, the gap between adjacent two gate structures 2 1 2 is larger. In addition, the gate structure 21 2 is a gate Dielectric layer 2〇4, polysilicon layer 206

1284364

And a metal lithium layer 208. Wherein, the gate junction step is, for example, first depositing a layer on the substrate 200 to form a polycrystalline layer (not shown), a layer of metal (not shown), and a layer of nitrogen (not green). After that, the nitride layer is deuterated by a lithography to form the cap layer 210. Subsequently, the top cover d = the curtain is patterned into the dendrite layer and the polycrystalline layer to form the interrogation structure 212. Here, during the etching process for defining the gate structure 212, the thickness of the gate dielectric layer 2〇4 on the surface of the substrate 200 may be removed, and the thickness of the gate dielectric layer 204 is thin. & Next, referring to FIG. 2B, a portion of the thickness of the sidewall of the portion of the metal silicide layer 208 of the gate structure 2丨2 is removed to form a metal halide layer 208a having a recess. Among them, the method of removing a part of the metal telluride layer 2〇8 is, for example, an etching process using RCA1 money etching solution. Since the top cover layer is partially etched at the sidewalls of the exposed metallization layer 2〇8, a metal halide layer 2〇8a having a recess is formed. In addition, the purpose of performing the above etching process is that the metal telluride layer 208 is likely to cause side protrusions due to the growth of the crystal grains in the subsequent thermal process, and the metal bump layer 20 8 which is convex on the side may cause non-fat. The expected short circuit phenomenon, so the partial etching of the sidewall portion of the metal telluride layer 208 in advance can prevent the above problem from occurring. Then, referring to FIG. 2C, a liner layer 214 is formed on the sidewall of the gate structure 21 2 and the substrate 200 not covered by the gate structure 212. The material of this lining 214 is, for example, yttrium oxide. Wherein, the formation method of the lining layer 2 14 is, for example,

11676twf.ptd Page 13 1284364 Hotline process. This thermal process is, for example, a Rapid Thermal Anneal (RTA) followed by a Rapid Thermal Oxide (RT0) to form a liner 214. Moreover, in the overheating of the thermal process, the conductive layer 208a may be laterally convex due to the growth of the crystal grains, and the originally recessed portion may be filled. Thereafter, please refer to FIG. 2D to form a patterned mask layer 216 ′ on the substrate 2 以 to expose at least the lining 2 1 4 between the gate structures 21 2 in the memory cell region 2 , 2, wherein The material of the mask layer 2 16 is, for example, a photoresist material. Next, the lining layer 214 is subjected to a dopant implantation step 213 to have a different etch of the lining 21 4a on the surface of the substrate 20 0 and the lining 2 1 4 a on the sidewall of the gate structure 212. Selectivity. It is, for example, such that the removal speed of the liner 2 1 4 a located on the side wall of the gate structure 2 1 2 in the memory cell region 2 大于 2 is greater than the removal speed of the liner layer 21 4a on the surface of the substrate 200. The dopant implantation step 213 is, for example, performing a tilt ion implantation step to implant the dopant 2 1 4 on the sidewall of the gate structure 2 1 2 not covered by the mask layer 2 16 . Since the doping implantation step 2丨3 is performed only on the sidewall surface of the gate structure 2丨2, the tilt angle of the oblique ion implantation step is controlled so that the dopant is implanted only in the gate. The lining 2 1 4 of the side wall of the structure 21 2 . In other words, if the gap width between the gate structures 212 is X and the height is γ, the tilt angle 0 of the oblique ion implantation step is “^ 0 = χ / γ, and the tilt angle 0 of the oblique ion implantation step is, for example, Between 丨〇 and 3 。. And 'the doping system implanted in this oblique ion implantation step has the property of speeding up the removal rate of the lining 2 1 4 a located on the sidewall of the gate structure 212 , so that the liner 2 1 4a at that point in the subsequent thinning step, the speed of removal

1284364

The rate will be greater than the non-doped lining 2Ha of the surface of the base 2GG, and the subsequent thinning step 斟% female B is therefore the lining 214a of the side of the gate structure with the dopant implanted 2 1 2 In the case of a substrate that has no dopant implanted, the surface of the substrate is implanted with a nitrogen ion or an inert gas ion, and the inert gas ion is, for example, a nitrogen ion _ Ji Ο ^ In a preferred embodiment, the lining layer 2 1 4 may be directly implanted into the step 2 丨 3 without covering the mask layer 2 16 . Wherein, the implantation step 213 is a tilt ion implantation step, and the oblique ion implantation step is inclined between 15 and 35 degrees without the mask layer 21?.彳戈疋" Next, please refer to Figure 2E for the thinning step to remove the partial lining, 214a. Here, the purpose of thinning the underlayer 214 & in the memory cell region 2 is to increase the width (opening) of the space and reduce the aspect ratio thereof to increase the process window for subsequent etching or deposition. The liner 214b remaining after the thinning step has a thickness on the sidewall of the gate structure 21 2 that is less than the thickness on the surface of the substrate 2. In addition, the thinning step is, for example, performing a wet etching process, and the etching solution used in the wet etching process is, for example, buffered hydrofluoric acid (Buf f er hf, BHF) or diluted hydrofluoric acid (Diluted HF, DHF). In addition, it is worth mentioning that since the lining 214 of the sidewall of the gate structure 21 2 is implanted before the thinning step, the doping of the accelerated rate can be implanted, so that when the thinning step is performed, there is a planting The lining layer 21 4a of the doped gate structure 2 1 2 will have a removal rate greater than that of the unimplanted dopant substrate 2 〇 ()

1284364

The layer of the surface is 2 1 4a. In other words, if the underlayer 2 1 4a ' is thinned by wet etching, the etchant (for example, buffered hydrofluoric acid or diluted hydrofluoric acid) used for the sidewall 2 1 of the gate structure 2 1 2 is used. 4b has a faster removal rate. Therefore, since the thickness on the surface of the substrate 2 is larger than the thickness of the sidewall of the gate structure 212, it is possible to avoid subsequent formation of the spacer and the process of opening the contact opening. 2〇〇 The surface is bare and even damaged. Thereafter, referring to FIG. 2F, after the mask layer 216 is removed, a spacer 218 is formed on the sidewalls of the gate structure 212 and the cap layer 210. The method for forming the spacers 218 is formed, for example, by forming a ruthenium layer (not shown) on the structure formed above, and then performing an anisotropic etching process to remove a portion of the tantalum nitride layer. . Moreover, the etching of the spacers 218 also removes portions of the liner 2 1 4b. Referring to Fig. 2G, an insulating layer 22 is deposited over the substrate 200. The material of the insulating layer 220 in the basin is, for example, a yttria insulating layer. Thereafter, the insulating layer 220 is patterned to form a corresponding self-aligned contact window opening 22/bottom 200 surface between the adjacent two gates of the memory cell region 202. The basic value of the substorm and the violent road is that ^ 丨 犯 △ △ △ 以 以 以 以 以 以 9 9 9 9 9 9 9 9 9 9 9 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 214 In the process of the quasi-contact window opening 222, the surface of the substrate 2 in which you are & is not damaged and the damage is located in the cell 5 (4) 2 and then the metal material (not shown) is filled in the opening 222 to shape

1284364 V. INSTRUCTION DESCRIPTION (Η) A contact window is formed to electrically connect a doped region in the substrate 200 to a subsequently formed bit line. Since the present invention first performs a processing step on the liner of the sidewall of the gate structure so that the subsequent layer on the sidewall of the gate structure is removed at a rate greater than that of the liner on the surface of the substrate. The rate at which the layer is removed. Therefore, it is possible to have a wider gap between adjacent two gate structures to increase the process window for subsequent etching or deposition. In addition, since the thickness of the unremoved lining on the surface of the substrate is thick after the thinning step by the method of the present invention, the moiré can continue to form a spacer on both sides of the gate structure and is in progress. When the self-alignment is self-aligned, the surface of the substrate is damaged by the etching process to cause damage. In the method of the present invention, the surface of the substrate (doped region) can be avoided, so that the leakage of the junction can be prevented. The invention of the gentleman soil, Bo 1 ^ ^ is outside, the mining step I can also do not need to carry out additional ion implantation of cattle, although this can simplify the process steps.限定本== As above, but it is not within the scope of the invention, and may be attached to the scope of the invention: the special μ M ^ / room decoration, so the protection of the invention is defined by the patent Prevail.

1284364 BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1F are schematic cross-sectional views showing a manufacturing process of a contact opening in a memory element. 2A through 2G are cross-sectional views showing the manufacturing process of the contact opening of the contact window in accordance with a preferred embodiment of the present invention. [The figure is not specified] 1 0 0, 2 0 0 : Base 1 0 2, 2 0 2 · Memory cell 103, 2 0 3 : Peripheral circuit area 1 0 4, 2 0 4 : Gate dielectric layer I 0 6, 2 0 6 : polycrystalline germanium layer 108, 108a, 208, 208a: metal germanide layer II 0, 2 1 0 : cap layer 1 1 2, 2 1 2: gate structure 1 1 4, 11 4 a : Lining oxide layer I 1 6 : photoresist layer II 7 : damage 11 8 , 2 1 8 : spacer 1 2 0, 2 2 0 : insulating layer 1 2 2, 2 2 2 : contact window opening 2 1 3 : dopant Implantation steps 214, 214a, 214b: liner 216: mask layer X: width Y: height

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Claims (1)

1284364 Patent application scope 1 1. A method for manufacturing a contact opening, comprising: providing a substrate, wherein a plurality of gate structures are formed on the substrate; forming a sidewall on a sidewall of the gate structure and the surface of the substrate a liner on the sidewall of the gate structures, the dopant being implanted such that the liner of the sidewalls of the interposer has a different etching selectivity than the liner on the surface of the substrate a thinning step to remove a portion of the liner, wherein the liner is left to have a thickness on the surface of the substrate that is greater than the thickness of the sidewalls of the gate structures; Forming a spacer on a sidewall of the gate structure; forming an insulating layer on the substrate to cover the gate structures; and patterning the insulating layer to form a gap between the adjacent ones of the gate structures Align the contact window opening yourself. 2. The method of fabricating a contact opening as described in claim 1, wherein the method of implanting the dopant on the sidewall of the gate structure comprises performing a tilt ion implantation step. 3. The method of manufacturing a contact opening as described in claim 2, wherein the oblique ion implantation step has an inclination angle of between 15 and 35 degrees. 4. The method of manufacturing a contact opening as described in claim 1, wherein the quality change has the property of accelerating the removal rate of the underlayer located on the sidewalls of the gate structures. 5. The method of manufacturing a contact opening according to claim 4, wherein the dopant comprises one of a nitrogen ion and an inert gas ion. 1284364 6. The method of manufacturing a contact opening according to claim 5, wherein the inert gas ion comprises a gas ion. The manufacturing method of the contact window opening according to the first aspect of the application of the first aspect of the invention is as follows: after the lining is formed, and the layer of the sidewalls of the gate structures is implanted & . ^ / , is further involved in forming a pattern on the substrate, the mask layer at least exposes the liner between the gate structures. 8) The method for implanting the dopant in the lining of the sidewall of the gate structure according to the method of the seventh aspect of the invention is to perform a tilt ion implantation step. . 9. The manufacturer of the contact opening as described in claim 8 of the patent application / 'where the inclination angle of the inclined ion implantation step is between 1 〇 and 3 I I, ^ & such as /, please The manufacturing method of the contact opening of the seventh aspect is formed; the step: after the step of thinning and before the step of forming the interstitial gap i on the sidewall of the gate structure, further comprising removing the mask layer . 11 . A method of manufacturing a contact opening, comprising: providing a memory cell and a peripheral circuit region, wherein a plurality of gate structures have been formed on the substrate; and a sidewall of the gate structure and the substrate The liner is subjected to a lining layer on the surface of the dopant implantation step and the liner on the sidewalls of the interpolar structures; ε = etching selectivity; / 锹 layer has a thinning Step, the layer is located on the surface of the substrate = the portion of the liner is removed, wherein the thickness of the layer is greater than the thickness of the gate structure 6. The thickness of the sidewall of the patent application area is formed; /aj is formed on the sidewall of the gate structure to form an insulating layer covering the gate structure, and patterning the insulating layer to be in the memory cell region Adjacent to the complex as well. A self-aligned contact window is formed between the gate structures of the sea. 1 2. The smear of the contact window opening as described in claim 11 of the patent application. The method wherein the dopant implantation step comprises performing a tilt ion implantation step to implant a dopant into the liner of the sidewalls of the gate structures. 1 3 . The method of manufacturing a contact opening as described in claim 2, wherein the inclined ion implantation step has an inclination angle of between 丨5 and 35 degrees. A method of fabricating a contact opening as described in claim 12 wherein the dopant has the property of accelerating the removal rate of the liner on the sidewalls of the gate structures. The method of manufacturing a contact opening according to claim 14, wherein the dopant comprises a nitrogen ion and an inert gas ion, wherein the contact is as described in item 15 of the patent application. A method of manufacturing a window opening wherein the inert gas ion comprises argon ions. The method of manufacturing a contact opening as described in claim 1 wherein the patterning is performed on the substrate after forming the liner and before performing the dopant implantation step on the liner. A mask layer is formed to at least blast the layer between the gate structures in the memory cell region. 1 8 · Manufacture of contact opening as described in item 7 of the patent application 11676 twf.ptd page 22 1284364 6. Patent application method, wherein the dopant implantation step comprises performing the oblique ion implantation step to implant the dopant on the liner of the sidewalls of the gate structures. A method of manufacturing a contact opening as described in claim 18, wherein the oblique ion implantation step has an inclination angle of between 1 Torr and 30 °. The method of manufacturing a contact opening according to claim 17, wherein the removing the cover is performed after the thinning step and before forming the spacer on sidewalls of the gate structures. Curtain layer. 11676twf.ptd Page 23