TWI284323B - Method and circuit for reading fuse calls in a nonvolatile memory during power-up - Google Patents

Abstract

A method and circuit are described for ensuring a properly operational power-up read of fuse cells in a nonvolatile memory by selecting predefined data for loading in a portion of a fuse memory and matching the reading of the predefined data during power-up with the predefined data, thereby indicating a proper power-up read of fuse cells. The fuse memory is partitioned into a first section of fuse cells for conducting a pre-check procedure to match a first predefined data being read against the first predefined data, a second section for reading main fuse cells to match with a second predefined data being read against the second predefined data, and a third section of fuse cells for conducting a post-check procedure to match a third predefined data being read against the third predefined data.

Description

1284323

" Sanda number: TW2295PA # IX. Description of the invention: [Technical field of the invention] The present invention relates to a non-volatile memory volume circuit, and in particular to a suitable data download at the time of power-on.

[Prior Art] ~3 The technology for electronically programmable and erasable non-volatile memory is based on the charge storage structure, as we know electronically erasable private read-only memory ( EEPR0M) and flash memory (memory) #Used today is a versatile application. The array of the body elements of the Hans in the flash memory can be independently programmed and read. The flashing 'Sense amplifiers' are made = the data value or the stored value in the 2-bit memory. In the traditional :::: and 曰: the current through the sensed memory component by the sense of current

1 Refer to the current (refererice current) to be more widely used i ° own L, body 疋 - an electronic storage medium, its memory components can be repeatedly written and remember storage capacity. This type of heart = the content of the piece can also maintain the life without power. In the dynamic random ^ memory with slit ~ New write period, an erased bit memory or static random access memory flash memory is erased and ^ Wei relative to single - or complex bits The meta-program memory (ΕΡ_)_#. Flash memory combines erasable and readable memory (ΕΕΡ_) in /+ features and electronic erasable programmable traditional flash c unremovable. Design of a floating interpolar transistor in a k-body element, 6 1284323

" Sanda number: TW2295PA / Each floating gate transistor has a source, a pole, a floating interlayer and a control idle layer. An access operation is applied as a bias signal applied to each region of the floating gate transistor. To implement a write operation, there is usually a floating electronic sin channel hot channel (channel hot~carrier) between the source and the drain, so that it can quickly move toward the Xiao floating gate and accelerate the application in the positive direction of the control gate. Biased reaction. The general erase operation type is the use of the 遂 current in the drain region > the 遂 current generated under the negative voltage of the galvanic electrons (F〇Wler N〇rdheim). The general sensing step of the read operation includes the current between the source and the > and the metal oxide semiconductor field effect transistor (MOSFET) current is applied to the bias applied to the control gate. If the memory component has been programmed, its initial voltage will be close to or exceed the bias of the control gate, which will cause the current to be low. If the memory component is erasable, the initial voltage will be lower than the bias voltage of the control gate, so that when the source is activated, the voltage generated from the power supply will change. The configuration data on the system is == scratchpad to set the configuration of this system. However, the start: the change of the wheel pressure will make the data generated during the reading have been properly stored in the register, a traditional verification result, and the memory component is supplied from the non-swept configuration data. The value that has been appropriate will be greater than the supply voltage value, especially at ^(5) voltage. This high-power device, and the circuit produces a larger than the supply: the special low-voltage start-up power charge report may occur - a large = electric repeatedly, like in, see nuclear and unstable electricity 7 1284323

w Sanda number: TW2295PA, source difference. Another conventional result is the use of a 3 volt device to detect the energy gap reference level and establish a preset read voltage. However, the prerequisite is that the energy gap reference level needs to be established when the power supply is restarted. However, there is a lot of interference in the voltage when the power is turned on, which will cause the configuration data to be loaded incorrectly. It is also difficult to apply this conclusion in low voltage products. For example, on a 1.8 volt product, the lower limit when restarting the power supply may be set to 1 volt, and it is currently difficult to design a zero-gap reference level at this voltage level. Therefore, it is necessary to provide a circuit and a method for accurately reading the configuration data when starting the power supply to the non-volatile memory, and includes a low-voltage flash memory. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a method and circuit for ensuring that a suitable electrical φ source of a fuse element of a volatile memory initiates a read operation and downloads to a fuse memory in accordance with the selection. The preset data of a part of the body is compared with the preset data read at the time of power-on, so a fuse element suitable for starting the reading of the power source is determined. The fuse memory can be designed as one side of the memory array for sharing the read circuit and the write circuit, or the memory array itself has a read circuit and a write circuit, and the fuse memory Separately disposed, and the fuse memory is divided into a first region of the fuse element for guiding the first preset data read in the pre-detection program to compare the first preset data from the main fuse element The second preset data read in the second area is compared with the second preset resource 1284323, and the third area of the fuse element is used to guide the third preset data read in the post-detection program. The third preset data. The first area of the fuse element of the fuse memory is written to the first set preset data to the pre-detection private sequence. The second region of the solvolysis element of the solvolysis memory is written to the preset data of the second device including the configuration data. The third area of the fuse element of the solvolysis memory is written to the third set of preset data for the post-test procedure. A method for ensuring an appropriate voltage to pass through a fuse element of a fuse memory having a pre-detected fuse element memory area during a power-on read operation of the non-volatile memory, Main fuse element memory area and post-detect fuse element memory area. The method includes: reading data from the memory area of the first fuse element to perform a pre-detection action to determine whether the read data of the memory area of the first fuse element meets the first preset resource, and the memory area of the main fuse element is read. Information to determine the main fuse element data. = whether the read data of the memory area meets the second preset data; and, after reading the data from the memory area of the dissolution line component to perform the post-detection, it is judged whether the read data of the memory area of the third bright line component is met. Third preset, in addition,

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。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Please refer to FIG. 1 , which is a schematic diagram of reading a fuse element when a non-volatile memory is activated at a power source according to a first embodiment of the present invention. The memory array 110 includes a matrix of a plurality of memory elements, which are arranged in a horizontal direction, called a word line, and a vertical direction, which is called a bit line. When the executives take the fetch operation, the buffer address 120 receives an input address 2 and passes the column address to the column decoder (r〇w decorder) 13 and the row address to the row decoder. (column decoder) 140, the read circuit ι5 此 so far enough to read the data is obtained by the column decoder through the decoder 140 to analyze the obtained address. The read circuit is located between and coupled to the write circuit 152 and the pass gate 154. Some memory components that conform to the body array, such as electronic erasable and configurable N0R flash memory components, mask read-only memory (masked hair or ferroelectric s memory components) (ferroelectric memory cel Is), /, sentence is electronically programmable memory. Hyun, line το has been used in flash memory, and use flash memory to store on the Dexter line - Aberdeen The configuration data of the trimming parameters of the circuit. The configuration data in the fuser is generally used for boot-up - the advantage of remembering the memory is that there is no need to add extra Another use of line components is as component redundancy (device 1284323

The three-digit number: TW2295PA' and these redundant components are like the fyce(1) or line memory component can be used to replace the defective memory column or row in the memory. If a missing or defective memory line is found in the test, the defective memory column or defect ^ = address will be stored in the (10) line component. The storage component of the secret line component is different from the different specifications of the different products (enable bit) 〇

When the power is turned on, the configuration data is accessed from the memory device by the downloader or the static random access memory. The static m state = access § memory is read at a very fast speed, but must be - a lower operating power supply. Volatile memory such as dynamic random access memory or static random access memory is also considered a scratchpad in terms of specifications. The configuration data is instantly downloaded to the scratchpad when the power is turned on, and the configuration data can be directly evaluated after startup. When the non-volatile memory 100 is tested, the configuration data is written to the fuse line component of the fuse #memory 170. Some examples of configuration data include circuit corrections, selective data for different rules, redundant data, and special parameters for other wire tests. When the power is turned on, the data in the fuse memory 17〇 will be fetched and written to the set register or latch boundary (iatCh) 18G. Operation (4) Initiating the reading (4) circuit 19 (^ is established on the reading data provided by the solution line. Referring to FIG. 2, the non-volatile memory according to the second embodiment of the present invention is activated at the time of power-on. A simplified architectural diagram of the read-wrap component. In this embodiment, the solvolysis memory 210 is not part of the memory array, 11 1284323

A three-digit number: TW2295PA' is disposed separately from the memory array, and the fuse marker 170 different from that shown in FIG. 1 is used to share the read circuit 15A and the write circuit 152, and the line memory 210 itself That is, a set of read and write circuits is provided, and the fuse memory 210 is lightly connected to the read circuit 220 and the write circuit 230. The non-volatile memory 200 provides an elastically set reference value on the fuse element of the fuse memory 210. The non-volatile memory 200 does not require a large load memory array and a fuse element of the fuse memory 210 of the read-and-hold operation as compared with the non-volatile memory 100 of the first embodiment. In addition, the scratchpad is further connected to a single or multiple configuration circuits 240. Non-green is non-volatile memory 1 或 or non-volatile memory 200 is suitable for low-voltage flash memory, such as 1 · 8 volt flash memory. Referring to Figure 3, there is shown a schematic diagram of a register for resetting non-volatile memory in a reset circuit in accordance with the first and second embodiments of the present invention. The power-on reset circuit 300 includes a gate 311, a drain 312, and a source 313 of an enhanced p-type metal oxide semiconductor (PMOS) field effect transistor ❿ 310. The gate 312 of the PM0S transistor 31 is connected to the series resistor 320 and then grounded (GND) 33 〇. The gate 311 of the PM0S transistor 310 is connected to the ground terminal 340. The source 313 of the pm〇s transistor 310 is connected to the power supply terminal (Vdd) 350. This resistance value is selected in accordance with the specifications of the power-on reset circuit 3〇〇. The capacitor 36 is connected from the DC voltage (Vdd) of the power supply to the PM 〇s transistor 31; and between the poles 312. Two serial inverters (invei^er) are a first inverter 370, a second inverter 371 and a third inverter 372, respectively, and are coupled to the drain 312 of the pM〇s transistor 310. Connected to receive signals. First reverse 12 1284323 Sanda number: TW2295PA The trigger point on 370 (triggeHng pQint) is set according to the voltage detected by open circuit 300. The second inverter 371 and the third inverter 372 are used as buffers for the driver of the output P〇R signal. This input POR signal 380 will reset all the temporary crying on the integrated circuit. When the voltage reaches the preset value, the output signal 38 is not enabled for the group operation of the integrated circuit, for example, downloading data from the fuse element to the temporary memory. Therefore, the power-on reset circuit 3 (10) effectively provides a single-two stable circuit. An application suitable for this power-on reset circuit is to supply power to a 1.6 volt operation. FIG. 4 is a schematic diagram showing a clock circuit used as a power-on reset read in accordance with an embodiment of the present invention. The first set of inverters 410 411 412 and 413 operate, such as a ring oscillator, to generate an alpha kine signal 42. The second set of inverted 430 431, 432, and 433 positions are prior to connecting the first set of set inverters 410, 411, 412, and 413, and operate as a buffer to produce the Lusheng CLK A number 420. A plurality of n-type metal oxide semiconductor (nm〇S) field effect transistors 440, 44, 442, 443 and 444 can be combined as a capacitor, and the capacitance value is determined by the size of the inverter. And the frequency of the oscillator is determined. Additional PMOS transistors 450, 451 and NM 〇s transistors 452, 453 are used as enable control circuits for CLK signal 420. As shown in Figure 3, the vibrator is automatically enabled when the P0R signal 380 is maintained at a low level. The clock circuit 400 is designed to operate even if the power supply provides a lower voltage, even only 1 volt. When the clock circuit 400 used as the power-on read is started, the CLK signal 420 will be turned on. 13 1284323

i reaches the number: TW2295PA activated (activated). After the current circuit is completed, the CLK signal 420 is disabled. Referring to Fig. 5, there is shown a fuse block diagram of a fuse memory structure having a fuse element structure used in the fuse memory 170 of the first embodiment or the fuse memory 210 of the second embodiment. The fuse element 5 (10) has three fuse elements. The file consists of pre-detection () memory 510 " and 520 and post-check memory 530 in the heart data. The pre-detection memory 51〇 and the post-detection memory 53〇 are placed on the fuse. The worst read path in 500, the purpose of which is to read the fuse element t to raise the worst h condition. This worst case condition is generally located at the top and bottom addresses of fuse line = body !00. When the pre-detected memory is successfully/supplied and the detected memory 530 successfully performs the read action: 1, 丨 will provide this, and take the worst case condition of the action. Therefore, if this pre-existing double-recovery body 510 and Deyu, witness j, refining line memory H 500, == body 530, the positive handle is read before. The fuse element of the τ/, 匕 position should also be correctly read. Referring to Figure 6, the pot device - ^ /, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The reading process 600 of the θ of each of the θ lines is performed. 2 In the example of the execution of the power-on reading step 610: Γ the preset data is downloaded to the memory 510 to perform the pre-detection. After being downloaded to the configuration data content 52〇, the third preset bellows is downloaded to the memory 530. ρ气妩话玩+ οη The detection action is performed after the light is executed. At step 610, the power-on reset circuit 300 generates ρ&^1ΠΠ, οππ, apostrophe 380 to reset the scratchpad of the non-volatile memory 100 or 200. Recognize + m after the power-on reset operation is completed, 14 1284323

Sanda number: TW2295PA t, process 6gg enable, start read operation. In the step wheel, this process is the clock that enables the power-starting action. In step 骅, the pre-detection program is turned off and the read _ input material is matched. If it does not match, this process: . ; [, brother - default capital Λ田冷王bt) 0 back to step 640. If the younger - the default (four) with this Wei _. In step 650, the process _ the order to enter the next step and read the main refining "to determine the content of === to the temporary material. If not, this product:,,: whether or not The second preset capital is consistent, and the process _ is carried out after the next younger one of the default lean process is tested. The third preset data is consistent with the third preset data. If you don’t kiss people, δ draws the feed. Whether or not with step 640. In the case of an anastomosis, if; new: the final address of the pre-detection program in the fuse memory 500 is from the flow _ complete power-on read operation (four) step 670 'Action' and non-enable power start reading action ^ Power start 5 buy the ▲ mouth η μ - ^ clock, in order to save the thunder. 言月参π弟7 diagram, it is not in accordance with the invention - The block diagram of the memory structure. The complex data of the fuse line fuse includes the non-volatile memory 2 = ^ ^ detection preset data and configuration data. Two phases _ and Ν are to be used Pre-test procedure or post-test procedure. The part of -, (words) AAAA16 and the second preset data is 5 = The part of the shell material is the character (4) on the hard-to-finish order. 16' These two strokes are preset. ΛΑΑΑ16 and 555516 are hexadecimal 1284323

'Sanda number: TW2295PA ^ The unique method of the bit method, and also has a binary value that is unique to the binary representation. The carry value of A A A A16 is a series of "10"s with a value of "1010101010101010". The 255516 bis carry value is a series of consecutive "01" whose value is "010101010101010Γ. To some extent, the data formats of AAAA16 and 555516 have been used because the two forms of data provide a wide range of error. It is understood by the skilled person that the present invention can also use other forms of data that ensure proper power-on reading, and does not violate the spirit of the invention. The address line is the address 0, and the data written on the dissolution element memory structure 700 is AAAA16 (1010101010101010). The second address line is the address 1, which is smashed on the fuse element Luiji recall structure 700. The incoming tribute is 5 5 5 516 (0101010101010101). When the first two data read from address 0 and address 1 match the first preset data, the power supply is ready to execute a melting The line component is read. In the correct reading, the first data is read from address 0 equal to AAAA16 (1010101010101010) and the second data is read from address 1 equal to 555516 (0101010101010101). However, if the first The data read by the pen is not the same as AAAA16, the result of the second data reading will not be 555516. Because the delay of the first reading data and the second data is only one cycle of counting cycles. So there will be insufficient time to reverse, let each bit from 1010101010101010 to 01010101011010 in the post-testing procedure 'the last two sites of the tribute form in the refining line memory 16 1284323

'Sanda number: TW2295PA ^ Body structure 700 is AAAA16 and 555516. The data written to the η-1 address on the fuse memory structure 700 is aaaa16 (1010101010101010). The data written to the η address on the fuse memory structure is 555516 (〇ΐ〇ι〇ι〇ι〇ι〇ι〇ι〇ι). When the two data of the last stroke read from the η-1 address and the η address coincide with the third preset data, the power supply is ready to perform a fuse element reading. When reading correctly, the η-! pen data read from the address η-1 is ΑΑΑΑ16 φ (1010101010101010) and the n-th data read from the address η is 555516 (〇1〇1〇1) 〇1〇1〇101〇1). However, if the result of the first data read is not AAAA16, the result of the nth data read may not be 555516 when correctly read. Because the n-1 pen reads the data and the nth pen. The delay of the data is only one cycle of the number of cycles, so there will be insufficient time to reverse, so that each bit is from 1〇1〇1〇1〇1〇1〇1〇1〇 to 0101010101010101. In the first and last addresses, the worst case condition is to read 0 spring or 1. The correct reading of the first and last addresses is correct in protecting the other addresses. In the configuration data content area 71, DQ0 indicates whether the character data is odd or even in the verification bit DQ15-0 of each column. The power supply initiates a floating process of read detection, and the read result matches the preset. This test is executed on every read character and will be more suitable for noisy power-up situations. In addition, redundant data can be entered in different locations in the content area of the configuration data. Referring to Figure 8, there is shown a schematic diagram of a memory structure of a fuse element in accordance with a second embodiment of the present invention. Each of the high and low bytes 17 1284323

• The three-digit number: TW2295PA, the bit is the same in the configuration data content area 810. The high byte Dqi5-8 is 7-bit wide and the low byte DQ7-0 is also 7-bit wide. The fuse element memory structure 8 (10) provides more redundant data areas in this embodiment. The dummy cell area of the fuse memory and the peripheral circuits generally occupy a larger area than the line components. As described above, the present invention has been described by way of example only, and the invention may be modified, modified and changed without departing from the spirit and scope of the invention. For example, although the present invention displays the position of the fuse element as shown in FIGS. 1 and 2 in the above two yoke examples,

The fuse element of the Ming can also be placed in other locations or combined with other electrical X-paths. In addition, although in the first embodiment, the first, second, and third preset materials are selected before the generation of the p〇R signal, the familiar artisan can

Obviously, the preset data can also be defined using other methods or in a different order. In the above, the present invention has been described above in a preferred embodiment, and is not intended to limit the invention, and it is to be understood by those skilled in the art without departing from the spirit and scope of the invention. Various modifications and refinements can be made, so the scope of protection provided by the appended claims is 18 1284323 - number, TW2295PA [Simple Description of the Drawings] Figure 1 shows the first implementation in accordance with the present invention. A simplified architectural diagram of a non-volatile memory reading a fuse element while moving. Fig. 2 is a simplified block diagram showing the reading of the fuse element at the time of startup of the non-volatile memory in accordance with the second preferred embodiment of the present invention. FIG. 3 is a schematic diagram of a power-on reset circuit for resetting the temporary memory of the non-volatile memory of the first and second embodiments in accordance with the present invention. Fig. 4 is a schematic diagram showing a clock circuit used as a power-on reset read in the embodiment of the present invention. , =5 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图The younger brother of the 7th figure shows the block diagram of the structure of the dream and the structure of the memory. In the case of the "a" example of the secret element of the invention, the figure 8 of the present invention will be shown in a block diagram of the structure of the structure.溶 溶 溶 溶 主要 主要 主要 主要 主要 主要 主要 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100

Sanda number: TW2295PA 150, 220: read circuit 152, 230: write circuit 154: Y transfer gate 170, 210 · fuse element 180: register 190: power start read control circuit 240: configuration circuit 300: power-on reset circuit 400: clock circuit 500: fuse memory 510: pre-detect memory 520: configuration data content 530: post-detection memory 700, 800: fuse element memory structure 710, 810: group Data content area

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Claims (1)

Ϊ284323 : TW2295PA ' X. Patent application scope: 1. A method for ensuring the proper voltage to pass through the line (10) se Ce(1) in the power-up reading process of non-volatile memory, the memory of the miscellaneous line has ; (Pre_check) fuse element memory area, a main fuse element record area, and a post-check (Post_check) fuse element record area. The method includes: ~, from a first fuse element memory area Reading data to perform a pre-test 2 as 'to determine whether the read data of the memory area of the first-hyun line component meets a first preset data; and - reading the data in the memory area of the main fuse element to judge Whether the read data of the 7L piece of the memory area of the main material line conforms to a second preset resource, the third fuse element, and the memory area read data to execute a </ </ RTI> to determine whether the third lining element memory area is a combination of the third preset data. Bessie detects the first address and the second address of one of the pre-line memory areas by the method described in the item 1. 'The line component memory L or the second preset (10) manned to the main fuse detection 2 for the method described in item 3, and the execution of the pre-month 1j further includes loading the third preset data To the third melt 21 1284323 - up to the pain: TW2295PA line C remembers one of the next address and a last address. The method of detecting L, such as the method of claim 1, is to generate a restart signal during the execution of the pre-, 乍, month. The new method of the item "after the generation of the weight" 11唬, further includes enabling a power source to initiate the reading action. The reading method: the method described in item 6 of the range, the action of the power source is activated. Further, the clock is started to start the reading operation of the power source. 8. The method described in claim 7 of the patent application further includes the clock of the non-power source starting read operation. The method described in the item, including the fuse line $, the selection-worst case condition data, the method of selecting - the piece - taking the 'selection', the carry in the memory area of the first pre-element The method is the method described in the m-th component memory area Jm5555 in the sixteen paste 1 package and the third item, and is used to detect the main bright line in the "memory memory = wide selection of a poor material setting value". The method described in the section, including the section m § and the shell material, includes the pre-selection-worst case condition data from any of the ray line memory strains of the lysate memory. In the purchase, please select the preset, please refer to the method of 2, in the second bracket. 1 - the character is like the six-touch method is the third - dazzle 22 1284323 Erda number: TW2295PA in one of the memory arrays side. Body, apply for the non-volatile memory of the 15th item. A reset circuit is consumed by the flash memory, and is reset to the temporary storage, and the scale is used in the reset circuit. . Body, material, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Songdian (4) is connected to the bribe line memory to start the power supply, and the Zhongyi 5 memory array includes a low voltage flash memory. twenty four