TWI282915B - Integrated circuit with power gating function - Google Patents

Abstract

The present invention relates to an integrated circuit with power gating function, which comprises a linear voltage regulator, a switch module, and an equalizer; wherein, the linear voltage regulator is coupled to a first power line to provide the power to the first power line; the switch module is connected between a second power line and a power source, and control the open/close based on a mode signal to determine if the power source is providing the power to the second power line; the equalizer is connected between the first power line and the second power line, and with the control through the mode signal to be operating with the switch module, so that when the mode signal makes the power source providing the power to the second power line, the voltages on the second power line and on the first power line are approximately equal.

Description

J282915 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit, and more particularly to an integrated circuit having an electrical and source gating function. [Prior Art] Since the mobile device (1) and the threshold voltage are reduced, it is expected to achieve light weight, low power consumption, and high speed. However, the drop in the threshold voltage leads to static energy. In the mode, the leakage current rises, thereby increasing the power consumption. The development of the integrated circuit with power gating is an attempt to solve the high power consumption problem in the static mode of the integrated circuit. _ Generally, the circuit can be divided into input/output circuits. (inpui/〇utputcircuit) and core circuit (:〇reClrcmt) 'Rainer includes current supply circuit, the latter includes logic reversed early 70 and small-sized storage unit composed of small size, primary threshold voltage, low operating voltage. When in the dynamic mode, a circuit is used for shore-shoes, heavy... The power supply in the integrated circuit should be used for the operation of the data, and when the data is stored in the static mode. The power supply, but when the 1C is in the packet source circuit, only the data is supplied: The circuit is turned off at this time, so the static power of the static dice can be reduced, and the logic saves more power, static energy. The power consumption of 槿彳/下, or in order to be able to operate the power supply required by the circuit, the circuit required for the logic operation unit storage unit is turned off at this time. -"Data storage There is no need to transport the brother in the unit. The figure shows a conventional power supply block diagram, including the first power supply, the line 100 is lightly coupled to the empty function, and the circuit of the circuit is 0697-A40439TWF. The data storage single magic G6 (such as the part of the circuit shown as h in the figure; the second power line 1〇2 is lightly combined with the inverter / D Flip-Flop) within the logic unit 1G4 # ° to the low critical power (four) One of the crystal compositions is Hanbei 枓 storage unit 1 〇 6 yuan 1 〇 8 coupled to the logic transport tube stay - part of the circuit; interface single % #早兀104 and data a traditional switch transistor 11 〇 钤仵 钤仵 106 106 106 And between the conventional switching transistor and the second power line (10) crystal 'and its gate coupled to the private voltage P Μ 0 S type electric ... loose signal "S1eePl 11? β must pay attention to, the data One of the storage units iq6, the power line 100, or the circuit such as R_ can be connected to the first As shown in the figure, it can be partially connected to the second power line 1Q2 read, line 100 and part of the outline. The source can be low turn, the body m is turned on, and the result is _!, should be the second power cord Receiving, the logic operation unit and the lean material storage circuit 106 are connected to the second power supply line and then part of the circuit operation. At the same time, the logic operation unit can just store its operation data through the interface unit 108 to the data storage unit 106. Conversely, when the integrated circuit is in the -static mode, the mode signal "Sleep ^ is high voltage, so the conventional switching transistor 11 is not turned on, and the power supply is not supplied from the first source line 1 to the second. The power line is 1〇2, so the logic unit

0697-A40439TWF 1282915 * 1 action; however, at this time, the first power line 100 still supplies power to the circuit connected to the data storage unit '106 for enabling the circuit to store the previous logic mode' The data received by circuit 104. Although the core circuit has been developed towards the use of low operating voltages, it is often necessary to externally connect circuits with high operating voltages. Therefore, the power supply circuit generally includes a line regulator to provide a high voltage level provided by an external high voltage source. Quasi-converted to the core. The low operating voltage level required for the circuit. Figure 2 is a block diagram showing a conventional integrated circuit with a power regulator function, including a linear regulator 200 coupled to the first power line 100 for providing The steady voltage is set to the first power line 100. Except for the addition of the linear regulator 200, the rest of the second figure is the same as in the first figure. FIG. 2 also shows a typical circuit structure of the linear regulator 200, including an operational amplifier 202, a reference voltage generator 204, which can provide a reference voltage that does not change with temperature, process, etc., and a resistor R1. A voltage dividing circuit composed of R2, and a first transistor 206 of a PMOS type connected to a voltage source Vcc (for example, 3.3V). The drain voltage of the first transistor 206 is the output voltage of the linear regulator 200, and the series resistors R1 and R2 divide the output voltage and feed it back to the operational amplifier 202 to output a reference voltage with the reference voltage generator 204. In comparison, the gate voltage and equivalent impedance of the first transistor 206 can be adjusted to stabilize the output voltage. However, this prior art has the following disadvantages. First, the performance of the core circuit and the correctness of the timing model are not satisfactory. This is because although the first power line 0697-A40439TWF 8 1282915 (10) and the linear viewer 2_ horse and the electric dust is stable, the second power line ι 2 is transmitted through the conventional switching transistor 11 to the first power supply, the line 1 〇〇 electric (4) Ma He, can not directly feedback its voltage to the linear device. When this results in the § mode, the second power line is removed from the power supply (4) except for the first power supply line (10), and it cannot be automatically compensated by the linear suspension to stabilize, so the core circuit performance and timing model The correctness is reduced. The second 'traditional germanium transistor (10) consumes a large amount of integrated circuit area. In order to reduce the difference between the electric power of the second power line 102 and the stable electric grind of the first power line _, the conventional switch electric power is used in the case where the conventional switching transistor 11G circulates the high current required for the second power line 1Q2. The crystal 11G is bound to be a large-sized transistor, which generally consumes a large circuit area of the magic, and the increase in size increases the leakage current. In the first disk of the first - Et, the flat from the RB η /, the division of the traditional switch transistor 110 size of the younger station has been a subject of consideration in the prior art. In order to minimize the leakage current of the integrated circuit in the static mode, the conventional switching transistor 110 must have a high remaining portion of the remaining transistors in the same process. The boundary voltage is often not compatible with the core circuit, and the process fusion technology is required and the cost is fourth. In the dynamic mode, the power efficiency is not satisfactory. Since the power supply needs to consume additional power through the transistor 206 and the squad, the power supply system in the dynamic mode is transmitted to the second power line 102. The switching transistor 11 is inferior. .

0697-A40439TWF 1282915 SUMMARY OF THE INVENTION In view of the above, the present invention provides an integrated circuit in which an integrated circuit can automatically operate on a first mode in a dynamic mode, which is stable. The present invention provides: leakage current to improve power, improve: and reduce the static core circuit to be manufactured in the same process. The power supply frequency, and the present invention provides an example of a power supply control circuit linear regulator coupled to the second limb circuit, including a 筮叩 coupling to the first power line, and a power cord, And using a modulo-type t-regulator coupled to the first number to control the dance to the brother-integrated circuit in the dynamic die-cutting action. When the power supply is supplied to the second power line; the type signal makes the second linear stability _ stop supplying power / traits - the mode of the model, and the power supply gate control circuit of the integrated circuit a power supply line, the switch module is connected to the second electric two: an electric power source is connected between the first power supply line and the second power supply line, wherein the switch module is connected The opening and closing with the equalizer is controlled by the _ mode signal. When the integrated circuit is in the dynamic mode, the mode signal causes the open mode module to open the Asian equalizer, and thus the power (4) supplies power to the second power line, and the same The voltage of the line is substantially equal to the voltage of the first power line, and when the integrated circuit is in the static mode, the mode signal causes the switch module to be opened, so that the voltage source cannot supply power to the second power line, and the equalizer also

0697-A40439TWF 10 1282915 No action. The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims [Embodiment] FIG. 3 is a circuit block diagram showing a first embodiment of an integrated circuit having a power gating function according to the present invention, including a first linear regulator 300 coupled to a first power line. 100, for providing power to a portion of the data storage unit 106 connected to the first power line; a second linear regulator 302 coupled to a second power line 102 for providing power to the logic unit 104 and A portion of the data storage circuit 106 that is connected to the second power line 102 is used. The first linear regulator 300 typically includes a reference voltage generator 204, an operational amplifier 306, a PMOS type transistor 312 coupled to a voltage source Vcc, and two resistors R11 and R12. Similarly, the second linear regulator 302 also includes an operational amplifier 308, a PM〇S type transistor 314 coupled to the voltage source Vcc, and resistors R21 and R22, and sharing the reference voltage with the first linear regulator 300. The generator 204 is controlled by the mode signal "Sleep" 112 to determine whether the second linear regulator 302 supplies power to the second power line 102. It should be noted that the circuits in the data storage unit 106 may all be connected to the first power line 100 or, as shown, may be partially connected to the first power line 100 and partially connected to the second power line 102, in fact The choice is based on design needs. 0697-A40439TWF 11 1282915 f 4 When the integrated circuit is imaginary~, when it is in a dynamic mode, the first linear #@ should stabilize the power supply to the first ~, '300 for power line 100, thus making the data storage In the 罝-, the first power line 100 is in phase with the <partial circuit action; at the same time, the mode (1) is _, so the nose amplifier 308 of the transistor 314 can operate normally and rotate The voltage is 卩_ to make it guide (4) the material effect group, so that the + voltage source Vcc can provide a stable voltage and the data storage power: the source to the second power line 102 for the logic operation unit. 106 is connected to a portion of the second power line 1% of the circuit. Conversely, when the product suspension 300 keeps the power supply in the static mode, the first linear regulator and the first power supply line 100: the first one The power line 100, and thus the data storage unit (10), the number "Sleep" 112 is ancient: some of the circuits can still operate; and the mode is "乂", "quote", so the operational amplifier 308 takes a turn The repulsion level is up to PMOS, and the gate of m & M is turned off, so that the rain os transistor 314 is cut off, and the voltage source vcc cannot be supplied to the second power line. 1 02, 4 士|兮, r 1 unit 104 and data storage ^ original line 〇 2,,,. If the logic operation circuit 106 is connected to the second power source, the circuit cannot operate. (4) The part of the force H line 106 is due to the dynamic mode. The voltage of the power line 1〇2 of the Chu-di is directly provided by the second line 302, and the middle of the u-t-state... and the additional conventional switching transistor u In the conventional technology, the second power port is not the difference between the voltage of the 02 soldier-power line 100. 1 71 The younger-wire power device 302 can automatically compensate the second power line 1〇2 to make it Stable, ^ ^ Large second power line 102 can provide logic unit

0697-A40439TWF 12 1282915 1〇4 and the data storage circuit 1〇6 is connected to the voltage of part of the circuit of the second power line 1〇6. In summary, the first embodiment of the integrated circuit with power gating function provided in Fig. 3 of the present invention provides advantages over the prior art: the core circuit has no problems such as % accuracy or cell performance degradation. + The poorly provided figure 3 provides the "first method of the road to provide other advantages over the prior art. · · -, when the static mode is directly cut off and the electricity source ν" The connected transistor 314, and thus the leakage motor is reduced by _>, the power consumption is also reduced. Second, the size of the circuit is reduced without the required area of the conventional switching transistor (10). For this point, please refer back to Figure 1, although the iron 2 shell example I brother 1 map of the conventional technology is more - a second linear stable, the first linear regulator crying 3 bloody - Yu. The linear-regulator 302 only needs to supply the currents required for the first source line 1 〇〇 and the common gong, and the area * 4 仏, , , 02, so the size of the individual left-hand stream is reduced. The size of the soil is not the same as the size of the product. Overall, the integrated circuit dimensions provided by this P must be reduced by the technique of the present invention. Third, the core circuit of the Japanese circuit is made by the second circuit. The required process r. When the four brothers are screaming, the current is only passed through the transistor 3 to switch the transistor U0, and the R ϋ π is too far outside the signal. Therefore, the power efficiency can be improved. The money picture circuit of the second embodiment includes a linear regulator 200 for smashing your brother-power line. To fund the power supply, use some of the circuits in the δ 存 兀 兀 兀 兀 兀 δ δ ; ; ; ; ; ; ; ; ; ; ; ; 连接 连接 连接 连接 连接 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

0697-A40439TWF 13 1282915 第二 a second power cord € signal "Sleep" Sleep" 112 is torn through the switch, wherein the switch 槪 is connected between the electricity source source 1 〇 2, and the control module 4 〇 4 The wheel end is coupled to 112 and the wheel end is coupled to the switch 4〇6. The control module 404 controls the opening and closing of the switch 4〇6, and supplies power to the logic operation unit 1〇4 to determine a part of the circuit of the voltage source Vcc circuit 106 connected to the second power line 106. . The power supply further includes an - equalizer 4G8 connected to the first power line 丨 (10), between the integrated circuits of the force energy, and coupled to the mode signal rsleep" 112 and the action of the p ^ power line 102 for The voltage source Vcc is difficult to supply the power to the first mode, the group 402 simultaneously makes the second power line 1 (10) and the first power line _ 1G2 t simultaneously. It should be noted that the data storage unit 106 is in the upper phase. - the power cord 1GG, or as shown, can be partially connected - the connection is connected to the second power line 102, in fact the brother 1 source line - and part of the integrated circuit is in - dynamic mode Day ± ', depending on design needs. The source-to-power source and the trace are used to provide a part of the circuit for supplying the power-power line, and the remaining material storage unit 70 1 () 6 and the control module 404 enable the switch 4 〇6 dozens of money "Sleep" 112 via the power supply to the second power line (10), so that logic 2 is therefore connected to the second power line 1〇6^; 2〇 and data storage when the power dog provides the way (10) The equalizer 408 also operates to cause the first and seventh knives to move sufficiently. This is basically the same as the electricity of 1〇〇. 'U 102 and the first - power cord

0697-A40439TWF 14 1282915 Conversely, when the integrated circuit is in - static mode > ± section ~ town type 捋 'the linear regulator 200 holds the power supply to the _ power line 1 〇 _, Ding inch health saves early The circuit connected to the first power line 100 in the 7L 100 operates, but the switch "Sleep" 112 turns off the switch 4〇6 via the control module 404, and the voltage source Vcc cannot supply power to the The second power line 1〇2, ...the day-to-be-seeking 408 does not operate, and as a result, the logic unit 1〇4 and the data storage circuit 106 are connected to the second power line 100, and the circuit does not operate. As shown in FIG. 4, when the integrated circuit is in the virtual core mode, since the first power line 1〇〇 is directly coupled directly to the wheel + output of the linear regulator 200, the first power line is The voltage regulation of 100 is directly achieved, and the voltage regulation of the power supply line 102 is indirectly regulated by the equalizer 408 to be substantially equal to the voltages of the first power supply and the line 100. The operating principle of the detailed circuit will be described in detail below using the example of the circuit. The circuit construction and detailed operation modes included in Figure 4 will now be described more closely. In Fig. 4, the circuit and operation principle of the linear regulator 2 are the same as those described in Fig. 2. The switch 406 in the switch module 402 is a PMOS type switch transistor 410, and the control module 404 includes a PM 〇S type third transistor 412, and a PMOS type fourth transistor 414, wherein the third The gate of the transistor 41〇 is lightly coupled to the gate of the first transistor 206, the gate of the first transistor 206, and the gate of the switch transistor 410 and the fourth battery. The third transistor 412 is used to transmit the gate voltage of the first transistor 206 to the switching voltage in the dynamic mode when the dynamic mode is used to transmit the linear regulator 2〇〇0697-A40439TWF 15 1282915 λ ί ί ' The gate of the crystal 410 is coupled; the mode signal "Sleep" 112 is coupled to the gate of the fourth transistor 414 via an inverter 418, and the source of the fourth transistor 414 is coupled to the voltage source vcc for The fourth transistor 414 can transmit the high voltage level of the voltage source vcc to the gate of the switching transistor 410 in the quiescent mode to turn it off. The equalizer 408 is a PMOS type and has a low threshold voltage equalization transistor 416 whose source and drain are respectively coupled to the first power supply line 100 and the second power line 1〇2, and the gate is coupled. Mode signal rsleep" 112. • When the integrated circuit is in a dynamic mode, the mode signal "Sleep" 112 is at a low potential, and is converted to a surface potential via the inverter 418, so that the fourth transistor 414 is turned off, and the gate voltage of the second transistor 412 is turned off. Turning on for a low potential, the gate voltage of the first transistor 2〇6 is transmitted to the gate of the switching transistor 410 and turned on, so that the voltage source Vcc supplies power to the second power line 1〇2. At the same time, the gate voltage of the equalization transistor 416 is also turned on at a high potential, so that the voltage of the second power line 1〇2 and the voltage of the first power line 100 are substantially equal to reach the second power line. Regulatory effect. On the other hand, when the integrated circuit is in a static mode, the mode signal "Sleep" 112 is the local potential. The gate of the third transistor 412 is extremely high and is turned off, and the mode signal "Sleep" 112 is also turned via the inverter 418. At a low potential, the fourth transistor 414 is turned on and outputs a high voltage level to the gate of the switching transistor to turn off the switching transistor 410, so that the Vcc voltage source cannot supply power to the second power line ι2. At the same time, the rake signal "Sleep" 112 is turned to a low level via the inverting n 418, so the fourth transistor 4H is turned on and outputs a high-charge ink to the gate of the equalizing transistor 416.

0697-A40439TWF 16 1282915 1 Ί ^ and cut it off. It is noted that in the dynamic mode, the current supplied by the current source Vcc to the second power line 102' passes almost through the switching transistor 410 instead of the equalizing transistor 416, so that the equalizing transistor 416 does not need to have a large size. Moreover, in the static mode, this is achieved by turning off the switching transistor 410 instead of the equalizing transistor 416, and thus does not require it. The transistor 416 has a high threshold voltage. The function of the equalization transistor 416 is only to enable the two sources. The levels of the source lines can be interconnected. The voltage of the second power line 102 can be adjusted by the linear regulator 200 and is substantially the same as the voltage of the first power line 100. . Since the voltage of the second power line 102 is directly supplied by the voltage source Vcc through the switching transistor 410 in the dynamic mode, there is no need to pass the additional conventional switching transistor 110, so that there is no pressure difference between the first power line 100 and the conventional power line 100. In addition, the second power line is coupled to the first power line 100 by the equalizing transistor 416, and the gate of the switching transistor 410 is also coupled to the gate of the first transistor 206, so the linear regulator 200 can automatically The voltage of the second power line 102 is compensated to stabilize it, so that the second power line 102 can provide a stable voltage to the core circuit. In summary, the second embodiment of the integrated circuit with power gating function provided in Fig. 4 of the present invention can provide advantages over the prior art: the core circuit has no timing accuracy or a decrease in unit performance. In addition, the second embodiment of the integrated circuit with the power gating function provided by the fourth embodiment of the present invention provides several other advantages over the prior art: first, the static mode is directly cut off. The switching transistor 410 connected to the voltage source Vcc has a reduced leakage current and a reduced power consumption due to the 0697-A40439TWF 17 J282915 fee. Second, there is no large area required for the conventional switching transistor 110', and thus the circuit size is reduced. Referring back to FIG. 1 for this point, ' although this example has more switching transistor 410, control module 404, and conventional switching transistor 110 instead of equalizing transistor 416, compared to the conventional technique of FIG. Since the first transistor 206 and the switching transistor 410 only need to supply the current required by the first power line 100 and the second power line 102, the individual sizes are reduced according to the magnitude of the supplied current, and the overall size is unchanged. The control module 404 is only used for logic purposes, so the surface # is not large, and the equalization transistor 416 only needs to pass a small current caused by the small voltage difference between the first power line 100 and the second power line 102. Not big. Overall, the size of the integrated circuit provided by the present invention is thus reduced. Third, when manufacturing the core circuit, since it is not necessary to obtain the high threshold voltage of the transistor 416, it is not necessary to add the process fusion technology required for the conventional switching transistor 110 for manufacturing a high threshold voltage. Fourth, in the dynamic mode, the current only passes through the switching transistor 410, and there is no need to pass the additional conventional switching transistor 110, so the power efficiency can be improved. It is noted that the second embodiment of the fourth embodiment of the present invention includes only one operational amplifier and two resistors, as compared to the first embodiment of the present invention, including two operational amplifiers and four resistors. The size is even smaller. It will be apparent to those skilled in the art that the switches, control modules and equalizers included in the second embodiment can have other types of circuit configurations while still achieving the same objectives. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any one skilled in the art can make some use of 0697-A40439TWF 18 1282915 4 ^ without departing from the spirit and scope of the present invention. The scope of protection of the present invention is defined by the scope of the appended patent application. " [Simple description of the diagram] Figure 1 shows a block diagram of a conventional integrated circuit with a power gating function. Figure 2 shows a block diagram of a conventional integrated circuit with a power gating function in conjunction with a voltage regulator. • Fig. 3 is a circuit block diagram showing the first embodiment of the integrated circuit having the power gating function proposed by the present invention. Fig. 4 is a circuit block diagram showing a second embodiment of the integrated circuit having the power supply gating function proposed by the present invention. [Main component symbol description] 100 to first power supply line 102 to second power supply line • 104 to logical operation unit 106 to data storage unit 108 to interface unit 110 to conventional switch transistor 112 to mode signal "Sleep" 200 to linear stability Voltage converter 202 ~ operational amplifier 0697-A40439TWF 19 Ί 282915 Ί • 204~ reference voltage generator '206~ first transistor, 208~ one of the op amp input 210~ op amp input two 212~ resistor divider Output terminal 212 to output terminal 300 of linear regulator 200 to first linear regulator | 302 to second linear regulator 306 to operational amplifier 308 to operational amplifier 312~? 1^03 type transistor 314~卩"〇3 type transistor 402~switch. Module 404~control module> 40 6~ switch 408~ equalizer 410~switch transistor 412~third transistor 414~ Fourth transistor 416 ~ equalization transistor 418 ~ inverter 20

0697-A40439TWF 1282915 R1, R2, R11, R12, R21, R22~ resistance Sleep~ mode signal ’ Vcc~ voltage source

twenty one

0697-A40439TWF

Claims (1)

1282915 % Ten, the scope of application for patents: Case No. 94111820 Revised on December 29, 1995 95. 12. 29 —____________ ^ Replacement page I 1. An integrated circuit with power gating function, including: a first linear a voltage regulator coupled to a first power line for supplying power to the first power line; and a second linear regulator coupled to a second power line for determining whether to provide power according to a mode signal To the second power line, wherein the first linear regulator supplies power to the first power line when the integrated circuit is in a dynamic mode, and the mode signal causes the second linear regulator Providing a power supply to the second power line; and wherein the first linear regulator supplies power to the first power line when the integrated circuit is in a static mode, and the mode signal causes the second linearity The regulator does not provide power to the second power line. 2. The integrated circuit with a power gating function as described in claim 1, further comprising a data storage unit connected between the first power line and a ground line, and a logic operation unit connected to The second power line is between the ground line and the ground line. 3. The integrated circuit with the power gating function as shown in the first aspect of the patent application, further comprising a data storage unit and a logic operation unit, the data storage unit having a partial circuit connected to the first power line and A logic circuit is connected between the ground line and a portion of the circuit between the second power line and the ground line, and the logic operation unit is connected between the second power line and the ground line. 4. An integrated circuit having a power gating function, comprising: a linear regulator coupled to a first power line for providing power to the 0697-A40439TWF1 22 1282915 A power supply line; a switch module connected between a second power line and a voltage source, according to a mode signal to control opening and closing, to determine whether the voltage source provides power to the second power line; The first equalizer is connected between the first power line and the second power line, and is simultaneously operated with the switch module via the mode signal control, and is configured to enable the voltage source to supply power to the first mode At the same time as the two power lines, the voltage of the second power line and the first power line are substantially equal. 5. The integrated circuit with a power gating function as described in claim 4, further comprising a data storage unit connected between the first power line and a ground line, and a logic operation unit connected to The second power line is between the ground line and the ground line. 6. The integrated circuit with a power gating function as shown in claim 4, further comprising a data storage unit and a logic operation unit, the data storage unit having a partial circuit connected to the first power line and A logic circuit is connected between the second power line and the ground line, and a logic circuit is connected between the second power line and the ground line. 7. The integrated circuit with a power gating function as claimed in claim 4, wherein the mode signal causes the switch module to be turned off when the integrated circuit is in a dynamic mode. 8. The integrated circuit with the power gating function as described in claim 7 wherein the mode circuit causes the switch to be 0697-A40439TWF1 23 1282915 when the integrated circuit is in a static mode. The module is open. 9. The integrated circuit with a power gating function as described in claim 8 wherein the switch module has a control module and a switch, and the output of the control module is generated according to the mode signal. Different voltage levels are used to control the opening and closing of the switch. 10. The integrated circuit with a power gating function as described in claim 9 wherein the switch is a PMOS type switching transistor, the gate of which is coupled to the output of the #control module, the source thereof A pole is coupled to the voltage source, the drain of which is coupled to the second power line. 11. The integrated circuit with power gating function according to claim 10, wherein the linear regulator comprises an operational amplifier, a reference voltage generator, a resistor divider circuit, and a PMOS type. a first transistor, wherein an input of the operational amplifier is coupled to the reference voltage generator, and another input is coupled to an output of the resistor divider circuit, and a gate of the first transistor is coupled to the An output terminal of the amplifier, a source of the first transistor is coupled to the voltage source, and a drain of the first transistor is coupled to an input of the resistor divider and the first power line. 12. The integrated circuit with power gating function according to claim 11, wherein when the integrated circuit is in the dynamic mode, the output of the control module provides the first PMOS transistor gate The voltage level is applied to the gate of the switching transistor to control its conduction. 0697-A40439TWF1 24 1282915 9^12/3⁄4 9 曰修(更)正正% P | II 『_ ___师·镳Ι·Ι—II _1_ ! Ih Hl—I MMI HI ^—'^^^ΓΠΤΙΓΓΤΤΙ ΓΤΓΠΓΜΓΜίΤΓ II. 13. The integrated circuit with power gating function as described in claim 4, wherein the equalizer is a PMOS type transistor, the gate of which is controlled by the mode signal, and the remaining two poles respectively The first power line and the second power line are coupled. 14. The integrated circuit with a power gating function as described in claim 5, wherein the equalizer is manufactured in the same process as the data storage unit and the logic operation unit. 0697-A40439TWF1 25