TWI282684B - Optimum interpolator method and apparatus for digital timing adjustment - Google Patents

Abstract

A digital timing synchronizer of a receiver is provided for timing synchronization to a transmitter in a wireless communication system, wherein the received signal has a timing error with respect to a reference code. A channel estimator estimates an initial code phase of the received signal. A code generator generates a timing reference code that is adjustable by integer increments. An interpolation feedback circuit is configured for interpolation and correction of the timing error, whereby the interpolation is achieved through an integer code shift, plus a quantized fractional adjustment selected from a look-up table of quantized fractional adjustment values and their associated predetermine interpolator coefficients, from which a time corrected version of the received signal is produced.

Description

ι 1282684 IX. INSTRUCTIONS OF THE INVENTION · The technology to which the invention pertains The invention has a stepper of the New Zealand office, and has an effective execution of the interpolator in the _digit timing synchronizer. Prior Art In the future, the WTRU (10)_ includes but is not protected by the mobile station's mobile station's fixed or mobile subscriber unit, pager or any faceless device that can operate in a wireless environment. Neweye is in the silk, the Taiwanese system contains but is not subject to _base#, fine, fine side ϋ, deposit or no _land towel interface device. In the wireless communication system of the duplexer _) or the time division duplex (10), the timing synchronization between the transmitted and received signals of the base station and the WTRU is important for promoting the two-way communication (4). _, if the line is in the mine, the Doppler effect can be suspected of the frequency difference. In order to offset the timing difference between the base station local oscillator and the wireless transmission/reception single local oscillator, if the receiver does not have much light processing, then the wireless transmission/reception unit is connected to the local button|| The error can be corrected by applying a lead or delay to the sampling rate. However, due to the multipath signal effect, the conventional receiver of the wireless private system uses a device that can detect the multi-channel pinch signal and a device that can reconstruct the transmitted signal, such as a 耙 (_) receiver. Each route is estimated in two stages. First, the channel estimator is used to search for the approximate location of each path of the rural path communication channel in time. Secondly, for each channel, the 12822684 path and the finger-finger finger related tracking system can search for the path in time. _ Each gambling has a fine timing position. Therefore, it is not possible to correct the timing error in the _ channel environment by controlling the code timing separately. In order to deal with the problem of the township lake, Ma pursued the job to make the 执行 执行 execute the digital timing synchronization instead of controlling the local keeper. To effectively execute the interposer, a finite pulse plane (pIR) f·!! can be used. There are legs that are __ turn to have different methods. The simplest method is to use the intercept sinc function as a flush response interleaver. Another - the thin polynomial filament. Clear, minimum mean square error (_) interleaver Ke Shulang. This lining towel, the quietest variance and the finite length of the ideal inter-interpolator provides the smallest error. It should be noted that if there is a lack of a spacer U shoulder unit that ensures that the interposer is placed in the center of the main lobe of the sinc function (that is, in the middle of the interpolated function), the interpreter II can produce a higher precision than required. There is a _ impulse response coefficient. The shortcomings of the excess coefficient are intervening calculations, and in some social _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Therefore, the expansion of the consumption of the tracking device is a fine relationship. SUMMARY OF THE INVENTION The present invention provides a method for the transmission of a sequence in a wireless communication system. The channel estimator can be estimated to be connected to 1282684. The enchantment device can generate the code to be tested. The interleaved feedback circuit is configured to interpolate and correct the timing «Digital Yu' and 観自面定器魏娜之The segment delay estimation is achieved by the quantized # segment delay estimate of the S-valued lookup table, whereby the production i is received by the §flj tiger's time-corrected version. Interpolated 峨t财, is freshed, and the rate is _ Configuring to shift the received signal in time by delaying or leading the slice I. The error estimator can determine the timing error estimate by the timing difference between the input signal of the interleaving circuit and the timing reference code of the code generator. The inter-interpolator controller can respond to the timing error estimation and the timing error can be estimated in the opposite direction. Generating and transmitting the integer digital shift signal to the code is generated as 'and a segment delay estimate can be generated, whereby the interleaving can be controlled by maintaining the segment delay estimate within a predetermined range. Having the predetermined interpolator coefficient Locating the quantizer of the table' and the predetermined interpolator coefficient is correlated with the quantized segment delay estimate, selecting the quantized segment delay estimate that is closest to the segment delay estimate. The interpolator can process the coefficient of the quantized segment delay estimate correlation The present invention can be understood in more detail from the following preferred embodiments and the accompanying drawings. Embodiments Although this embodiment illustrates the third generation cooperation plan (3GPP) wideband code division multiple access using the time division duplex mode (W- CD chaotic system, but this embodiment is applicable to any hybrid code division multiple access (CDMA) / time division multiple access (TDMA) communication system. 1282684 Furthermore, this embodiment is It can be applied to a code division multiple access (CDMA) system, such as the proposed frequency division duplex (FDD) of the 3rd Generation Partnership Project. Figure 1 shows a block diagram of a preferred embodiment of the code tracker 10, including channel estimates. 11, post-processing unit 12 'code generator 13, interleaver 14, down sampler 15, timing error example, loop ship||17, stealing test 18, quantizer 19 and power measurement 20. Received signal 21 becomes an input signal to the channel estimator and interleaver 14. The code tracker 10 can perform digital timing synchronization of the receiver to the corresponding wireless transmitter. For example, in the third generation cooperation plan similar system, the code tracker 1 放置 放置 · 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 动 〇 〇 〇 〇 One method for estimating the channel estimate includes but is not subject to the use of a sliding window correlator. The sampling period of the channel estimate should be less than or equal to 2TC, where Tc is the period of a wafer job. For example, if the timing error estimator 16 uses early and late gate synchronization, the start timing error code should be limited to UdTd. Otherwise, the timing error may be fine and the calculation cannot be operated. However, the present invention is not subject to the _ early and late gate synchronizer and any other timing error estimator 16 may be used. In the latter case, different sampling intervals of the channel estimator can be used. By using the channel estimator 11 having a sampling interval of less than 2Tc, the path position intermediate error is limited to the range of -Tc to Tc. The post-processing unit 12 can estimate the signal and noise power for the noise threshold. After the post-processing 8 Ϊ 282684, all the paths with the power level above the noise gate are recognized. The position of these and day read ridges is referred to as the start path phase 22. The strongest path can be used alone or the path group above a particular root can be used in the ( (10) receiver structure. Since the RAKE receiver can effectively use the time division of the channel, it is very useful in a multipath channel environment. In the example with the strongest selected path, there is only one code tracker, which includes an interleaver 14 and an interleaver controller 18. For a RAKE receiver, it should have a one-bit tracker dedicated to each path. However, in this example, the channel estimator and post-processing unit 12 are common to all of the coded trackers. The timing synchronization is started by applying a start code phase 22 for a single path from the post-processing unit 12 to the code generator 13. For each code tracker of the ( (_) receiver, the code generator 13 can generate a reference code for the basic timing as a clock. The start code phase 22 can adjust the start timing offset of the code generator 13 in the reticle wafer only by timing in which the reference code is generated in a timely manner or delayed. After the start of the correction is completed, the code generator 13 is controlled by the code shift instruction 28 from the inter-insertion control. The start path phase 22 is applied only in two cases. The receiver is activated for the first time, and the signal power drops any time below the noise threshold. The code shift 28 is a shift command that is generated by the interleaver controller 18 in one of the leading or retarding directions. After the start correction is completed, the worst timing error estimation example is limited to the range of -Tc to Tc. Interleaving loop 35, interleaved with interleaver 14, downsampler 15, timing error estimator 16, loop filter 1282684, and interleaver controller μ, will now be explained in detail. Interleaved feedback loop 35 drives timing error estimate signal 24 to a value close to zero, and drive delay estimate 25 toward the actual delay duration. The interpolator 14 can mathematically shift the received signal in time equal to the amount received from the quantized segment delay estimate 29. The output signal from the theoretical interleaver is expressed by Equation 1 as: 00 y{n) = χ{η + 〇)= ^χ(η - m)Sinc{m -fa) Equation 1 n=~〇〇 where n For the integer time index, x(n) is the oversampled received signal 21, ό represents the quantized segment delay estimate 29, and the Sine function is defined as: Equation 2

The 7DC is reset to zero by the initial repetition of the interleaved feedback loop 35, causing the received signal through interleaver 14 to be uncorrected. Regarding the operation interleaver 14 and formulating the quantized segment delay estimate 29 (i.e., a value of zero), the second and other repetitions of the interleaved feedback loop 35 will be described in further detail. The downsampler 15 can reduce the oversampling rate of the received signal 21 by the oversampling factor 1 processed by the interleaver 14. A code tracker 1 having an interpolator μ can be applied to a receiver operating at a sampling rate of any integer value L greater than or equal to one. The code tracker 10 can perform an optimal sampling rate range of timing adjustments 丨^^ 8. The example corresponds to not oversampling. On the other hand, if the sampling rate is related to an integer, the timing error is reduced to a value of 1/16 W, whereby the contribution 1282684 of the interleaver unit 14 is significantly reduced and self-sufficient by the simple sampling shift of the downsampler 15. However, when the high oversampling rate of L-8 produces excessive power consumption of the receiver resources, it is advantageous to operate at a low sampling rate and perform code tracking on the code tracker 1 according to FIG. 1 . The convertible sampling rate is the wafer rate such that the sampling rate interval Ts is dedicated to the wafer rate interval Tc at the output of the downsampling 15 . Therefore, the output of the downsampler 15 can be expressed as z(n) as follows: z(n) = y(L - n + k) Equation 3 where k is an integer representing the base point 26 of the downsampler 15. For example, for an oversampled signal having a sample rate factor of L = 4, the sample rate interval before the down sampler 15 is Ts = TC / L = Tc / 4, and after downsampling 'which is Ts = Tc. Initially, the base point is reset to zero. The k-value variation will be explained later with reference to Equations 6a, 6 . The output of the downsampler 15 is a time correction output signal 23 that is further processed by the WTRU receiver. The power measurement unit 2 can process the round-out 23 and transmit the power measurement of the signal to the channel estimator u as a timely location of the approximate location of each path to the input of the multi-pathway. For the accuracy of the timing, the downsampling output 23 is also inserted back to the timing error estimation leg via the code tracking (4), and the timing error of the input signal is measured and transmitted as a timing error estimate. Timing error estimator 16 can operate in accordance with various known timing error estimation calculus. The preferred embodiment utilizes a morning and evening gate synchronizer. Then, the loop filter 17 can receive the timing error estimate and generate a delay estimate. 1282684 25. The choice of the type of loop filter 17 depends on the video channel. However, the invention is not limited to the particular loop filter being used. Preferably, the loop filter 17 is a first or second order filter. For example, a known proportional integrator (PI) filter can be regarded as the loop filter 17. The first-order autoregressive (AR) filter can also be used as the loop filter. The second diagram shows the preferred configuration of the loop filter 17, including the second-order proportional integrator filter 50, the accumulator 56, and the reverse. Multiplier 57. The proportional integrator filter 50 includes an integrator 51 including a multiplier 52, an accumulator 53, a multiplier 54 and an adder 55. Multipliers 52 and 54 can apply constants 3 and 13 to the timing error estimate 24 input, respectively, which are split at the input of the proportional integrator filter 50. The timing error estimate 24 input is multiplied by the constant integrator 51 of the parallel integrator 51. The parallel output is summed by adder 55 to produce a proportional integrator filter output. Next, the proportional integrator filtered state output is accumulated by the accumulator 56 and processed by a multiplier having a constant-c. The opposite sign of the constant c in multiply state 57 can produce a reverse timing correction to compensate for the timing error estimate 24' in the signal useful for the negative feedback system shown in Figure 1. Depending on the order of the loop filter, the code trace (4) may contain the first, second or even higher order feedback loop. The output of multiplier 57 is a delay estimate of 25. The output delay of the loop filter 17 is estimated to be 25 systems; ^Td is expressed as follows: Equation 4

Td = -r(Te) where Te is the timing error estimate 24 from the timing error estimator 16, and (() is the line_calculus delay estimate 25 is transmitted to the interleaved!! controller 18 for further processing 12 1282684 The interleaver controller 18 provides two main functions: a control delay estimate of 25 ranges and a minimum interpolator coefficient. First, regarding the maintenance of the _____ skill rate, the fineness is determined by the choice of the fine weighed wire legs. For example, 'for the early and late _ step type timing error estimation training, the operation 镰 _ _ _ L. There are two Qing timing error estimation view of the working surface limit signal timing variation. First of this can be shifted by the downsampler The base point of 2_2 is extended by t25 and _ is reached. However, the entire receiver of this county corresponds to the start of the change frame. It can only be understood whether there is only one-way transmission path to the receiver. However, in the multi-path environment, Preferably, the code generator 13 of the code tracker 10 dedicated to the delay direction shifting path is used in the delay estimation 25. In addition to the timing error estimator 16, the timing error estimate 24 of the received signal 21 is used as a code generator. 13 generated the reference code in the receiver The interleaver 抆U8 can control the delay estimate 25 and can reverse the shift code generator 13 regardless of its specific range. Since the code generator 13 is in the range of the chip rate _ rate To operate, the minimum shift amount is equal to the wafer persistence, that is, Tc. Therefore, 'when the delay estimate 25 becomes a record> 7 (: / Na < one Tc/2, the execution code shift 28 is better. In the implementation of the inter-communication system, the relative delay between the base station and the mobile radio transmission/reception unit receiver may be excessively changed. Mainly, it may occur for the following reasons. First, the mobile radio transmission/reception unit The movement of the receiver can be changed to 13 1282684. The needle-spinning _ wheel/storage. The receiver movement has a first-order change in the timing error. The second dynasty base station and mobile wireless transmission/ The receiving unit receives the local oscillator frequency difference. This also leads to the second-order change of 25 estimates. These effects will accumulate. However, the timing change is not the first change. The code for the fine-order change (4) Interleaver controller 18 can be used if needed According to the w-order change, the Shima shift can be performed at any required time. The code shifting decision made by the code tracker 10 is firm and does not hinder the low signal noise (SNR) and the silk test slave. In order to avoid the vibration caused by the disturbance, the shift operation depends on the shift. The delay timing and the fixed-speed action wireless transmission/reception unit action change timing are displayed in Figure 3A and 3B. The time offset is a sawtooth waveform due to the cyclic time shift of the linearly varying time delay. As shown in Figure 3A, the delay estimate 25 is linearly increasing. The peak transition occurs at the code shift sink, which is Tc/ 2 + Δ, code shift 28 is performed in a negative direction to compensate for the incremental delay estimate 25. Conversely, in the second paste, the linear degressive delay estimate 25 is compensated by the _ positive code shift 28. Although the linear change of the delay estimate 25 is depicted in the second and third graphs, it should be noted that the code tracker 1 is not limited to the linear change of the delay estimate 25, but will act on the delay estimate 25 update. Any type of change. The code shift 28 occurs in both directions as described above for delay or lead. As shown in Fig. 3A and the evil diagram, any small value of Δ (such as 〇·〇5Tc) is used to avoid the vibration behavior near the 25-point shift of the code. After the code shift 28 occurs, the new delay estimate 25 14 1282684 used by the interleaver controller 丨8 is derived as follows: $ = ?^ The subroutine where sgn[.] indicates the direction of the code shift 28 (ie Positive, negative or neither) and is defined as: ^7^,/2 + Δ Equation 5b Which is called 0,-7;/2 △ &lt;7;&lt;7;/2 + △ I a w-Tcm

Regarding the inter-inclusion of the sect of the sect of the sect of the sect of the sect of the sect of the sect of the sect of the sect. Returning to the equation, there is an infinite coefficient _ lying down __ can not be implemented. The optimal interpolator coefficients for a finite-size interleaver can minimize the unique error via the best variation, such as the minimum mean square error (瞧). Under the threat - the county is detailed. Fine, because the approximation error of the finite-interpolator can be minimized by using the ship's late estimation 27 as the equation 6a

Being stepped down. Therefore the 'interpolation view' is configured to achieve this. The delay estimate 25 after the code shift processing can be written as: fd = k, Ts + a. Ts where k is defined as follows: k = ^ Equation 6b

The UJ operand [X] represents the largest integer of X. The k value corresponds to the number of sample intervals of oversampling present in ξ. This delay or leading 简单 is a simple shift corresponding to the oversampled input signal by the amount equivalent to the k sample. This transfer of bribes is achieved by the integer k of Equation 3, 15 1282684, which reaches the base point 26 of the shift downsampler. After the base point 26 is shifted, the remaining time shift is equal to

Td:Td — k.Ts = a,Ts Equation 7

Since the interleaver 14 is normalized to the sampling rate ts, the value of the interpolator μ after quantization is the segment delay estimate 27 (i.e., 0). At the same time, it is important to note that after the decomposition delay estimate 25 (i.e., the equation is as good as the value of the equation and ^ in the equation )), the slice delay estimate 27 is limited to a range of 1 &lt; α &lt; 1 . This range limitation keeps the segment delay estimate 27 to a minimum and achieves the expected increase in interleaving errors. To depict the operation of the interleaver controller 18, it is presented in the following example. Assume that the filtered timing error estimate 25 is Td = 0.66 Tc and the oversampling rate is l = 4. Therefore, the sampling rate is Ts = TC / L = Tc / 4. According to Equations 5a and 5b, the code shift 28 is required, so the code shift delay estimate 25 is =0 = 64Tc - Tc = -0 · 36Tc. From the perspective of the private 6b, the base point 26 is k = -1, and from the equation 6a, the segment delay estimate 27 is a = - 〇 · 44 〇

Lihuazhai 19 is the last remaining stage of the interleaving feedback loop 35. The segment delay estimate 27 is quantized (i.e., discretized) by the quantizer 19 before being used by the interleaver. Quantization 1 § 19 is useful for the calculation of the interpolator coefficient limits to avoid delay estimation 25 being updated each time. The arbitrator 19 includes a lookup table for storing pre-computed interpolator coefficients associated with a set of available quantized segment delay estimates. This lookup table reduces the complexity of interleaving and increases processing speed. Quantizer 丨9 may determine a number of levels based on the required timing accuracy and oversampling rate L to quantize the segment delay 16 &gt; 1282684 estimate. The timing accuracy required for timing adjustment is Tc/q, which is a positive integer. She refused to suspect her e/Q. ____ 2 ^&lt;α&lt;1 fine 嶋化 level. For example, if the needle is 4, the price of money needs to be shameful/16, and the level of fineness of the test is fine. Then, according to the above example, the correction segment delay estimate 27 is α 44, and the quantized delay can be determined from the nearest money of the self-contained money key. Because this is a bit of a store, so the job is from the following _, the king does not create interleaving so it is not used). Because _0· seems to be closest to A 5, it is the same as the initial iteration of the inter-insertion loop 35 The continuation is repeated to track the change in timing error. Returning to inter-interpolator 14, the finite interleaving of Equation 1 will be described, including an interleaver, which is initially processed to receive revenue 21. As shown by the equation, the ideal interpolated system is the sum of infinite lengths. In order to be effective, _ must be a finite addition of Equation 1. The following equation 8a indicates that the output is not limited to the following: m2 Equation 8a x~(4)(8) Its ~(8) represents the interpolated coefficient, which is derived as follows: 1282684 Equation 8b Equation 9 ^ά(η) = Sinc(m + ά) The frequency response of the ideal interpolator of the infinite length filter is as follows: 8(ω,αΤ3) = ίτ^&amp;αΤ\\ω/2π\ &lt;l/(2Ts) [ 0, otherwise Output signal error ugly (6) The difference between the finite representation of the ideal interpolator rotation and the interleaver is determined by equation A. Ε(ά) = χ(/7 + ά) - χ(^η _μ ^

The most _ _ _ inter-interpolator coefficient... is determined by minimizing the following program 11 to determine the best way to use the errata version. The frequency of the scales is less than l/(2Ts) ‘Applying the Parseval relationship to Equation 1〇 produces: Ε\ά)=] jwaTs M2- YjhMe'ji m--Mx jcoaTs άω Equation 11

Equation 11 represents the finite impulse response filter, the minimum mean square error version of the waver, which is the 'ϋ compared type of the interleaver 14. The formula u has several different solutions. For example, the Fletcher-Powell method can be used to solve equation u. It should be noted that embodiments of the invention are not limited to any particular solution of Equation 11. If (M1=M) and (Μ24Η) are selected for the total number of 2Μ coefficients, the minimum difference is achieved. Since the coefficients are found from Equation 12, the optimal minimum mean squared finite impulse response interpolator 14 can be represented by the following equation: Μ-1 ^a) = ^{nm)hM) Equation i2 18 1282684, as known to the skilled artisan The coefficient is a rim, which can be written as ^(1-Fantasy 1)' When it is not possible, the value of the 13th value of the previous (4) and the predetermined coefficient is stored in the lookup table of the quantizer 19. This derivation Μ · ((Q/D-2) size of the real number of people σ check, its genemark is quantitative quiz: and □ is α-0疋 all will not produce interpolated, so it is excluded from quantification The lookup table size can be reduced by the M ((Q/L) 2)/2 κ number by using the symmetry property of Equation 13. Alternatively, the interleaver structure is implemented. However, if a polynomial interleaver is used, the lookup table can be deleted and replaced by an instant calculation. In practice, depending on the interpolation error, M d has a 2 Μ coefficient W). For example, the code tracker designed for the receiving state of the third generation cooperative plan receiving unit includes the early and late gate synchronizer, two oversampling (L=2), and the integral including the accumulator as shown in Fig. 2. The first P white loop filter state of the vessel produces M=2 or a total of four coefficients at the parent quantizer level. For the required accuracy of Tc/16 (that is, Q=i6), the quantizer level used is 8. According to the present invention, by optimizing the interpolation, the timing is effectively reduced regardless of whether or not the coefficient limit number is used. The favorable results of the error can be achieved. Although the present invention has been described with reference to a multipath fading channel and a rake receiver, it is not limited to these applications. Alternative embodiments of code tracker 10 include, but are not limited to, inter-interleavers of the following types: polynomial finite impulse response interleaver, linear interleaver, 19 1282684 and Lagrange interleaving. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a block diagram of a code tracker with optimal interleaving; Fig. 2 shows a block diagram of a loop filter; Fig. 3A, Fig. 3B shows a code shift timing diagram of a code tracker;

Component symbol description: 10 code tracker 11 channel estimator 12 post processing unit 13 code generator 14 interleaver 15 down sampler 16 timing error estimator 17 loop filter 18 interleaver controller 19 quantizer 20 power measurement Unit 21 is received signal 22 Start path phase 23 Time correction output signal 24 Timing error estimation signal 25 Delay estimation value 26 Base point 27 Fragment delay estimation 28 Code shift instruction 35 Interleaving feedback loop 29 Quantization segment delay estimation 50 Proportional integrator Filter·wave fast 51 integrator 53 , 56 accumulator 55 adder 52 , 54 , 57 multiplier a ^ b constant

20

Claims (1)

1282684 X. Applying for a patent Fan Park························································································· a channel estimator configured to estimate a start code phase of the received signal; a code generator configured to generate a timing reference code that can be adjusted by an integer increment; and configured to interpolate and correct The timing error is inserted into the feedback circuit, whereby the inter-parallel insertion can be achieved by the integer digital shift and the look-up table of the selected self-quantized segment delay estimation value and the reticle alignment. The time-corrected version of the received signal is generated therefrom. 2. The digital timing synchronization H of claim 1 of the patent scope, wherein the interleaving feedback circuit further comprises: the i-scaled inter-rate inter-interpolator is configured to bring the ship to the ship late or lead in time to shift Received signal; φ ▲ Sequential Wu difference estimated juice is 'can wire ^ the inter-insertion circuit output signal and the timing reference code this scale is more error-free; inter-interpolator controller, can return timing The error estimate is generated by the timing error estimation inversion and the __峨 domain is generated within a predetermined range to generate a segment delay estimate to ride the _Wei; and /, yes, the predetermined I slice is estimated to be correlated with the stored interleaving 21 1282684 The miscellaneous table of the benefit coefficient, the churning observation of the financial segment is closest to the estimated delay of the segment delay estimation. 3. The digital timing synchronizer of claim 2, wherein the interleaving feedback circuit comprises a filter that can detect the delay estimate of the timing error estimate with a delay estimate. Thereby, the interleaver controller can pre-record the peak delay to estimate the delay estimate in the timing material II. 4. The digital timing synchronizer of claim 3, wherein the interleaving path further comprises a sampler that can be returned to the interleaver controller, configured by a fibrillation factor and according to the The base point associated with the ratio of the received signal and the sampling rate of the delay estimate reduces the sampling rate of the received signal. 5. The digital timing synchronizer of claim 2, wherein the interpolator is a minimum mean square error optimized finite impulse response interleaver. 6. The digital timing synchronizer of claim i, wherein the received signal system comprises a plurality of jobs, and the interleaved feedback circuit enters a step _step including a single heart #被出职(四)计开始The code is used to encode the noise power of the tantalum between the base and the base, thereby generating the code generator to develop the start code phase of the reference code. 7. If the digital timing synchronizer of claim 1 is applied, the predetermined range of the delay estimate of the segment is between (_1) A(1). For example, the scope of the patent application scope! The digital timing synchronizer, wherein the received signal is excessively factored by the L factor and the predetermined number of quantized segment adjustment values is a quantization bit determined according to 22 ' I282684 ^ timing adjustment precision t/q of timing adjustment The quasi-team's: τ represents the sampling period 'Q stands for a positive integer, and l stands for a positive integer. For example, the digital timing synchronizer of the i-th article of the patent application scope is the first one of the digital transmission/reception unit of the patented range. e 11. - Shooting the radio recording and the digital device of the contactor. The method of synchronization is based on the timing error timing of the reference code. Estimating the start code phase of the received signal; generating a timing reference code that can be adjusted by intensification: incremental adjustment; timely error, whereby the interpolated _____ = _ segment delay estimate of the rhyme table of the fragmentation delay value And its related pre-single number is reached, the time-corrected version of the received m is produced from it 12. The method of claim </ RTI> wherein the interleaving and correcting step further comprises: framing delay or leading to shift the received signal in time, based on the time corrected version of the received signal and the timing reference code The timing difference between the two determines the timing error estimate; the inverse of the timing error is used to generate the integer digital shift signal; 23 Ϊ 282684 in the dare _ domain to observe the _ _ coefficient; and. The side interpolator coefficients are in the lookup table, and the quantized version delay estimate that is closest to the segment delay estimate is selected from the lookup face. The method of claim 12, wherein the interpolating step further comprises a delay estimate of the inverse view of the filter-sequence estimation domain, wherein the delay estimate is controlled by the timing error fine-matching · Within the relevant predetermined operating range. 14. The method of claim 13, wherein the interpolating step further comprises an oversampling factor, wherein the sampling rate of the received signal is reduced according to a base point of the received signal and the ratio of the rate. . 15. The method of claim n, wherein the received signal comprises a multipath, and the interpolating step further comprises processing the estimated start code phase and the estimated signal and the noise threshold of the noise threshold. This produces the code generator to develop the start code phase of the reference code. 16. The method of claim 12, wherein the predetermined range of the segment delay estimate is between (4) and (1). 24 1282684 VII. Designation of Representative Representatives: The representative designation of the case is as follows: (i) Figure 1)) The component of the representative ® is a list of explanations: 10 code tracker u 13 code generator 14 16 timing error estimator 17 19 Quantizer 20 22 Start Path Phase 23 24 Timing Error Estimation Signal 28 Code Shift Command &amp; 35 Interleaved Loop Channel Estimator 12 Post Processing Unit Interleaver 15 Downsampler Loop Filter 18 Interleaver Controller Power measurement unit 21 is received signal time correction output signal 26 base point 27 segment delay estimation quantized segment delay estimation case right * chemical handle, copper shows the most basic chemical formula