1282551 <@ill9494號專利申請案 中文說明書替換頁(95年8月） 玖、發明說明： 【發明所屬之技術領域】 本發明係關於-使用雙門檻電壓電晶體之靜態記憶體，其巾咖似惟電壓電 晶體來驅動資料位元線，並使用高低門檻電壓電晶體來贿:雜，以擷取高與低門 檻電壓的優點，來達成加速記憶體操作和降低待機功率消耗 【先前技術】 近年來，不論是個人電腦或是工作站等電子設備，為了加快其運算速度以及執 行更大的制程式，對記憶體存取速度的要妓越來越高。然而，由於製程的進步 與縮小化，電晶體臨界電壓細之料化為—必紅_，將硫姐界電流過 大，或是漏電流過大之情形’對於高速存取與資料維持產生困難。因此本發明即利 用雙門檻電壓針對靜態記憶體來加以改良。 先前之SRAM製程技術因為無論是PM0S或是雇沉均僅具有單一之臨界電 壓。-個先前技術中所示之6-T SRAM記憶單元示於圖一中，其^中ι〇ι與1〇2為字 元線控制之位元線驅動電晶體，而PM0S 103、1〇4與繼〇s 1〇5、1〇6、形成資料 儲存之_ (臟）。因此若這些電晶體之臨界電壓過高，且作為位元線驅動/時， 將產生開關時間過長之問題；反之若臨界電壓過低，且作為背對背耗合之記情問鎖 時’因為臨界電壓低，導致漏電流增加’除了破壞資料之電壓之外，也造成^必要 之電力消耗。因此，本發明將同時解決前述之無法同時達成縮短存取時= 料電壓之問題，而且無需額外之電路成本。 ^ 、 【發明内容】 本發明之-目㈣-綱兩個獨臨界電壓電晶體構成_ SR^挪… 其中具有第-臨界電壓之電晶體以背對背交又輕合之方式形成儲存資料元及 具有第二臨界電壓之f晶體作為位元線驅動元件，無需更改製程 作與維持資料之目的。 ^ ^ ^發明之另-進-步之目的為-利用_不同臨界電晶體構成—S顯 記憶單70,其巾具有第-臨界f壓之電晶體以背對背交讀合 _ 元件，以及具有第二臨界電壓之電晶體作為位元線驅動元件，前第^儲存貝料 =於前述之第二臨界電壓’因此無需更改製程’而可達到高速操二特 6 令却⑽494號專利申請案 中文說明書替換頁(95年8月） 為了達成上述之發明目的，本發明包括複數個記憶單元所構成之記憶陣列，其 中。己丨思單元係由複數個電晶體構成資料閂鎖，以及兩個nmqs導通電晶體連接一 位元線對，複數條輸入位址線以定址所欲存取之記憶單元；一列解碼器，用以根據 前述輸入位址線之一部份進行解碼，產生一字線控制信號以驅動整列之複數個記憶 單兀；一行解碼器，用以根據前述輸入位址線之一部份進行解碼，以產生一選擇信 號來選擇前·鴨之記鮮元域元線，進行寫人或讀㈣作；減個感測放大 器（sense amplifier，SA)，用以偵測前述被選擇之位元線對上之差異，予以放大成 為輸出；一資料輸出輸入緩衝器電路，將被選擇之位元線對上之資料予以鎖住，以 進行寫入或讀出動作；一控制電路，其係用以產生其他電路所需之時脈信號與控制1282551 <@ill9494 Patent Application Chinese Manual Replacement Page (August 95) 玖, Invention Description: [Technical Field] The present invention relates to a static memory using a double-gate voltage transistor, A voltage-like transistor is used to drive the data bit line, and the high and low threshold voltage transistors are used to bribe: to extract the high and low threshold voltages to achieve accelerated memory operation and reduce standby power consumption. [Prior Art] In recent years, electronic devices such as personal computers and workstations have become more and more expensive in terms of memory access speeds in order to speed up their computing speeds and execute larger programs. However, due to the progress and reduction of the process, the critical voltage of the transistor is reduced to - must red, the current of the sulfur boundary is too large, or the leakage current is too large, which makes it difficult for high-speed access and data maintenance. Therefore, the present invention improves the static memory by using a double threshold voltage. Previous SRAM process technology has only a single critical voltage, whether it is PM0S or hiring. A 6-T SRAM memory cell shown in the prior art is shown in Figure 1, where ι ι and 1 〇 2 are bit line controlled bit line driving transistors, and PM0S 103, 1 〇 4 With the 〇 s 1 〇 5, 1 〇 6, the formation of data storage _ (dirty). Therefore, if the threshold voltage of these transistors is too high, and as a bit line drive / time, it will cause a problem that the switching time is too long; if the threshold voltage is too low, and as a back-to-back consumption, the lock is called because of the criticality. The low voltage causes the leakage current to increase. In addition to destroying the voltage of the data, it also causes the necessary power consumption. Therefore, the present invention simultaneously solves the aforementioned problem that the access voltage cannot be simultaneously shortened, and no additional circuit cost is required. ^, [Summary of the Invention] The present invention - the four (four) - the two unique threshold voltage transistor constitutes _ SR ^ move... The transistor having the first threshold voltage forms the storage data element in a back-to-back and light-weight manner and has The f-crystal of the second threshold voltage acts as a bit line driving element, and does not need to change the process for maintaining and maintaining data. ^ ^ ^ The other purpose of the invention - the purpose of the step - is to use - different critical crystals - S memory memory 70, the towel has a first critical f-voltage transistor to back-to-back read-in _ components, and has The second threshold voltage transistor is used as the bit line driving component, and the first storage material is the second threshold voltage 'therefore, no need to change the process', and the high speed operation can be achieved. Replacement Page (August 95) In order to achieve the above objects, the present invention includes a memory array constructed of a plurality of memory cells, wherein. The unit has a data latch composed of a plurality of transistors, and two nmqs conductive crystals are connected to one bit line pair, a plurality of input address lines are addressed to the memory unit to be accessed; and a column decoder is used. Decoding according to a portion of the input address line to generate a word line control signal to drive a plurality of memory cells of the entire column; a row of decoders for decoding according to one of the input address lines Generating a selection signal to select the pre-duck's fresh element domain line for writing or reading (4); and subtracting a sense amplifier (SA) for detecting the selected bit line pair The difference is amplified to be an output; a data output input buffer circuit locks the data on the selected bit line pair for writing or reading operations; and a control circuit that is used to generate other Clock signal and control required by the circuit
因此，在一後文中所示之實施方式中，本發明所揭示之靜態隨機存取記憶體由 下列各組件所組成： 複數個兄憶單元所構成之記憶體陣列（mem〇ryaiTays); 列解碼器（row decoder ); 行解碼為（column decoder ); 複數個感測放大器（senseampliger，Sa); 資料輸出輸入緩衝器電路； 控制電路（control circuitry，CC); 止擾器（quenchers) 〇 【實施方式】 圖二為本發明之一較佳實施例系統圖，2〇1為記憶體陣列，其由複數個記憶單 元所構成，亦可安排為階層式多個記憶庫（bank)之格式；2〇2為列解碼器，其接 收。卩分之位址線，進行解碼，產生至少一字線驅動信號，以驅動一列之記憶單元； 203為行解碼器，其亦接收其他部分之位址線，進行解碼，產生至少一位元線選擇 指號給記憶體陣列201，以將所欲存取之記憶單元進行讀取或寫入；2〇4為複數個 感測放大器組成之電路，其將位元線對間之信號差異予以放大，加速操作；2〇5為 貝料輸出輸入緩衝器電路，其根據2〇6控制電路之信號，將位元線與外部匯流排耦 接’將被選擇之位元線對上之資料予以鎖住，以進行寫入或讀出動作；施為控制 電路，主要功能為接收外部給定指令信號，解碼之後，產生時脈信號與控制信號予 7 19494號專利申請案 中文說明書替換頁(95年8月） 前述各方塊之電路 圖三為本發明所提出之記憶單元電路，本發明之記憶單元係由複數個電晶體形 成背對背交叉耦合而成之一閂鎖，以及兩個由字元線選擇信號控制之導通電晶體連 接一位元線對。在本實施例中，303與304為NMOS電晶體，其與3〇5、3〇6 pM〇s 電晶體分別形成反相器，此兩反相器以背對背耦合之方式連接，形成一儲存資料之 問鎖（latch)，301與302為NMOS電晶體，其閘極由字元線（WL，w〇rdUne)控 制，兩者分別再接到位元線對之一，BL與BLB。當WL為高電位時，資料儲存節 點Q與QB將與BL與BLB耦合，反之，當WL為低電位時，資料儲存節點Q與 QB將與BL與BLB形成斷路。Therefore, in an embodiment shown in the following, the static random access memory disclosed by the present invention is composed of the following components: a memory array composed of a plurality of brother cells (mem〇ryaiTays); column decoding Row decoder; row decoder; multiple sense amplifiers (Sa); data output input buffer circuit; control circuitry (CC); quenchers (quenchers) 〇 [implementation 2 is a system diagram of a preferred embodiment of the present invention, and 2 is a memory array, which is composed of a plurality of memory units, and can also be arranged in a hierarchical multi-bank format; 〇2 is the column decoder, which receives. Decoding the address line, decoding, generating at least one word line driving signal to drive a column of memory cells; 203 is a row decoder, which also receives other part of the address line, performs decoding, and generates at least one bit line Selecting an index to the memory array 201 to read or write the memory cell to be accessed; 2〇4 is a circuit composed of a plurality of sense amplifiers, which amplifies the signal difference between the bit line pairs Accelerating operation; 2〇5 is a bunker output input buffer circuit, which couples the bit line to the external bus bar according to the signal of the 2〇6 control circuit to lock the data on the selected bit line pair Live to write or read out; as a control circuit, the main function is to receive an external given command signal, after decoding, generate a clock signal and control signal to the Chinese version of the patent application 7 19494 replacement page (95 years) August) The circuit diagram of the foregoing blocks is the memory unit circuit proposed by the present invention. The memory unit of the present invention is formed by a plurality of transistors forming a latch-up of back-to-back cross coupling, and two The word line selection signal controls the conduction current crystal to connect a bit line pair. In this embodiment, 303 and 304 are NMOS transistors, which respectively form inverters with the 3〇5, 3〇6 pM〇s transistors, and the two inverters are connected in a back-to-back coupling manner to form a stored data. The latches 301 and 302 are NMOS transistors whose gates are controlled by word lines (WL, w〇rdUne), which are respectively connected to one of the bit line pairs, BL and BLB. When WL is high, data storage nodes Q and QB will be coupled to BL and BLB. Conversely, when WL is low, data storage nodes Q and QB will form an open circuit with BL and BLB.
由於高臨界電壓之電晶體具有低漏電流之特性，適合作為存裝置，相對地，低 臨界電壓之電晶體具有高輸出電流與開關速度較快之特性，適合作為輸出駆動哭。 因此我們將303、304、305、306以高臨界電壓（high-Vth)之電晶體來實現，而 將301、302以低臨界電壓（l〇w-Vth)之電晶體來實現。本發明之一較佳實施例係 以台灣積體電路公司（TSMC)之lP5M0.25umCMOS製程來實施，該製程中具 有二種臨界電壓之電晶體’高者為Nominal Vth ( = 0.53 V),低者為Native vth (= 0·21 V)。第一、二、三表分別列出在不同溫度下，〇〇c、25〇c、75〇c，各種電曰體 第二個字母為PMOS)所產生之電流，所有的情形均顯示低臨界電壓（i〇w ν&) 之電晶體，即Native Vth電晶體具有較大之輸出電流。 第一表Since the transistor with high threshold voltage has the characteristics of low leakage current, it is suitable as a memory device. In contrast, a transistor with a low threshold voltage has a high output current and a fast switching speed, and is suitable as an output swaying cry. Therefore, we implement 303, 304, 305, and 306 as high-voltage (high-Vth) transistors, and 301 and 302 as low-voltage (l〇w-Vth) transistors. A preferred embodiment of the present invention is implemented by the Taiwan Semiconductor Integrated Circuits Corporation (TSMC) lP5M0.25um CMOS process, in which the transistor having two threshold voltages is 'Nominal Vth (= 0.53 V), low It is Native vth (= 0·21 V). The first, second and third tables respectively list the currents generated by 〇〇c, 25〇c, 75〇c, and the second letter of the various electric rafts at different temperatures, and all cases show low criticality. The transistor of voltage (i〇w ν &), the Native Vth transistor, has a large output current. First table
Model TSMC 0.25um Process ( 0 C) 増加比例 Native Vt Nominal Vt Bit line current (uA) Bit line current (uA) TT 278 199 --------- _ ?0 7/1 230 163 SF 255 191 ---^LLsJJl_ C 1 FS 301 207 FF 336 241 ~---------- ^^39.42 第二表 8 19494號專利申請案 中文說明書替換頁(95年8月）Model TSMC 0.25um Process ( 0 C) V Plus ratio Native Vt Nominal Vt Bit line current (uA) Bit line current (uA) TT 278 199 --------- _ ?0 7/1 230 163 SF 255 191 ---^LLsJJl_ C 1 FS 301 207 FF 336 241 ~---------- ^^39.42 Second Table 8 19494 Patent Application Replacement Chinese Manual Replacement Page (August 95)
Model TSMC 0.25um Process (25 °C) 增加比例 Native Vi Nominal Vt Bit line current (uA) Bit line current (uA) (%) TT 260 191 _ 36.13 SS 215 156 _ 37.82 SF 239 183 30.60 FS 283 198 42.93 FF 314 232 _ 35.34 第三表Model TSMC 0.25um Process (25 °C) Increase the ratio Native Vi Nominal Vt Bit line current (uA) Bit line current (uA) (%) TT 260 191 _ 36.13 SS 215 156 _ 37.82 SF 239 183 30.60 FS 283 198 42.93 FF 314 232 _ 35.34 Third table
Model TSMC 0.25um Process (75 °C) 增加比例 Native Vt Nominal Vt Bit line current (uA) Bit line current (uA) (%) TT 232 174 33.33 SS 188 141 33.33 SF 212 168 26.19 FS 252 182 38.46 FF 281 214 3131Model TSMC 0.25um Process (75 °C) Increase the ratio Native Vt Nominal Vt Bit line current (uA) Bit line current (uA) (%) TT 232 174 33.33 SS 188 141 33.33 SF 212 168 26.19 FS 252 182 38.46 FF 281 214 3131
圖四為本發明之一較佳實施例中之記憶單元、位元線、行選擇器、感測放大器、 輸出緩衝器、與預充電等化器之電路圖。401即為圖三中之記憶單元，402為其預 充電等化器；403為Y-選擇器，其接收來自203行解碼器之輸出，將BL、BLB分 別耦接至輸出信號線DL、DLB;404為DL、DLB之預充電等化器；405為止擾器， 而406為感測放大器，而407為雙端電流鏡放大器及閂鎖，與輸出緩衝器耦接。 止擾器405為一對背對背相接之二極體所構成，其功能描述如下。一般傳統記 憶體之輸出信號線上之讀寫過程中所產生之震盪，在兩條信號線（DL，DLB)上 疋反相的，如圖五所示之現象。因此，我們以一對背對背相接之二極體，跨接在兩 條信號線（DL，DLB)，如此一來可以形成一迴圈，將兩信號線之訊號彼此抵銷， 結果如圖六所示。如此一來，不但資料信號線上之電壓收斂到穩態較快，同時也降 低功率消耗，達到高速度與低功率之效果。而在CM〇S製程中，二極體並不容易 單獨形成，我們可以利用閘極-源極-短路之MOS電晶體（G-D-shortMOS transistor) 來代替，效果相同。 圖七為本發明之一較佳實施例與相同尺寸之先前SRAM記憶單元之模擬波形 圖，經由此圖之比較，可以確認以Native VthNM〇s電晶體，確實較快，也能提供 較大之電流給位元線。 9 I28^^1u9494號專利申請案 中文說明書替換頁(95年8月） 圖八為達成本發明之目的之另一較佳實施例，其為一 4T SRAM記憶單元。其 中601、602為使用低臨界電壓（low-Vth)之_03電晶體為導通電晶體，作為 驅動位元線之用，而603、604為交又耦合之高臨界電壓（high-Vth)之NMOS電 晶體，作為資料儲存閂鎖。 圖九為達成本發明之目的之另一較佳實施例，其為一 4T SRAM記憶單元。其 中701、702為使用低臨界電壓（丨ow_Vth)之_〇8電晶體為導通電晶體，作為 驅動位元線之用，而703、704為交又耦合之高臨界電壓（high-Vth)之PMOS電 晶體，作為資料儲存閂鎖。4 is a circuit diagram of a memory unit, a bit line, a row selector, a sense amplifier, an output buffer, and a precharge equalizer in a preferred embodiment of the present invention. 401 is the memory unit in FIG. 3, 402 is its pre-charge equalizer; 403 is a Y-selector, which receives the output from the 203-line decoder, and couples BL and BLB to the output signal lines DL, DLB, respectively. 404 is a DL, DLB pre-charge equalizer; 405 is a disturbance, and 406 is a sense amplifier, and 407 is a double-ended current mirror amplifier and latch, coupled to the output buffer. The stop 405 is constructed by a pair of back-to-back diodes, the function of which is described below. Generally, the oscillation generated during the reading and writing process on the output signal line of the conventional memory is reversed on the two signal lines (DL, DLB), as shown in FIG. Therefore, we connect a pair of back-to-back diodes across two signal lines (DL, DLB), so that a loop can be formed, and the signals of the two signal lines are offset each other. Shown. In this way, not only the voltage on the data signal line converges to a steady state, but also reduces power consumption, achieving high speed and low power. In the CM〇S process, the diodes are not easily formed separately. Instead of using a gate-source-short-MOS transistor, the effect is the same. Figure 7 is an analog waveform diagram of a preferred embodiment of the present invention and a previous SRAM memory cell of the same size. By comparison of the figure, it can be confirmed that the native VthNM〇s transistor is indeed faster and can provide a larger one. Current is given to the bit line. 9 I28^^1u9494 Patent Application Replacement Page (August 95) Figure 8 is another preferred embodiment for achieving the object of the present invention, which is a 4T SRAM memory unit. Among them, 601 and 602 are _03 transistors using low-voltage (low-Vth) as the conduction current crystal, which is used as the driving bit line, and 603 and 604 are the high-voltage (high-Vth) of the coupling and coupling. NMOS transistor, as a data storage latch. Figure 9 is another preferred embodiment of the object of the invention, which is a 4T SRAM memory unit. Among them, 701 and 702 are _8 transistors using low threshold voltage (丨ow_Vth) as conduction current crystals, which are used as driving bit lines, and 703 and 704 are high-voltage voltages of high and low coupling. PMOS transistor, as a data storage latch.
圖十為達成本發明之目的之另一較佳實施例，其為一 4T SRAM記憶單元。其 中8(H、802為使用低臨界電壓〇ow-vth)之pM〇s電晶體為導通電晶體，作為 驅動位元線之用，而803、804為交叉耦合之高臨界電壓（high-Vth)之NM〇s電 晶體，作為資料儲存閂鎖。 工業上之適用性： 此發明可適用於：SRAM ’内嵌式SRAM之設計與製造。本發明已由前述之 較佳實施例（embodiment)所描述，而在本發明所提出之申請專利範圍(daim)，熟 習於本發明之贿者，可由其内容而思及並產生其他技^方式（mGdifieati〇n)， 但均不超出本發明之範疇。 【圖式簡單說明】 圖一、先前技術：傳統6-TSRAM記憶單元； 圖二、本發明之一較佳實施例； 圖三、本發明之一較佳實施例之記憶單元； 圖四、本發明之一較佳實施例之記憶單元位元線電路圖； 圖五、未使用止擾器之模擬波形圖； 圖六、使用止擾器之模擬波形圖； 圖七、本Μ之-健實施狀記鮮賴撤猶先紐狀記鮮元比較； 圖八、本發明之另一較佳實施例之4-Τ記憶單元； 圖九、本發明之另一較佳實施例之4-Τ記憶單元； 圖十、本發明之另一較佳實施例之4-Τ記憶單元。 【主要元件符號說明】 128^ ^J119494號專利中請案 中文說明書替換頁(95年8月） P3, P4, P5, P6, P7, 103, 104, 305, 306, 703, 704 101，102, 103, 104, 303, 304, N5, N6, N7, N8, 603, 604, 803, 804 801,802 301，302, 601，602, 701，702 具一般正常臨界電壓之PMOS電晶體 具一般正常臨界電壓之NMOS電晶體 具低臨界電壓之PMOS電晶體 具低臨界電壓之NMOS電晶體Figure 10 is another preferred embodiment for achieving the objects of the present invention, which is a 4T SRAM memory unit. The pM〇s transistor in which 8 (H, 802 is a low threshold voltage 〇ow-vth) is a conducting current crystal, which is used as a driving bit line, and 803 and 804 are cross-coupling high threshold voltages (high-Vth). ) NM〇s transistor, as a data storage latch. Industrial applicability: This invention is applicable to the design and manufacture of SRAM ’ embedded SRAM. The present invention has been described by the above-described preferred embodiments, and in the patent application (daim) proposed by the present invention, the bribe of the present invention can be considered by its contents and produces other techniques. (mGdifieati〇n), but none of the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a prior art: a conventional 6-TSRAM memory unit; FIG. 2 is a preferred embodiment of the present invention; FIG. 3 is a memory unit according to a preferred embodiment of the present invention; FIG. 5 is a schematic diagram of a memory cell bit line diagram; FIG. Figure 8 is a 4-Τ memory unit of another preferred embodiment of the present invention; Figure 9 is a 4-Τ memory unit of another preferred embodiment of the present invention. Figure 10 is a 4-inch memory unit of another preferred embodiment of the present invention. [Description of main component symbols] 128^^J119494 Patent request replacement Chinese manual replacement page (August 95) P3, P4, P5, P6, P7, 103, 104, 305, 306, 703, 704 101, 102, 103, 104, 303, 304, N5, N6, N7, N8, 603, 604, 803, 804 801, 802 301, 302, 601, 602, 701, 702 PMOS transistors with a normal normal threshold voltage with a normal normal threshold voltage NMOS transistor with low threshold voltage PMOS transistor with low threshold voltage NMOS transistor
Cbl5 Cwl5 電容 401 記憶單元 WL 字元線 402 預充電等化器 BL，BLB 位元線 403 Y-選擇器 AO 〜All 位址線 404 預充電等化器 DIN 資料輸入線 405 止擾器 DOUT 資料輸出線 406 感測放大器 CLK 時脈訊號 407 雙端電流鏡放大器及 閂鎖 WR 讀寫控制線 DL，DLB 資料信號線 EN 致能訊號 SAEN 感測放大器致能訊號 PCH 預充電訊號 EQ 等電位訊號 Y 位元線輸出傳輸閘 11Cbl5 Cwl5 Capacitor 401 Memory Cell WL Word Line 402 Precharge Equalizer BL, BLB Bit Line 403 Y-Selector AO ~ All Address Line 404 Precharge Equalizer DIN Data Input Line 405 Stopper DOUT Data Output Line 406 sense amplifier CLK clock signal 407 double-ended current mirror amplifier and latch WR read and write control line DL, DLB data signal line EN enable signal SAEN sense amplifier enable signal PCH pre-charge signal EQ equipotential signal Y bit Yuan line output transmission gate 11