TWI281249B - NAND-type non-volatile memory - Google Patents

Abstract

A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned on the data storage elements, an insulating layer covering surfaces and sidewalls of the plurality of control gates, and a bit line positioned on the insulating layer to cross the plurality of control gates.

Description

1281249 IX. Description of the Invention: [Technical Field] The present invention relates generally to a non-volatile memory, and more particularly to a NAND-type non-volatile memory. [Prior Art] Flash memory is a non-volatile memory that can continue to save data in the memory after the power is turned off, and can quickly perform repeated reading and data stylization and erasing operations. It is one of the most frequently used and fastest growing memory products. According to its architecture, flash memory can be divided into NOR flash memory and NAND flash memory. The memory of NOR flash memory is extremely parallel, so the reading speed is fast. It is used in program code-based code flash, and the NAND-type flash memory has two poles connected in series with the source, so it can accommodate more in unit area. The memory unit makes the density of the memory unit high, and is suitable for data flash which is mainly based on accessing data. Whether it is NOR flash memory or NAND flash memory, its memory cells have a similar MOS transistor structure, which can provide small size, high read speed and high density, etc. 1281249 Please refer to Figure 1, page 1 is a schematic cross-sectional view of a conventional flash memory. As shown in FIG. 1, the flash memory 10 includes a substrate 12, a P-type well 14 is formed on the surface of the substrate 12, a plurality of N-type doped regions 16 are formed on the surface of the P-type well 14, and a plurality of oxide layers are formed. 18. A stacked structure of a material layer such as a floating gate 20, an oxide layer 22, and a control gate 24 is disposed on the surface of the substrate 12. Each of the N-type doped regions 16 is used to define a buried drain/source (BD/BS), and between two adjacent N-type doped regions 16 is defined as the channel region L of each of the memory cells. In the process, the N-type doping region 16 is formed by using a doping process in the P-type well 14 after completing the pattern definition of the stacked structure such as the oxide layer 18, the floating gate 20, the oxide layer 22, and the control interlayer 24. The surface is implanted with N-type ions, followed by a thermal process to activate and diffuse these N-type ions to define the contour of the N-doped region 16 and the channel region L. During the above thermal process, the length of the channel region L is shortened due to the horizontal diffusion of the N-type ions implanted in the P well 14 . Therefore, in order to make the channel length conform to the component electrical requirements, a more common way in the prior art is to increase the line width of the stack structure such as the control gate 24, so that the distance between the two adjacent N-type doping regions 16 is increased to Leave space for heat to spread. Nevertheless, increasing the distance between two adjacent N-doped regions 16 will result in an increase in the feature size of the memory cell, so how to break between the channel length and the thermal budget to balance the component electrical requirements and avoid sacrificing flash memory. The feature size of the unit is still one of the difficulties that conventional techniques must overcome. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a non-volatile memory, <<>> to completely avoid the problem of the size limit of memory cells due to thermal budgets in the prior art. In a preferred embodiment of the present invention, the non-volatile memory comprises a bottom portion of a plurality of data storage elements disposed above the substrate, a plurality of controls being disposed over the data storage element, and the insulating layer is in a plurality of controls = The surface and the sidewalls, and the bit line, span across a plurality of control gates f $ and are disposed on the insulating layer. 1 pole

Since the non-volatile memory of the present invention forms a bit line above the I to replace the conventional buried bungee, it is not necessary to use a method such as a heat treatment to make a buried bungee, thereby avoiding miscellaneous and forming channels. If the length is not enough, it can also avoid the size limitation of the miscellaneous solution. In addition, according to the power supply provided on the bit line, the bit line of the present invention can be used as the isolation structure between the memory cells except for the memory unit, so the present invention is more η layer or shallow trench isolation. The structure is used as the field oxygen between the adjacent bits, and the present invention can be further applied to the nitride memory structure. SONOS respects the two-bit memory unit to provide a higher level of '', for example, a meta-array. . "度记忆泽1281249 [Embodiment] "Monthly reference to Fig. 2, Fig. 2 is an array of non-volatile memory of the present invention. As shown in FIG. 2, the non-volatile memory 30 includes a plurality of lines of words 'for example, WL0 WL WL31, and a plurality of bit lines, for example, BL0 〜 BL20 ' spanning over a plurality of word lines, and each of them A bit line and each word line intersect perpendicularly and define a brother cell, such as memory cell A, in its perpendicular intersection. In a preferred embodiment of the invention, • /, a memory cell string of the same bit line may comprise from about 16 to 32 memory cells. Referring again to Fig. 3, Fig. 3 is a schematic cross-sectional view showing the non-volatile memory/cutting line 33' shown in Fig. 2. As shown in FIG. 3, the non-volatile core body 30 includes a substrate 32, an oxide layer 34 is disposed on the surface of the substrate 32, and a plurality of lean storage elements 36a, 36b v 36c are disposed on the surface of the oxide layer 34. The oxide layer 38 is disposed over the data storage elements 36a, 36b, 36c, and a plurality of control gates 40a, 40b, 40c are disposed over the oxide layer 38. In addition, the non-volatile memory 3 includes an insulating layer covering the surface and sidewalls of the control gates 40a, 40b, 40c, and a bit line 44 is disposed above the control gates 40a, 40b, 40c. On the surface of the insulating layer 42. In a preferred embodiment of the invention, substrate 32 can be a p-type 底 base N-well or a P-well. The data storage elements 36a, 36b, 36c may be floated with doped polycrystalline material to store 1281249 storage element data in each memory unit, or the tributary storage component shirt, application, or * may also be a nitride layer In order to store - bit or binary data in each memory unit. In other embodiments of this & month, the data storage component can be formed, teared, 36c can also be formed from other materials that can store electrons, and the insulating layer 42 can be used as the data storage component 36a, 36b and the bit line 44. isolation. # Further, the control gates 40a, 4仙, 4〇c are respectively defined by a plurality of parallel word lines, and the bit line 44 is a plurality of parallel words spanning the definition control gates 40a, 40b, 40c. One bit line above the line, and the control gates 40a, 40b, 40c and the bit line 44 may be selected from doped polysilicon or other semiconductor material/conductor material for controlling the operation of each memory unit. . As for the insulating layer 42, it may be a rock oxide layer or a nitrogen layer to isolate the bit line 44 from other components, for example, as a separation between the bit line 44 and the control gates 40a, 40b, 40c, or Depending on the actual demand, the bit line _ is isolated from the data storage elements 36a, 36b, 36c or from the surface of the substrate 32. In the process, the insulating layer 42 may be a single or composite deposited layer, and may also include a top protective layer and a sidewall substructure. Please refer to the cross-sectional view of the non-volatile memory shown in the second diagram of the brother 4, which is shown by the tangential line 44'. As shown in FIG. 4, the non-volatile memory 30 includes a material layer such as an oxide layer 34, a data storage element 36, an oxide layer 38, a control gate 40, and an insulating layer 42 stacked in sequence above the substrate %, 1281249 and plural The strip lines 44a, 44b, 44c are provided on the surface of the insulating layer 42. The bit lines 44a, 44b, and 44c are a plurality of parallel bit lines, and the bit lines 44a, 44b, and 44c respectively define a plurality of adjacent memories with the control gates 4 and the data storage elements 36 below. unit. Please refer to the following three examples for the operation of the non-volatile memory of the present invention. In the first embodiment shown in Figs. 5 and 6, the non-volatile Luijimen body 30 is injected into the tunnel tunneling hot hole using the F〇wier_Nordheim tunneling mechanism. -to-band tunneling induced hot-hole injection (BTBTHH) mechanism for performing a program to remove electrons from selected memory cells, as well as non-volatile memory 3 erase operations Electron is injected into the selected memory cell using the Fullerox mechanism. For example, when the electrons are to be removed from the selected data storage element 36b in the direction indicated by the fifth arrow, the operation mode is applied to the control gate 40b above the data storage element 36b. The negative voltage Vwl is preferably between _5 乂 -15 volts, preferably -6 volts, and the bit line 44 above the data storage element 36b and other control gates of the common bit line 44 (eg, the control gate 40a, 40c) Applying a positive voltage VBL, Vpass, respectively, is recommended to be between +5V and +10V, preferably +6V. When a positive voltage is applied across bit line 44, an inversion layer 45 is formed on the surface of substrate 32 below bit line 44 for conducting the bit line voltage to the source/drain of the memory cell. In the preferred embodiment of the invention 1281249 + 4, the 'inversion layer 45 can apply a positive voltage V 10.5V to +5V, so that the gates of the selected memory cells are::, about 5.5V, to satisfy the brown The operation of Lenohan tunneling mechanism. The difference is up to the contract, and it is considered to be the same as the memory line of the memory line of the same-bit line. I am out of the extreme voltage of the selected memory unit. Xiang Shi =,, and determine the pressure difference between the gate 40b and its 汲 extremes, so that the direction of electricity, broken selection 46 from the selected data storage component 36b ^ r to arrow, better operational efficiency, when Applied to double digits to remove by single recall. In order to make it possible for the cell to be selectively formed on the surface of the substrate 32 - buried: 'each field' to define a buried wave / source in the miscellaneous region for a little positive voltage, such as ... 5V, which is more than +4 = ^ The pressure difference between the field gate 40b and its 汲 extreme. ^A control is in the direction indicated by arrow 48 in Fig. 6, when the electronic 4, the beak is stored in the element 36b, the operation mode is based on the control gate above the data storage element 36b, applying a positive voltage For the v machine, it is recommended to say that the V~ is preferably +1W' and the bit line 44 above the data storage element and the other control gates of the bit line 44 are grounded. The high voltage applied to the selected gate lion is intended to cause the substrate 32 to be in-reverse layer 45' and electrons can be injected into the selected data storage element 36b in the direction indicated by arrow 48. 12 1281249 As shown in the second embodiment of FIGS. 7 and 8, the non-volatile memory 30 is programmed by a band-to-band tunneling hot electron injection mechanism to inject electrons into the selected memory cell. As for the erasing operation of the non-volatile memory 30, the Fullerhan tunneling mechanism can be used to remove electrons from the selected memory unit. For example, in the direction indicated by arrow 50 in FIG. 7, when electrons are to be injected into the selected data storage element 36b, the operation mode is such that a positive voltage VWL is applied to the control gate 40b above the data storage element 36b. It is suggested that it is between +5V and +15V, preferably +6V, and is applied to the bit line 44 above the data storage element 36b and the other control gates of the common bit line 44 (for example, the control gates 40a, 40c). a negative voltage VBL,

Vpass, it is recommended to be between -5V and -10V, preferably -6V. When a negative voltage is applied to the bit line 44, an inversion layer 45 is formed on the surface of the base 32 below the bit line 44 for use. Conduct the bit line voltage to the source/drain of the memory cell. In a preferred embodiment of the invention, the inversion layer 45 can apply a negative voltage VBLi of about -4.5V to -5V to bring the gate-drain voltage difference of the selected memory cell to about 10.5V. The bit line 44 can be regarded as a transmission gate of a memory cell string sharing the same bit line, and defines the 汲 extreme voltage of the selected memory cell. The electrons can be injected into the selected data storage element 36b in the direction indicated by arrow 50 using the differential pressure applied between the selected control gate 40b and its drain. In order to achieve better operational efficiency, when applied to a dual-bit memory cell, each memory cell can selectively form a buried doped region on the surface of the substrate 32 to define a buried drain/source, and A small negative voltage is provided in the buried doped region, for example, 1281249 - IV~-5V' is preferably -4.5V to increase the voltage difference between the control gate 4〇b and its drain terminal. In the direction indicated by arrow 52 in Fig. 8, when the electrons are to be removed from the selected tributary storage element 36b, the mode of operation is applied to the control gate 4b above the data storage element 36b. The voltage vWL is preferably between -5V and -15V, preferably _6V, and provides a positive voltage on the substrate 32, and the lub is between +5V and +10V', preferably +6V. The difference in pressure applied between the selected control gate 40b and the substrate 32 causes the surface of the substrate 32 to form an inversion layer 45' and the electrons can be removed from the selected data storage element 36b in the direction indicated by arrow 52. . *. ; * ....

As shown in the third embodiment shown in FIGS. 9 and 10, the non-volatile memory 30 is programmed using the Fullerton random wear system to inject electrons into the selected memory cell as to non-volatile. The memory 3 erase operation 10 can use the Fullerhan tunneling mechanism to remove electrons from the selected memory cells. For example, in the direction indicated by arrow 54 in Fig. 9, when electrons are to be injected into the selected data storage element 36b, the operation mode is applied to the control gate 4b above the data storage element 36b. The voltage Vwl is preferably between +10V and +15V, preferably +.15V, the bit line 44 above the data storage element 36b and other control gates of the common bit line 44 (eg, control gates 40a, 40c) Apply a lower voltage vBL, V respectively

Pass, it is recommended to be between +5V and +8V, preferably +8V, and ground the substrate 32. Volume 14 1281249 provides a positive ^>献士面奋#, a sputum, and a base 45 below the bit line 44, which is 45° μ, to conduct the core voltage to the memory unit =:: The preferred implementation of the present invention is as follows: ^ = the gate voltage of the Wei memory cell _ & the interelectrode pressure difference reaches about 15V, in order to meet the operation of the Fleurnohan wearing the β ^ ^ tooth. Applying to the selected control voltage will cause electrons to be injected into the remotely accessed data storage component 36b in the direction of the arrow. As shown in Fig. 10, in the direction indicated by 56, when the electrons are to be removed from the selected data storage component, the operation mode is 4% of the control gate applied above the thank-you 36b - negative voltage V It is recommended to be between -10 V and -, preferably seven v, and the substrate 32 is grounded. The negative voltage applied to the selected control gate 听 hears that the surface of the substrate 32 forms an inversion layer 45. The electrons are removed from the selected data storage element 36b in the direction indicated by the tiger 56. It should be noted that the non-volatile memory of the present invention can utilize bit lines as a memory cell-age structure. For example, when operating a memory cell on bit line 44, a voltage value of -ον may be provided on a bit line on both sides of bit line 44 to isolate bit line 44 or be selected using these bit fields. Memory Cell 'The present invention can omit the fabrication of a field oxide layer or a shallow trench isolation structure as an isolation structure between adjacent bit lines. In practical applications, the present invention can connect each bit line to a different driving circuit 15 1281249, and then use an individual driving circuit to control the supply to each bit =, or this (4) can also call a single line Wm: several lines The switching of the supply voltage of the bit line: the structure = π demand and at the same time, the isolated junction and the source terminal are interchangeable, so that the voltage swap is not extremely eliminated, so as to satisfy the double-bit memory unit.

Please refer to FIG. 11 , the cross section of the front V memory (1) 1 is a non-volatile 30 ° # 11 ® Tibetan bungee 6G provided on the surface of the substrate 32, and a plurality of Buried 34 . t # 58 * ® ° 30 ^ ^ Gate storage element application ~ oxide layer 38, control

44 42 ^ .X is a p-type doped region Μ^ or -N-type well, and the buried dipole 60 can be a immersed 60 and has a phase-type hybrid region' and pushes the well 58 and the buried-auxiliary bit line. In the ^ conductivity type. The buried neopolar (9) can be regarded as facilitating the adjustment of memory simplification/郷6G to provide a suitable drum voltage value. The working voltage can be effectively applied to the control pole. 16 1281249 Please refer to [2, 12th The figure is a suggested value of the parameters of the non-volatile memory operating in the present invention. As shown in Fig. 12, the non-volatile memory is programmed on a selected memory cell (assumed to be an N-channel memory cell) by: providing a positive voltage to the bit line of the selected memory cell (VBL, seieeted = +6V), and ground the other bit lines (VBLunseieeted = 〇 v); provide a negative voltage # (Vwl - _6V) ' in the word line (control gate) of the selected memory cell Providing a positive voltage (Vpass=+6V) to other word lines; providing a positive voltage to the inversion layer below the selected bit line

(VSL=0V, Vwel corpse 0V) 〇 Ground the gamma and bottom of the memory unit of the county

The car is less than the familiar, μ?

A NAND type is provided above the word line, and the size is defined by the lithography and etching method 1281249, so that the word line and the bit line can satisfy the minimum design size, and the high density requirement of the 4F2 memory cell size is achieved. In addition, when the present invention performs a program operation on the selected memory unit, the other bit lines disposed on both sides of the selected memory unit can be grounded to form the isolation structure by using the grounded bit lines, and thus the present invention It is not necessary to fabricate a structure such as a field oxide layer or a shallow trench isolation as an isolation structure between adjacent bit lines. In addition, the non-volatile memory structure of the present invention can be applied to nitride memory to provide a higher density memory cell array of 2F2. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patentable scope of the present invention should be covered by the present invention. [Simple description of the drawing] ❿ Figure 1 is a schematic cross-sectional view of a conventional flash memory. Figure 2 is a schematic diagram of an array of non-volatile memory of the present invention. Fig. 3 is a schematic cross-sectional view showing the non-volatile memory shown in Fig. 2 along the tangential line 33'. Fig. 4 is a schematic cross-sectional view showing the non-volatile memory shown in Fig. 2 taken along a tangential line 44'. Fig. 5 and Fig. 6 are views showing the operation of the simplification/erasing of a non-volatile memory according to the first embodiment of the present invention. 18 1281249 Figures 7 and 8 are schematic diagrams showing the operation of stylizing/erasing a non-volatile memory in accordance with a second embodiment of the present invention. Fig. 9 and Fig. 10 are diagrams showing the operation of stiling/erasing a non-volatile memory in accordance with a third embodiment of the present invention. Figure 11 is a cross-sectional view showing a non-volatile memory of another embodiment of the present invention. Figure 12 is a suggested value of a parameter for operating a non-volatile memory of the present invention. [Main component symbol description] 10 Flash memory 12, 32 Substrate 14 P type and 16 N type doped regions 18, 22, 34, 38 Oxide layer 20 Floating gates 24, 40, 40a, 40b, 40c Control gate 30 non-volatile memory 36, 36a, 36b, 36c data storage element 42 insulating layer 44 ~ 44a > 44b, 44c bit line 45 inversion layer 46, 48, 50, 52, 54, 56 electron moving direction 19 1281249 58 doping well 60 buried bungee A memory cell BLO~BL20 bit line L channel area vpass, Vwl, VbL, VBL, i, voltage value ^BL, selected Λ ^BL, unselected ^BL,i,selected ' ^ BL, i, unselected VsL 'VwELL WLO ~ WL31 word line

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Claims (1)

1281249 X. Patent Application Range: 1. A non-volatile memory comprising: a substrate; a plurality of data storage components disposed above the substrate, wherein each of the data storage components is configured to store at least one meta-data; a control gate is disposed above the plurality of data storage elements to control the operation of the plurality of data storage elements by using Φ; an insulating layer covering the plurality of control gate surfaces and sidewalls; and a bit line crossing And above the plurality of control gates and disposed on the insulating layer. 2. The non-volatile memory of claim 1, wherein each of the data storage elements comprises a floating gate. 3. A non-volatile body of claim 1, wherein each of the material storage elements comprises a nitride layer. 4. For non-volatile memory as claimed in item 3 of the patent scope, each of the material storage elements may store two-dimensional data. 5. The non-volatile memory of claim 1 of the patent application, further comprising a buried doped region disposed on the surface of the substrate adjacent to each of the data storage elements. 6. The non-volatile memory of claim 5, wherein the substrate further comprises at least one doping well, the buried doped region is disposed in the doping well, and the doping well and the buried The doped regions have opposite conductivity patterns. 7. The non-volatile memory of claim 1, wherein the bit line and the plurality of control gates are formed of doped polysilicon. 8. The non-volatile memory of claim 1, wherein the insulating layer covers the sidewalls of the plurality of data storage elements. 9. A non-volatile memory, comprising: a substrate; a plurality of word lines disposed above the substrate; and a plurality of bit lines spanning the plurality of word lines, and wherein each of the bit lines Each word line intersects perpendicularly and defines a memory cell in its perpendicular intersection. 10. The non-volatile memory of claim 9, wherein the memory unit comprises a data storage component. 22 1281249 11. The non-volatile memory of claim 10, wherein the data storage element comprises a floating gate. 12. The non-volatile memory of claim 10, wherein the material storage element comprises a nitride layer. 13. The non-volatile memory of claim 12, wherein the data storage component stores bi-digit data. 14. The non-volatile memory of claim 9, wherein the memory cell comprises at least one buried doped region disposed on the surface of the substrate. 15. The non-volatile memory of claim 14, wherein the substrate further comprises at least one doping well, the buried doped region is disposed in the doping well, and the doping well and the buried type The doped regions have opposite conductivity types. 16. The non-volatile memory of claim 9 wherein the plurality of character lines are used to define a plurality of control gates. 17. The non-volatile memory of claim 9, further comprising at least one insulating layer disposed on a surface and a sidewall of the plurality of word lines. 23 1281249 18. The non-volatile memory of claim 9, wherein the plurality of bit lines comprise a source/drain of a selected memory cell. 19. The non-volatile memory of claim 9, wherein the plurality of bit lines comprise an isolation structure around the selected memory cell. 20. The non-volatile memory of claim 9, wherein the plurality of bit lines and the plurality of word lines comprise doped polysilicon. XI. Schema: 24